JP2002110818A - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can simplify the manufacture process and can reduce the occupation area of a memory cell at the same time, and its manufacturing method. SOLUTION: A MOS transistor for storage is constituted with an n+-type polycrystalline silicon film 12 as a gate electrode, with a silicon oxide film 17 as a gate insulating film, and with n+-type impurity diffusion layers 20 and 21, respectively, as a source region and a drain region. A diode is constituted by the pn junction between the n+-type polycrystalline silicon film 12 and the p+-type polycrystalline silicon film 13, and a MOS transistor MTr for transfer is constituted with an n+-type polycrystalline silicon film 16 as a gate electrode, with a silicon oxide film 19 as a gate insulating film, and with n+-type impurity diffusion layers 21 and 25, respectively, as a source region and a drain region, and these members are all buried in a trench 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a structure of a gain cell (Gain Cell) in which one memory cell is composed of two MOS transistors and one diode. is there.

[0002]

2. Description of the Related Art With the recent development of semiconductor manufacturing technology, miniaturization of semiconductor memory devices has been rapidly progressing. In particular, DR
In AM (Dynamic Random Access Memory), the miniaturization competition is intensifying. One memory cell of a conventional DRAM is composed of two elements, one transfer MOS transistor and one capacitor element. As the miniaturization of the DRAM advances, it is becoming difficult to secure the capacity of the capacitor element.

In order to solve the problem of securing the capacity of the capacitor element, a new memory cell structure has been proposed instead of the conventional one-transistor and one-capacitor structure, and one of them is a gain cell. The gain cell includes, for example, a conventional DRAM memory cell in which an element for amplifying a cell capacitor signal is added. As an example of one specific structure, a gain cell including two transistors and one diode is used. is there.

[0004] This structure will be described with reference to FIGS. 17 to 19. 17 is an equivalent circuit of a gain cell including two transistors and one diode, FIG. 18 is a plan pattern diagram thereof, and FIG. 19 is a cross-sectional view taken along line AA ′ in FIG.

As shown in the figure, one gain cell has a gate connected to a word line WL and a drain connected to a bit line B.
Transfer MOS transistor M connected to L
tr, the drain is connected to the source of the transfer MOS transistor Mtr, the source is connected to the power supply potential VDD, the storage MOS transistor Mst is connected to the gate of the storage MOS transistor, and the cathode is connected to the storage MOS transistor Mst. It is composed of a diode Di having an anode connected to the drain.

The MOS for transfer of the gain cell
The transistor Mtr and the storage MOS transistor Mst are connected to the active region AA (Active A
a gate electrode, each consisting of n ⁺ -type polycrystalline silicon film 120 provided through the silicon oxide film 110 serving as a gate insulating film on the rea), provided in a silicon substrate, source, and drain regions n ⁺ -type It is constituted by the impurity diffusion layer 130.

Further, the storage MOS transistor M
diode Di provided between the gate and drain of st
Is formed by a pn junction using the gate electrode 120 of the storage MOS transistor Mst as a cathode region and the p ⁺ -type polycrystalline silicon film 140 provided on the gate electrode 120 as an anode region.

Then, the p ⁺ type polycrystalline silicon film 140
The n ⁺ -type impurity diffusion layer 130 serving as the drain of the storage MOS transistor Mst is connected by a titanium silicide film 150 to form the gain cell shown in FIG.

Further, a silicon nitride film 160 is provided on the side walls of the gate electrodes of the transfer MOS transistor Mtr and the storage MOS transistor Mst, and an interlayer insulating film 170 is provided on the entire surface. Then, the metal wiring layer 180 provided on the interlayer insulating film 170 to be the bit line BL and the transfer MOS transistor Mtr
Is connected via a contact hole 190. The source region of the storage MOS transistor Mst is connected to the contact 2 by a wiring (not shown).
00 is connected to the power supply potential VDD.

[0010] The gain cell having the above structure is used for the silicon substrate 1.
A plurality of semiconductor memory devices are arranged in an array on the semiconductor memory device 00, and the gate electrodes 120 of the transfer MOS transistors of the gain cells arranged in the same column are commonly connected to the same word line WL. The gate electrode 120 of the storage MOS transistor Mst is provided independently in each gain cell.

As described above, the conventional structure has two MOS transistors.
By forming transistors in a plane direction on a silicon substrate, a gain cell having a configuration of two transistors and one diode has been realized.

However, arranging two MOS transistors on a plane causes the following problems.

(1) While the gate electrode of the transfer MOS transistor Mtr has a band-like pattern common to the gain cells arranged in the same column,
The gate electrode of the storage MOS transistor Mst has an isolated pattern that is independent for each gain cell. Therefore, it is very difficult to adjust the alignment to all the gate electrode patterns in the lithography process for processing these gate electrodes including the peripheral transistors.

(2) Storage MOS transistor M
Since the p ⁺ -type polycrystalline silicon film is provided on the gate electrode of st, the lithography process for processing the gate electrode described in (1) becomes more difficult.

(3) Storage MOS transistor M
A lithography step is also required for processing a titanium silicide film that connects the p ⁺ -type polycrystalline silicon film on the st gate electrode to the drain region. Then, it is very difficult to process the titanium silicide film so that the titanium silicide film is left over between the gate electrode and the source region which are designed with a minimum processing size.

(4) Storage MOS transistor M
It is necessary to connect the source region of st to the power supply potential VDD, and in addition to the wiring of the word line WL and the bit line BL of the conventional DRAM, a wiring for connecting to the power supply potential VDD is newly required.

As described above, forming two MOS transistors on a silicon substrate in a planar direction imposes a heavy burden on a lithography process, and further increases the number of wiring layers. For this reason, there is a problem that the process becomes complicated or the yield is reduced, and the manufacturing cost of the semiconductor memory device is increased and the reliability is deteriorated.

[0018]

As described above, in a DRAM composed of one MOS transistor and one capacitor element, it has become difficult to secure the capacity of the cell capacitor as miniaturization progresses. In order to solve this problem, a new memory cell structure called a gain cell has been proposed. One of the specific structures is a gain cell which forms a memory cell with two MOS transistors and one diode. In order to realize this gain cell, conventionally, two MOs of a transfer MOS transistor and a storage MOS transistor have been used.
An S transistor is formed in a plane direction on a semiconductor substrate, and a diode is formed by providing a gate electrode of a storage MOS transistor and an electrode of the opposite conductivity type on the gate electrode.

However, with such a configuration, the gate electrode of the transfer MOS transistor has a band-like pattern, whereas the gate electrode of the storage MOS transistor has an isolated pattern. Further, it is necessary to provide a semiconductor layer of a conductivity type opposite to that of the gate electrode on the gate electrode of the storage MOS transistor. Furthermore,
Wiring is required to connect between the gate electrode and the source region of the storage MOS transistor designed with almost the minimum processing size. These demands impose a great burden on the lithography process, which causes the process to be complicated and the yield to be reduced, thereby increasing the manufacturing cost of the semiconductor memory device and deteriorating the reliability. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a first object of the present invention is to provide a method of manufacturing a semiconductor memory device which can reduce a load on a lithography process and simplify a manufacturing process. .

A second object of the present invention is to provide a semiconductor memory device capable of simplifying a manufacturing process and reducing an area occupied by a memory cell, and a method of manufacturing the same.

[0022]

In order to achieve the above object, a semiconductor memory device according to a first aspect of the present invention includes a trench provided in a semiconductor substrate, a trench buried in the trench, and a source region. A storage MOS transistor to which a power supply voltage has been applied; and a storage MOS transistor buried in the trench, one electrode electrically connected to a gate electrode of the storage MOS transistor, and the other electrode connected to a drain of the storage MOS transistor. A diode connected to the region, embedded in the trench, a gate electrode connected to the word line, and a source region electrically connected to the other electrode of the diode;
A transfer MOS transistor having a drain region connected to a bit line;
One memory cell is composed of the S transistor, the diode, and the transfer transistor.

The structure of each element buried in the trench is, specifically, the storage MOS transistor is configured such that the inside of the trench provided in the semiconductor substrate of the first conductivity type is connected to the trench side wall. A first insulating film functioning as a gate insulating film is interposed between the first conductive film functioning as a gate electrode and the semiconductor substrate in contact with a region of the trench where the first conductive film is provided. And a first of a second conductivity type that functions as a source region.
An impurity diffusion layer, a second conductivity type second transistor provided in the semiconductor substrate that is separated from the first impurity diffusion layer and is in contact with at least a region of the trench where the first conductive film is provided, and that functions as a drain region. A second impurity diffusion layer, wherein the diode includes the first conductive film and the first conductive film.
The transfer MOS transistor is formed by joining the second conductive film electrically buried in the trench on the conductive film and electrically connected to the second impurity diffusion layer. A third conductive film functioning as a gate electrode, which is buried with a second insulating film functioning as a gate insulating film interposed therebetween and is electrically separated from the second conductive film;
Functions as the drain region of the S transistor,
A second impurity diffusion layer functioning as a source region of a transfer MOS transistor; and a second impurity diffusion layer provided in the semiconductor substrate separated from the second impurity diffusion layer and in contact with a region in the trench where the third conductive film is provided. And a third impurity diffusion layer of the second conductivity type functioning as a drain region.

In the method of manufacturing a semiconductor memory device according to the second invention, a step of forming a trench in a semiconductor substrate of a first conductivity type and a step of forming a trench in the semiconductor substrate near the bottom of the trench are provided. Forming a first impurity diffusion layer along a side wall from the bottom of the trench to a position higher than an upper end of the first impurity diffusion layer; Forming a first conductive film with the first insulating film interposed between trench sidewalls, forming a second conductive film in a trench above the first conductive film, and forming the first conductive film; Forming a second insulating film on the side wall of the trench from a position higher than an upper end of the second conductive film;
A third insulating film interposed between the third insulating film and the trench sidewall;
Forming a conductive film; and forming a second conductive film in the semiconductor substrate in contact with the trench in a region where the third conductive film is provided.
Forming a conductive type second impurity diffusion layer.

After the step of forming the second conductive film in the trench, a step of forming a fourth conductive film containing a second conductive type impurity in the trench on the second conductive film. Further comprising, in one or more steps requiring heating after the step of forming the fourth conductive film, diffusing impurities contained in the fourth conductive film into the semiconductor substrate; A third conductive type third conductive film is formed in the semiconductor substrate in contact with a trench in a region extending from the conductive film to the third conductive film.
An impurity diffusion layer may be formed.

According to the semiconductor memory device described in the first aspect of the invention, in a gain cell including three elements of a transfer MOS transistor, a storage MOS transistor, and a diode, these three elements are vertically formed in a trench. Embedded. for that reason,
The occupied area per gain cell can be reduced as compared with a conventional gain cell in which two MOS transistors are arranged on a plane.

Further, when compared with a conventional DRAM, the gain cell of the present invention is a DRA using a trench capacitor.
Since the M plane pattern can be used, a gain cell can be realized while keeping the same occupied area as the memory cell of the conventional DRAM. In this case, the existing technologies such as peripheral circuits used in the conventional DRAM can be used as they are.

In the present invention, the gain cell 3
Since all of the elements are buried in the trench, it is not necessary to form an element on the semiconductor substrate in addition to the trench. That is, a conventional D using a trench capacitor
The area occupied by the transfer MOS transistor in the RAM becomes unnecessary. As a result, the conventional DR
A gain cell can be realized with an area occupied by half of the AM memory cell.

According to the method of manufacturing a semiconductor memory device described in the second aspect, all the elements constituting the gain cell are buried in the trench. Therefore, since each element can be processed by filling and recess in the trench, the load on the lithography process can be greatly reduced as compared with the conventional method of manufacturing a gain cell.

The manufacturing process for embedding each element in a trench is performed by a conventional D type having a trench capacitor.
Many of the RAM manufacturing techniques can be used. Further, since no cell capacitor is required, the trench depth can be reduced, so that the respective manufacturing steps can be facilitated.

As described above, according to the first and second aspects of the present invention, the manufacturing process can be simplified and the manufacturing yield can be improved while reducing the area occupied by the gain cell composed of two MOS transistors and one diode. Therefore, the manufacturing cost of the semiconductor memory device can be reduced and the reliability can be improved.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. For this explanation,
Common parts are denoted by common reference symbols.

The semiconductor memory device according to the first embodiment of the present invention will be described with reference to FIGS. FIG.
3 are for explaining the gain cell according to the present embodiment, FIG. 1 is an equivalent circuit showing a configuration of one gain cell, FIG. 2 is a plan view of a semiconductor memory device having a plurality of gain cells, and FIG. FIG. 3 is a sectional view taken along line BB ′ in FIG. 2.

As shown in FIG. 1, one gain cell has two gain cells.
It is composed of three elements, one MOS transistor and one diode. That is, when the gate is the word line W
L, a transfer MOS transistor Mtr having a drain connected to the bit line BL, a storage MOS transistor Mst having a drain connected to the source of the transfer MOS transistor Mtr, and having a source connected to the power supply potential VDD. The storage MOS transistor is composed of a diode Di whose cathode is connected to the gate and whose drain is connected to the anode of the storage MOS transistor Mst.

In the gain cell having the above configuration, at the time of writing, the transfer MOS transistor Mtr is turned on and a voltage is applied to the bit line BL, similarly to the conventional DRAM. Then, since the diode Di is in a forward bias state, the storage MOS transistor Mst is turned on. MOS transistor M for transfer once
When tr is turned on, a forward bias is always applied to the diode Di by the power supply potential VDD. Therefore, even if the transfer MOS transistor Mtr is turned off, the storage MOS transistor Mst keeps on. Depending on the state of the storage MOS transistor Mst, "1" or "0" data is written.

At the time of reading, the transfer MOS transistor Mtr is turned on. MOS for storage
If the case where the transistor Mst is in the ON state is referred to as a “1” write state, the power supply potential VD is used when reading the “1”.
Since the region from D to the bit line BL is conductive, the potential of the bit line BL increases.

On the other hand, when "0" is read, the potential of the bit line BL does not change because the storage MOS transistor Mst is in the off state.

The structure of a semiconductor memory device having the above-described gain cell as a memory cell will be described with reference to FIGS.

As shown in the figure, element regions AA forming gain cells are arranged in a zigzag pattern in the p-type silicon substrate 10, and element isolation regions STI (Shallow) are formed in other regions.
Trench Isolation) is provided.

A trench 11 is provided at an end of the element region AA. The trench 11 has an n ⁺ -type polysilicon film 12, a p ⁺ -type polysilicon film 13, and an n ⁺ -type polysilicon film from the bottom. 14, silicon oxide film 15, and n ⁺
The polycrystalline silicon film 16 is sequentially buried.

A silicon oxide film 17 is provided on the side wall of trench 11 from the bottom to the height at which p ⁺ -type polycrystalline silicon film 13 is buried, and silicon oxide film 17 is provided at a region at which n ⁺ -type polycrystalline silicon film 14 is buried. A nitride film 18 is provided;
Further, a silicon oxide film 19 is provided in a region where the n ⁺ type polycrystalline silicon film 16 is embedded.

An n ⁺ -type impurity diffusion layer 20 is provided in the silicon substrate 10 around the trench 11 from the bottom of the trench 11 to the middle of the height at which the n ⁺ -type polycrystalline silicon film 12 is buried. ^An n ⁺ -type impurity diffusion layer 21 is also provided in the semiconductor substrate 10 around the trench 11 extending from the ⁺ -type polysilicon film 12 to the n ⁺ -type polysilicon film 16. The n ⁺ -type impurity diffusion layer 20 is connected to the power supply potential VDD by a wiring layer or a diffusion layer (not shown).

Further, on the active region AA of the silicon substrate 10 between the adjacent trenches 11, a band-shaped polycrystalline silicon film 23 extends in a direction orthogonal to the longitudinal direction of the element region AA via a silicon oxide film 22. A silicon nitride film 24 surrounds the polycrystalline silicon film 23. An n ⁺ -type impurity diffusion layer 25 is provided on the surface of the silicon substrate 10 in the active region AA.

Then, an interlayer insulating film 26 is provided so as to cover the entire surface of the silicon substrate 10 and the silicon nitride film 24, and a metal wiring layer 27 is provided on the interlayer insulating film 26. The metal wiring layer 27 is connected to the n ⁺ -type impurity diffusion layer 25 through a contact hole 28 provided in the interlayer insulating film 26.

In the above configuration, the area AREA1 shown by a broken line in FIGS. 2 and 3 constitutes one gain cell described with reference to FIG. That is, the n ⁺ -type polycrystalline silicon film 12 buried in the trench 11 becomes a gate electrode, the silicon oxide film 17 becomes a gate insulating film, and the n ⁺ -type impurity diffusion layers 20 and 21 become source and drain regions, respectively. Storage MOS transistor Mst
Is configured. Diode Di is storage MOS
The transistor Mst is formed by a pn junction of an n ⁺ -type polycrystalline silicon film 12 serving as a gate electrode of the transistor Mst and a p ⁺ -type polycrystalline silicon film 13 provided on the n ⁺ -type polycrystalline silicon film 12. In the transfer MOS transistor Mtr, the n ⁺ type polycrystalline silicon film 16 has a gate electrode,
The silicon oxide film 19 is configured such that the gate insulating film is used, and the n ⁺ -type impurity diffusion layers 21 and 25 are used as source and drain regions. The n ⁺ -type impurity diffusion layer 25 serving as the drain region of the transfer MOS transistor Mtr is connected to the metal wiring layer 27 through the contact hole 28.
, And the metal wiring layer 27 becomes the bit line BL. Further, a polycrystalline silicon film 23 provided on the n ⁺ -type polycrystalline silicon film 16 serving as a gate electrode of the transfer MOS transistor Mtr and extending in a band shape in a direction orthogonal to the longitudinal direction of the element region AA is formed as a word line. Functions as a WL (password line).

Note that, in the plan view of FIG.
The width of A in the word line WL direction is smaller than the width of the bit line BL. This is because priority has been given to the recognizability of the drawing, and it can be considered that both widths are the same.

As described above, the gain cell according to the present embodiment is formed in the trench 11 provided in the silicon substrate 10 so as to be sequentially buried and formed in the vertical direction.
It is composed of an OS transistor Mst, a diode Di, and a transfer MOS transistor. The element regions AA in which the gain cells are provided are arranged in a staggered pattern as shown in FIG. 2, and a trench in which each element constituting the gain cells is buried is provided at an end of the element region AA. Then, two word lines WL are arranged on one gain cell area of the element area AA. In the gain cell, one provided above the trench actually functions as a word line WL. The width of the word line is generally formed with a minimum processing dimension in the process. Then, the distance between the adjacent word lines WL, the width of the bit line BL, the trench width in the direction orthogonal to the longitudinal direction of the element region AA, and the distance between the adjacent element regions AA in the direction orthogonal to the longitudinal direction of the element region AA are also minimized. Designed with dimensions. Expressed wherein the minimum feature size in F, longitudinal width of the construction element region AA is 4F, in the direction of the width of 2F perpendicular to the longitudinal direction, the occupied area of one gain cell becomes 8F ^2. That is, it has the same size as a BEST (BuriEd STrap) cell using a trench capacitor in a conventional DRAM. As described above, realizing a gain cell without increasing the area occupied by one memory cell can be said to be a great advantage in a semiconductor memory device in which miniaturization is the most important issue in terms of cost. Furthermore, since the plane pattern is the same as that of the conventional DRAM, existing peripheral circuits such as a sense amplifier of a folded bit line system widely used in the DRAM can be applied as they are.

Next, a method for manufacturing the gain cell will be described with reference to FIGS. 4 to FIG.
FIG. 8 is a cross-sectional view sequentially showing the manufacturing steps, focusing on one gain cell.

First, as shown in FIG.
A silicon oxide film 30 by thermal oxidation or the like,
The silicon nitride films 31 are respectively formed by a (Chemical Vapor Deposition) method or the like. Then, the silicon nitride film 31, the silicon oxide film 30, and the silicon substrate 10 are sequentially processed by a lithography technique and an anisotropic etching technique such as a RIE (Reactive Ion Etching) method to form a trench 11. The short side of the opening of the trench 11 is designed with the current minimum processing dimension.

Next, as shown in FIG.
nic) is formed by the CVD method, and then the trench 1 is formed by lithography and etching.
1 down to the area where the source region of the storage MOS transistor Mst is to be formed. The insulating film 32 is, for example, A
SG (Arseno Silicate Glass) film or the like.

Subsequently, an insulating film is formed on the entire surface by the CVD method. Then, for example, at a temperature of 1000 in a nitrogen atmosphere.
C. annealing is performed. By this annealing, the insulating film 32
Is diffused into the silicon substrate 10 and becomes n ^{+ serving as} a source region of the storage MOS transistor Mtr.
Formed impurity diffusion layer 20 is formed. The formation of the insulating film can suppress the diffusion of As into regions other than the region where the n ⁺ -type impurity diffusion layer 20 is to be formed. Thereafter, the insulating film and the insulating film 32 are removed by isotropic etching to obtain a structure shown in FIG.

Next, a silicon oxide film 17 is formed on the entire surface. This silicon oxide film 17 functions as a gate insulating film of the storage MOS transistor Mtr. Further, an n ⁺ -type polycrystalline silicon film 12 doped with an n-type impurity such as As is formed on the entire surface. Then, the n ⁺ -type polycrystalline silicon film 12 is removed to the region where the gate electrode of the storage MOS transistor Mst is to be formed, thereby obtaining the structure of FIG. The removal of the n ⁺ -type polycrystalline silicon film 12 is performed, for example, by using a CMP (Chemical Chemical) using the silicon nitride film 31 as a stopper.
The polishing is performed by polishing using a mechanical polishing method and etching in the trench by using the RIE method. The n ⁺ type polycrystalline silicon film 12 is formed of a storage MOS transistor M
It functions as the st gate electrode and the cathode region of the diode Di.

Next, a p ⁺ -type polycrystalline silicon film 13 doped with a p-type impurity such as B (Boron) is formed on the entire surface, and is removed up to a region where the anode region of the diode Di is to be formed. obtain. This removing method is performed by the CMP method and the RIE method as in the case of the n ⁺ -type polycrystalline silicon film 12.

Then, the silicon oxide film 17 formed on the side wall of the trench 11 at a level above the p ⁺ -type polycrystalline silicon film 13 by wet etching, RIE, or the like.
Is removed. Subsequently, as shown in FIG. 9, by performing a heat treatment in a nitrogen atmosphere to nitride the sidewalls of the trenches 11, a silicon nitride film 18 is formed on the sidewalls of the trenches 11 from which the silicon oxide film 17 has been removed.

Next, as shown in FIG. 10, an n ⁺ -type polycrystalline silicon film 14 is formed on the entire surface, and is dropped to a region where the film is to be formed by the CMP method and the RIE method. Then, the silicon nitride film 18 remaining on the side wall of the trench 11 at a level above the n ⁺ -type polycrystalline silicon film 14 is removed by, for example, wet etching. Silicon nitride film 18
Changes the n ⁺ -type polycrystalline silicon film 14 in the trench 11 to R
When etching by the IE method, it plays a role of protecting the silicon substrate 10 on the side wall of the trench 11. Further, the n ⁺ -type polycrystalline silicon film 14 serves as a diffusion source of an impurity for forming the n ⁺ -type impurity diffusion layer 21 serving as a drain region of the storage MOS transistor Mst and a source region of the transfer MOS transistor Mtr. , For electrically connecting the n ⁺ -type impurity diffusion layer and the p ⁺ -type polycrystalline silicon film 13 serving as the anode electrode of the diode Di.

Next, TEOS (tetraethylorthosilicat)
e; LP (Low Pressure) -CV using Si (OC ₂ H ₅ ) ₄ )
A silicon oxide film 15 is formed by the D method or HDP (High Density Plasma) method to fill the trench 11. Then, as shown in FIG. 11, the silicon oxide film 15 is
By the P method and the RIE method, the trench is dropped into a region where the trench 11 is to be formed. Of course, CMP and RI
The method is not limited to the combination with the method E, and may be performed by, for example, wet etching.

Next, as shown in FIG.
A silicon oxide film 19 is formed on the side walls of the trench 11 by the D method or the like.
Is formed, and an n ⁺ -type polycrystalline silicon film 16 is further formed to fill the trench 11. This silicon oxide film 19
Functions as a gate insulating film of the transfer MOS transistor Mtr. The n ⁺ -type polycrystalline silicon film 16 functions as a gate electrode of the transfer MOS transistor Mtr. Thereafter, the n ⁺ -type polycrystalline silicon film 16 is dropped to the height of the surface of the silicon substrate 10 in the trench 11 by the CMP method and the RIE method.

Next, as shown in FIG.
Form a TI. This element isolation region STI is constituted by, for example, a trench buried with a silicon oxide film 29. Then, the silicon nitride film 31 on the silicon oxide film 30 is removed by wet etching or the like, and then n ⁺ -type impurities are introduced into the surface of the silicon substrate 10 in the element region AA by ion implantation or the like to diffuse the n ⁺ -type impurities. A layer 25 is formed. This n ⁺ type impurity diffusion layer 25
It functions as the drain region of the transfer MOS transistor Mtr. Further, the silicon oxide film 30 on the surface of the silicon substrate 10 is removed by etching, and a silicon oxide film 22 is newly formed on the surface of the silicon substrate 10 by a thermal oxidation method, a CVD method, or the like.

Then, as shown in FIG. 14, a word line WL of a polycrystalline silicon film 23 is formed on the silicon oxide film 22 and the trench 11. In FIG. 14, two polycrystalline silicon films 23 are provided in one gain cell, but what actually functions as a word line is the polycrystalline silicon film 23 on the trench 11, which is provided in the trench 11. It is electrically connected to a polycrystalline silicon film 16 functioning as a gate electrode of the transfer MOS transistor Mtr.

Further, a silicon nitride film 24 is formed so as to cover the side walls and the upper surface of polycrystalline silicon film 23.

The n-type impurities contained in the n ⁺ -type polycrystalline silicon film 14 buried in the trench 11 are diffused into the silicon substrate 10 by respective steps after the formation of the n ⁺ -type polycrystalline silicon film 14. I do. Thereby, the silicon substrate 10 over the n ⁺ -type polycrystalline silicon film 16 of n ⁺ -type polycrystalline silicon film 12 in the trench 11, as a source region and a drain region of the MOS transistor Mst Storage of the transfer MOS transistor Mtr A functioning n ⁺ -type impurity diffusion layer 21 is formed.
However, if it is possible to form the n ⁺ -type impurity diffusion layer 21 without using solid layer diffusion in which impurities are diffused from a diffusion source (n ⁺ -type polycrystalline silicon film 14) embedded in the trench, Of course, it is not necessary to form the n ⁺ -type polycrystalline silicon film 14 and the silicon nitride film 18.

Thereafter, BPSG (Boron Phosph
An interlayer insulating film 26 is formed from an orous silicate glass film or a silicon oxide film using TEOS, and a contact hole 28 connected to the n ⁺ -type impurity diffusion layer 25 is formed in the interlayer insulating film 26. Then, the structure is connected to n ⁺ -type impurity diffusion layer 25 through this contact hole to form metal wiring layer 27 serving as bit line BL, thereby completing the structure of FIG.

According to the above-described manufacturing process, the storage MOS transistor Mst, the diode Di, and the transfer MOS transistor Mtr are vertically embedded in the trench, and these elements are processed by, for example, a CMP method. It is possible to perform the recess by a combination of polishing by RIE and etching by RIE. Specifically, the processing after filling the trench with each member,
First, the member on the silicon substrate can be removed by a CMP method using the silicon nitride film 31 on the silicon substrate as a stopper, and then the etching can be performed by etching such as RIE using the silicon nitride film 31 as a mask. is there.
For this reason, a great burden is not imposed on the lithography process as in the related art, and the manufacturing process can be greatly simplified from the viewpoint of alignment at the time of lithography.

In many of the steps of vertically embedding each element in the trench, the manufacturing process of a conventional DRAM using a trench capacitor can be diverted, without complicating the manufacturing process. I'm done. Further, in the conventional DRAM, it is necessary to increase the trench depth in order to secure the capacitor capacity, and accordingly, it is difficult to maintain the filling property in the trench. However, a gain cell composed of two transistors and one diode does not require a capacitor element, so that it is not necessary to make the trench particularly deep. Therefore, processing of each member in the trench becomes very easy, and as a result, it is possible to improve the yield of the gain cell, improve the reliability, and reduce the manufacturing cost.

Next, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIGS. 15 and 16 are views for explaining the gain cell according to the present embodiment. FIG. 15 is a plan view of a semiconductor memory device having a plurality of gain cells, and FIG. 16 is a cross section taken along line CC ′ in FIG. FIG.

As shown, element regions AA forming gain cells are arranged in an array in the p-type silicon substrate 10, and element isolation regions STI are provided in other regions. As described in the first embodiment, the trench 11 in which the storage MOS transistor Mst, the diode Di, and the transfer MOS transistor Mtr forming the gain cell are sequentially buried is formed at the longitudinal end of the element region AA. Is provided. A word line WL is provided directly above the trench 11.

In the structure of this embodiment, the element region A
Since A is arranged in an array, the trenches of the respective gain cells arranged in the column direction in each row are all located in the same column. Therefore, the dummy word line WL does not exist on the element region AA, and the contact of the bit line BL is located between the word lines WL on the trench 11.

As a result, the area occupied by one gain cell is the area AREA2 shown by the broken line in FIGS. 15 and 16, and the width of the element area AA in both the longitudinal direction and the direction perpendicular to the longitudinal direction is only 2F. area single gain cell occupies becomes 4F ^2. That is, the area occupied by the gain cell can be reduced to half that of the memory cell in the conventional DRAM.

In other words, a semiconductor memory device having twice the storage capacity in the same area can be manufactured.
This can be said to be a very large breakthrough in semiconductor memory.

As described in the first and second embodiments, in the present invention, two transistors and one diode constituting a gain cell are buried vertically in a trench. The processing of each element in the trench can be performed by a recess such as a combination of a CMP method and an RIE method. Therefore, the burden on the lithography process can be significantly reduced. Furthermore, since many of the steps of burying each element in the trench can use the process of the conventional DRAM using the trench capacitor, the element can be formed without complicating the manufacturing process. Conversely, since the capacitor element is not used, the depth of the trench does not need to be particularly deep, and the trench filling property and the like are the same as those of the conventional type.
It can be said that it is superior to RAM. As described above, since the gain cell can be easily realized,
It is possible to improve the yield of the gain cell and reduce the manufacturing cost.

Further, since the plane pattern of the gain cell is the same as that of a conventional DRAM using a trench capacitor, the above-mentioned effect can be obtained without increasing the area occupied by the cell and the like. The used peripheral circuit can be used as it is. In addition, if the cells are arranged in an array, the occupied area of the cells in the conventional DRAM is reduced to one.
/ Placement of 2. It 4F ² is possible. That is, the degree of integration of the semiconductor memory device in the same area can be doubled.
One of the most important issues in a semiconductor memory device is the degree of integration, and the ability to greatly improve the degree of integration without complicating the manufacturing process is a very great advantage as a semiconductor memory device.

The purpose of the present invention is to form each element constituting the gain cell vertically in the trench, and a wide range of application is possible without departing from the purpose. For example, the diode connected between the gate and the drain of the storage MOS transistor is not limited to a pn junction diode.

For example, p in the first and second embodiments
^The heterojunction diode may be formed by replacing the ⁺ type polycrystalline silicon film 13 with a semiconductor material different from silicon, for example, SiC to form a heterojunction. In addition, a Schottky diode may be used instead of a semiconductor material instead of a metal material. In the metal / semiconductor junction, the barrier height changes depending on the impurity doping amount of the semiconductor. Therefore, the junction with the n ⁺ -type polycrystalline silicon film 12 is a Schottky contact, and the junction with the n ⁺ -type polycrystalline silicon film 14 is an ohmic contact. It is necessary to set the doping amount of the impurity to each polycrystalline silicon film so as to make contact.

Further, neither the manufacturing method described in the first embodiment nor the recess method of dropping each member into the trench, for example, is limited to the combination of the CMP method and the RIE method. It is not limited to the method shown in the example.

Further, the two MOS transistors for transfer and storage constituting the gain cell are not limited to the n-channel type as described in the embodiment, but may be p-type.
It goes without saying that a channel type may be used. In this case, the diode naturally has the opposite polarity to that of the embodiment, and the power supply potential VDD becomes a negative potential. In addition, the polycrystalline silicon film 14 serving as a diffusion source of an impurity contains a p-type impurity.

Note that the present invention is not limited to the above-described embodiment, and can be variously modified in an implementation stage without departing from the gist of the invention. Furthermore, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved and the effects described in the column of the effect of the invention can be solved. Is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention.

[0077]

As described above, according to the present invention, it is possible to provide a method of manufacturing a semiconductor memory device capable of reducing the load on the lithography process and simplifying the manufacturing process.

Further, according to the present invention, it is possible to provide a semiconductor memory device capable of simplifying a manufacturing process and reducing an area occupied by a memory cell, and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of a gain cell according to a first embodiment of the present invention.

FIG. 2 is a plan view of the gain cell according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the gain cell according to the first embodiment of the present invention, which is a cross-sectional view taken along line BB ′ of FIG. 2;

FIG. 4 is a sectional view showing a first manufacturing step of the gain cell according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing a second manufacturing step of the gain cell according to the first embodiment of the present invention.

FIG. 6 is a sectional view showing a third manufacturing step of the gain cell according to the first embodiment of the present invention.

FIG. 7 is a sectional view showing a fourth manufacturing step of the gain cell according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing a fifth manufacturing step of the gain cell according to the first embodiment of the present invention.

FIG. 9 is a sectional view showing a sixth manufacturing step of the gain cell according to the first embodiment of the present invention.

FIG. 10 is a sectional view showing a seventh manufacturing step of the gain cell according to the first embodiment of the present invention.

FIG. 11 is a sectional view showing an eighth manufacturing step of the gain cell according to the first embodiment of the present invention.

FIG. 12 is a sectional view showing a ninth manufacturing step of the gain cell according to the first embodiment of the present invention.

FIG. 13 is a sectional view showing a tenth manufacturing step of the gain cell according to the first embodiment of the present invention.

FIG. 14 is a sectional view showing an eleventh manufacturing process of the gain cell according to the first embodiment of the present invention.

FIG. 15 is a plan view of a gain cell according to a second embodiment of the present invention.

FIG. 16 is a cross-sectional view of the gain cell according to the second embodiment of the present invention, which is a cross-sectional view taken along line CC ′ of FIG. 15;

FIG. 17 is an equivalent circuit of a conventional gain cell.

FIG. 18 is a plan view of a conventional gain cell.

FIG. 19 is a cross-sectional view of a conventional gain cell, and is a cross-sectional view taken along line AA ′ of FIG.

[Explanation of symbols]

10, 100: silicon substrate 11: trench 12, 14, 16, 23, 120: n ⁺ type polycrystalline silicon film 13, 140: p ⁺ type polycrystalline silicon film 15, 17, 19, 22, 29, 110: silicon Oxide films 18, 24, 160: silicon nitride films 20, 21, 25, 130 ... n ⁺ type impurity diffusion layers 26, 170 ... interlayer insulating films 27, 180 ... metal wiring layers 28, 190 ... contact holes 150 ... titanium silicide film

Claims (11)

[Claims] 1. A trench provided in a semiconductor substrate, a storage MOS transistor buried in the trench and a power supply voltage applied to a source region, and one electrode buried in the trench. A diode electrically connected to the gate electrode of the storage MOS transistor and the other electrode connected to a drain region of the storage MOS transistor; and a diode buried in the trench, and a gate electrode connected to a word line. A transfer MOS transistor having a source region electrically connected to the other electrode of the diode, and a drain region connected to a bit line, wherein the storage MOS transistor, the diode, and the transfer transistor are connected to each other. One memo with three elements The semiconductor memory device characterized by forming a cell. 2. The storage MOS transistor has a first insulating film functioning as a gate insulating film interposed between the trench provided in the semiconductor substrate of the first conductivity type and a sidewall of the trench. A first conductive film that is buried and functions as a gate electrode; and a second conductive type first impurity that is provided in the semiconductor substrate in contact with a region of the trench where the first conductive film is provided and functions as a source region. A second diffusion layer that is provided in the semiconductor substrate that is separated from the first impurity diffusion layer and that is in contact with at least a region of the trench where the first conductive film is provided, and that functions as a drain region;
The diode is configured by a conductive type second impurity diffusion layer, wherein the diode is embedded in the first conductive film and the trench on the first conductive film, and is electrically connected to the second impurity diffusion layer. The transfer MOS transistor is buried in the trench with a second insulating film functioning as a gate insulating film interposed between the trench and a sidewall of the trench. 2
A third conductive film electrically separated from the conductive film and functioning as a gate electrode; and the second impurity diffusion layer functioning as a drain region of the storage MOS transistor and functioning as a source region of the transfer MOS transistor. A second conductivity type third impurity diffusion layer provided in the semiconductor substrate and separated from the second impurity diffusion layer and in contact with a region in the trench where the third conductive film is provided, and functioning as a drain region; 2. The semiconductor memory device according to claim 1, comprising: 3. The first insulating film further intervenes between the second conductive film and the side wall of the trench, and buries the trench between the second conductive film and the third conductive film. A fourth conductive film electrically separated from the third conductive film, wherein the second conductive film is electrically connected to the second impurity diffusion layer via the fourth conductive film. 3. The semiconductor memory device according to claim 1, wherein: 4. The semiconductor device according to claim 1, further comprising a fifth conductive film provided on the trench opening, electrically connected to the third conductive film, and functioning as the word line. The semiconductor memory device according to claim 1. 5. The semiconductor device according to claim 1, further comprising an interlayer insulating film provided on the semiconductor substrate, wherein the bit line is formed on the interlayer insulating film, and the bit line is formed through a contact hole provided in the interlayer insulating film. 3
5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to an impurity diffusion layer. 6. The fifth conductive film is provided at both ends of an element region provided in an array in the semiconductor substrate, and functions as a common word line for the element regions arranged in the same column. The contact hole is provided in the element region between the adjacent word lines, a width of the word line, a distance between the adjacent word lines,
6. The semiconductor memory device according to claim 5, wherein the length of the short side of the trench is a minimum processing dimension. 7. The fifth conductive film is provided at both ends of an element region provided in a zigzag pattern in the semiconductor substrate, and functions as a common word line for the element regions arranged in the same column. In the element region between the adjacent word lines, the word lines of the element regions adjacent in the row direction are extended, and the width of the word line and the distance between the adjacent word lines in the element region 6. The semiconductor memory device according to claim 5, wherein a length of a short side of said trench is a minimum processing dimension. 8. A step of forming a trench in a semiconductor substrate of a first conductivity type; a step of forming a first impurity diffusion layer of a second conductivity type in the semiconductor substrate near a bottom of the trench; Forming a first insulating film from the bottom along the side wall; and interposing the first insulating film between the trench and the side wall in the trench up to a position higher than the upper end of the first impurity diffusion layer. Forming a first conductive film; forming a second conductive film in a trench on the first conductive film; and forming the trench from a position higher than upper ends of the first insulating film and the second conductive film. Forming a second insulating film on a side wall; forming a third conductive film in the trench on the second conductive film with the second insulating film interposed between the trench and the side wall; The train in a region where the third conductive film is provided; Wherein in the semiconductor substrate, a method of manufacturing a semiconductor memory device characterized by comprising the step of forming a second impurity diffusion layer of a second conductivity type in contact with. 9. A step of forming a fourth conductive film containing a second conductive type impurity in the trench on the second conductive film after the step of forming the second conductive film in the trench. Further comprising, in one or more steps requiring heating after the step of forming the fourth conductive film, diffusing impurities contained in the fourth conductive film into the semiconductor substrate; 9. The method according to claim 8, wherein a third impurity diffusion layer of a second conductivity type is formed in the semiconductor substrate in contact with a trench in a region extending from the conductive film to the third conductive film. 10. The method according to claim 1, further comprising, before the step of forming a trench in the semiconductor substrate, the step of forming a mask material on the semiconductor substrate. Forming each of the trenches so as to reach a substrate, and embedding the first to third conductive films in the trenches; forming a conductive film on the semiconductor substrate and in the trenches, respectively; Polishing each of the conductive films using the mask material as a stopper and leaving only in the trench; and etching each of the conductive films remaining in the trench by etching using the mask material as a mask. 10. The method of manufacturing a semiconductor memory device according to claim 8, further comprising the step of removing the semiconductor memory device to a predetermined height in the trench. 11. A step of forming an element isolation region in the semiconductor substrate after the step of forming the second impurity diffusion layer, and forming a fifth conductive film functioning as a word line on the third conductive film Forming an interlayer insulating film on the semiconductor substrate; forming a contact hole in the interlayer insulating film that reaches the second impurity diffusion layer adjacent to the word line; 11. The method according to claim 8, further comprising: forming a metal wiring layer that is electrically connected to the second impurity diffusion layer via the contact hole on the insulating film and serves as a bit line. 2. A method for manufacturing a semiconductor memory device according to claim 1.