JP2002110771A - Semiconductor manufacturing apparatus - Google Patents

Semiconductor manufacturing apparatus

Info

Publication number
JP2002110771A
JP2002110771A JP2000298107A JP2000298107A JP2002110771A JP 2002110771 A JP2002110771 A JP 2002110771A JP 2000298107 A JP2000298107 A JP 2000298107A JP 2000298107 A JP2000298107 A JP 2000298107A JP 2002110771 A JP2002110771 A JP 2002110771A
Authority
JP
Japan
Prior art keywords
wafer
vertical
temperature
reactor
outer peripheral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000298107A
Other languages
Japanese (ja)
Other versions
JP4342096B2 (en
Inventor
Mikio Tanabe
幹雄 田辺
Toshimitsu Miyata
敏光 宮田
Wakako Shiratori
和賀子 白鳥
Katsunao Kasatsugu
克尚 笠次
Eiji Hosaka
英二 保坂
Kenji Ono
健治 大野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Kokusai Electric Inc
Original Assignee
Hitachi Kokusai Electric Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Kokusai Electric Inc filed Critical Hitachi Kokusai Electric Inc
Priority to JP2000298107A priority Critical patent/JP4342096B2/en
Publication of JP2002110771A publication Critical patent/JP2002110771A/en
Application granted granted Critical
Publication of JP4342096B2 publication Critical patent/JP4342096B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Chemical Vapour Deposition (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent slippage of a wafer support part produced due to excessive temperature difference by reducing the excessive temperature difference in a wafer, when high speed temperature increase and temperature decrease processing is conducted. SOLUTION: A semiconductor manufacturing device is provided with a vertical reactor, a heater for heating the water W inserted in the reactor provided so as to surround the outside, and a vertical boat 30 mounting a number of the wafers in a laminating state in the vertical direction to insert and remove them in the reactor and increases and decreases the temperature of the board of the inside of the reactor at a prescribed high speed. A plurality of ring holders 32 for mounting the wafers W at prescribed intervals in the vertical direction are provided on the vertical boat 30, a wafer-mounting recess part 34 having the level difference of the thickness of the wafer or thicker is provided on the upper face inner peripheral part of the ring holder 32, and a distance A from the outer peripheral edge of the ring holder 32 to the outer peripheral edge of the recess part 34 is set on the basis of a vertical interval H of the ring holder 32.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、一般の昇温・降温
速度よりも高速で昇温・降温を行う高速昇温降温速度炉
を反応炉として備えた縦型拡散装置や縦型CVD装置等
の半導体製造装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical diffusion apparatus, a vertical CVD apparatus, and the like having, as a reaction furnace, a high-speed heating / cooling rate furnace for heating / cooling at a higher speed than a general heating / cooling rate. A semiconductor manufacturing apparatus.

【0002】[0002]

【従来の技術】従来の縦型拡散装置や縦型CVD装置等
の半導体製造装置では、縦型の反応炉に対しウェーハ
(基板)を出し入れする手段として縦型ボートを使用し
ており、縦型ボートに多数のウェーハを水平姿勢で上下
方向に多段に搭載して処理を行っている。
2. Description of the Related Art In a conventional semiconductor manufacturing apparatus such as a vertical diffusion apparatus or a vertical CVD apparatus, a vertical boat is used as a means for taking a wafer (substrate) into and out of a vertical reaction furnace. A large number of wafers are mounted on a boat in a horizontal position in multiple stages in the vertical direction for processing.

【0003】図3は従来の半導体製造装置の一例を示し
ている。図3において、1は縦型反応炉、2は該縦型反
応炉1の上端部に設けられたガス吹出口、3はガス吹出
口2に処理ガスを送り込むガス供給路、4は縦型反応炉
1の下部に設けられたガス排出路、5は縦型反応炉1の
下端開口を塞ぐボートキャップ、10はキャップ5上に
載せられた縦型ボートである。縦型反応炉1の周囲に
は、図示しないが、縦型反応炉1内の雰囲気を加熱する
ヒータが設けられている。
FIG. 3 shows an example of a conventional semiconductor manufacturing apparatus. In FIG. 3, reference numeral 1 denotes a vertical reactor, 2 denotes a gas outlet provided at the upper end of the vertical reactor 1, 3 denotes a gas supply path for feeding a processing gas into the gas outlet 2, and 4 denotes a vertical reactor. A gas discharge path 5 provided in the lower part of the furnace 1 is a boat cap for closing a lower end opening of the vertical reactor 1, and 10 is a vertical boat mounted on the cap 5. Although not shown, a heater for heating the atmosphere in the vertical reactor 1 is provided around the vertical reactor 1.

【0004】ウェーハ(基板)Wは、縦型ボート10に
水平姿勢で搭載された形で、反応炉1の内部に装入され
る。図4は従来の半導体製造装置に使用されている縦型
ボートの構成を示している。この縦型ボート10は、図
4(a)に示すように、上下端にリング状の端板12、
13を配し、上下の端板12、13間に、3・4本の支
柱14を円周方向に所定の間隔をあけて互いに平行に立
設したものである。各支柱14の内側面には、図4
(b)に示すように、上下方向に一定の間隔で多数のス
リット15を水平に形成することにより、半導体ウェー
ハWの周縁部を支持する多数のウェーハ保持爪16が突
設されており、各ウェーハ保持爪16上に半導体ウェー
ハWを載せることで、上下方向に多数のウェーハWを積
層状態で搭載できるようになっている。
[0004] A wafer (substrate) W is loaded into the reactor 1 in a form mounted on a vertical boat 10 in a horizontal posture. FIG. 4 shows a configuration of a vertical boat used in a conventional semiconductor manufacturing apparatus. As shown in FIG. 4A, the vertical boat 10 has ring-shaped end plates 12 at upper and lower ends.
13 are arranged, and three or four columns 14 are erected in parallel with each other at predetermined intervals in the circumferential direction between the upper and lower end plates 12 and 13. As shown in FIG.
As shown in (b), a large number of slits 15 are formed horizontally at regular intervals in the vertical direction, so that a large number of wafer holding claws 16 for supporting the peripheral portion of the semiconductor wafer W are provided in a protruding manner. By mounting the semiconductor wafer W on the wafer holding claws 16, a large number of wafers W can be mounted in a stacked state in the vertical direction.

【0005】ウェーハWは、例えば処理ガスを、ガス供
給路3→ガス吹出口→反応炉1内→ガス排出路4の順路
で流しながら高温雰囲気下で処理される。
The wafer W is processed in a high-temperature atmosphere while, for example, flowing a processing gas in the order of a gas supply path 3 → a gas outlet → the inside of the reactor 1 → a gas discharge path 4.

【0006】[0006]

【発明が解決しようとする課題】ところで、半導体デバ
イスの高集積化に伴い、サーマルバジェットの低減やス
ループットの向上を図るために、従来の縦型拡散装置や
縦型CVD装置において高速での昇温・降温処理が必要
になってきた。
However, in order to reduce the thermal budget and improve the throughput with the increase in the degree of integration of semiconductor devices, the temperature of a conventional vertical diffusion apparatus or vertical CVD apparatus is increased at a high speed.・ Temperature lowering treatment has become necessary.

【0007】しかし、通常の縦型反応炉に用いられてい
る、図4に示すようなボート10を用いて高速昇温・降
温処理を行った場合、昇温・降温時にウェーハW面内に
大きな温度差が生じるという問題があった。例えば、8
インチウェーハの場合、ウェーハ間隔5.2mmで昇温
・降温速度を50℃/minとした場合、約60℃以上の温
度差が生じることがあった。この場合、昇温時には凹面
状の温度分布(中央部が低温で周辺部が高温の温度分
布)となり、降温時には凸面状の温度分布(中央部が高
温で周辺部が低温の温度分布)となる。
However, when a high-speed temperature raising / lowering process is performed by using a boat 10 as shown in FIG. 4, which is used in a normal vertical reactor, a large amount of water is left in the wafer W during the temperature raising / lowering. There is a problem that a temperature difference occurs. For example, 8
In the case of an inch wafer, a temperature difference of about 60 ° C. or more may occur when the temperature rise / fall rate is 50 ° C./min at a wafer interval of 5.2 mm. In this case, when the temperature rises, the temperature distribution becomes concave (temperature distribution is low at the center and the temperature is high at the periphery), and when the temperature falls, the temperature distribution becomes convex (temperature distribution is high at the center and the temperature is low at the periphery). .

【0008】このような過大な温度差がウェーハ面内に
生じた場合、その温度差によってウェーハ内に熱応力が
発生してウェーハWに撓みが生じ、ウェーハ保持爪16
上においてウェーハWにスリップが発生するという問題
があった。
When such an excessive temperature difference occurs in the wafer surface, the temperature difference generates a thermal stress in the wafer, causing the wafer W to bend, and the wafer holding claws 16
Above, there was a problem that a slip occurred in the wafer W.

【0009】このウェーハ面内に過大な温度差が生じる
原因について検討してみたところ、積層状態に搭載して
あるウェーハWの間隔が狭いために、ウェーハの外周側
からの輻射加熱によりウェーハが不均一に加熱されるこ
とに原因があることが分かった。
When the cause of the excessive temperature difference in the wafer surface was examined, the interval between the wafers W mounted in a stacked state was narrow, and the wafer was not radiated by radiant heating from the outer peripheral side of the wafer. It was found that there was a cause for the uniform heating.

【0010】即ち、昇温時には、ウェーハは、ウェーハ
の外周側にあるヒータ(加熱源)からの輻射熱によって
加熱されるが、ウェーハの上下間隔が狭いので、ウェー
ハ全面に均等に輻射熱が行き渡らない。まず、ヒータの
輻射熱によってウェーハ外周部が加熱され、熱伝導によ
ってウェーハ外周部から、温度の低いウェーハ中心部に
熱が伝わり、ある時間経過後にウェーハ全面が均一な温
度になるのであるが、ヒータによる昇温速度がウェーハ
面内における熱伝導による熱の移動速度よりも速いため
に、ウェーハ全面の温度均一化が遅れ、ウェーハ面内に
凹面状の温度分布が生じることになる。
That is, when the temperature is raised, the wafer is heated by radiant heat from a heater (heating source) on the outer peripheral side of the wafer. However, since the vertical interval between the wafers is small, the radiant heat does not spread evenly over the entire surface of the wafer. First, the outer peripheral portion of the wafer is heated by the radiant heat of the heater, and heat is transmitted from the outer peripheral portion of the wafer to the lower central portion of the wafer by heat conduction. After a certain period of time, the entire surface of the wafer has a uniform temperature. Since the rate of temperature rise is faster than the speed of heat transfer due to heat conduction in the wafer surface, the temperature uniformity over the entire wafer is delayed, and a concave temperature distribution occurs in the wafer surface.

【0011】また、降温時には、昇温時とは逆に、ウェ
ーハ外周部へ入射する輻射熱量が時間と共に減少し、且
つ、ウェーハ外周部から対流や熱伝導によって外部に熱
が逃げることによって、ウェーハ周辺部がウェーハ中心
部よりも速く温度が低下するが、温度の高いウェーハ中
心部からウェーハ外周部への熱伝導による熱の移動速度
が、ヒータによる降温速度より遅いために、ウェーハ面
内の温度均一化が遅れて、ウェーハ面内に凸面状の温度
分布が生じることになる。
In addition, when the temperature is lowered, the amount of radiant heat incident on the outer peripheral portion of the wafer decreases with time, and the heat escapes from the outer peripheral portion of the wafer to the outside by convection or heat conduction. Although the temperature of the peripheral part decreases faster than the central part of the wafer, the speed of heat transfer by heat conduction from the central part of the wafer to the peripheral part of the wafer is lower than that of the heater. The delay in homogenization causes a convex temperature distribution in the wafer surface.

【0012】本発明は、上記事情を考慮し、通常より高
速で昇温・降温処理を行う場合に、ウェーハ面内の過大
な温度差を低減し、過大な温度差によって発生するウェ
ーハ支持部のスリップを防止することのできる半導体製
造装置を提供することを目的とする。
In view of the above circumstances, the present invention reduces an excessive temperature difference in a wafer surface when performing a temperature increase / decrease process at a higher speed than usual, and reduces a wafer supporting portion generated by the excessive temperature difference. An object of the present invention is to provide a semiconductor manufacturing apparatus capable of preventing a slip.

【0013】[0013]

【課題を解決するための手段】請求項1の発明は、下端
開口より基板の搬入出が行われる縦型反応炉と、該縦型
反応炉の外側を囲繞するように設けられ反応炉内に挿入
された基板を加熱するヒータと、上下方向に多数の基板
を積層状態で搭載して前記縦型反応炉内に出し入れされ
る縦型ボートとを備え、前記ヒータを制御することによ
り所定の高速度で反応炉内の基板を昇温及び降温させる
半導体製造装置において、前記縦型ボートに、基板を上
下方向に所定の間隔で載置する複数のリングホルダを設
け、このリングホルダの上面内周部に基板の厚み以上の
段差を持つ基板載置部を設け、リングホルダの外周縁か
ら基板載置部の外周縁までの距離をリングホルダの上下
方向の間隔に基づて設定したことを特徴としている。
According to the first aspect of the present invention, there is provided a vertical reactor in which substrates are loaded and unloaded from a lower end opening, and a vertical reactor which is provided so as to surround the outside of the vertical reactor. A heater that heats the inserted substrate; and a vertical boat that mounts and stacks a large number of substrates in the vertical direction and that is inserted into and out of the vertical reaction furnace. In a semiconductor manufacturing apparatus that raises and lowers the temperature of a substrate in a reaction furnace at a speed, the vertical boat is provided with a plurality of ring holders on which substrates are mounted at predetermined intervals in a vertical direction, and an inner peripheral surface of an upper surface of the ring holder. The substrate mounting part having a step larger than the thickness of the substrate is provided in the part, and the distance from the outer edge of the ring holder to the outer edge of the substrate mounting part is set based on the vertical distance of the ring holder. And

【0014】従来の縦型ボートを使用して、ウェーハ
(基板)を高速昇温・降温処理した場合、ウェーハ面内
に過大な温度差が生じ、ウェーハの支持部にスリップが
発生する。この温度差が生じる原因は、ウェーハ面内へ
の輻射加熱の不均一性に起因して、熱伝導によるウェー
ハ面内の温度均一化速度が、ヒータの昇温・降温速度に
追従できないためである。
When a wafer (substrate) is heated and cooled at a high speed using a conventional vertical boat, an excessive temperature difference occurs in the wafer surface, and a slip occurs in a wafer support portion. The cause of this temperature difference is that, due to the non-uniformity of the radiant heating in the wafer surface, the temperature uniformization speed in the wafer surface due to heat conduction cannot follow the temperature rise / fall speed of the heater. .

【0015】そこで、上述の請求項1の発明では、ヒー
タからウェーハの外周面への熱輻射を遮る「壁」をボー
トに設けている。即ち、ボートに、基板を上下方向に所
定の間隔で載置する複数のリングホルダを設けて、この
リングホルダの上面内周部に基板の厚み以上の段差を持
つ基板載置部を設け、基板載置部の外側の肉厚部分を輻
射熱を遮る「壁」として機能させている。
In view of the above, according to the first aspect of the present invention, the boat is provided with "walls" for blocking heat radiation from the heater to the outer peripheral surface of the wafer. That is, a boat is provided with a plurality of ring holders on which substrates are mounted at predetermined intervals in the vertical direction, and a substrate mounting portion having a step greater than the thickness of the substrate is provided on the inner peripheral portion of the upper surface of the ring holder. The thick part outside the mounting part functions as a "wall" that blocks radiant heat.

【0016】こうすることで、高速昇温時に、ウェーハ
外周部に入射する輻射熱量を制限することができると共
に、高速降温時に、ウェーハ外周部からの熱の逃げ(放
熱)を軽減することができる。
By doing so, it is possible to limit the amount of radiant heat incident on the outer peripheral portion of the wafer when the temperature is raised at a high speed, and to reduce the escape of heat (radiation) from the outer peripheral portion of the wafer when the temperature is decreased at a high speed. .

【0017】また、このようにウェーハの外周部を取り
囲むようにリング状の「壁」が存在することにより、ウ
ェーハが上下のリングホルダの隙間から入射する輻射熱
のみを受けることになる。そこで、請求項1の発明で
は、前記リング状の「壁」の厚さ、つまり、リングホル
ダの外周縁から基板載置部の外周縁までの距離を、リン
グホルダの上下方向の間隔に基づいた所定値に設定する
ことで、上下のリングホルダの隙間を通して基板の外周
部に入射する熱線の入射角を所定値以下に制限し、ウェ
ーハ外周部への輻射熱の入射を極力低減するようにして
いる。
Further, since the ring-shaped "wall" surrounds the outer peripheral portion of the wafer, the wafer receives only the radiant heat incident from the gap between the upper and lower ring holders. Therefore, in the invention of claim 1, the thickness of the ring-shaped “wall”, that is, the distance from the outer peripheral edge of the ring holder to the outer peripheral edge of the substrate mounting portion is based on the vertical interval of the ring holder. By setting to a predetermined value, the incident angle of the heat ray incident on the outer peripheral portion of the substrate through the gap between the upper and lower ring holders is limited to a predetermined value or less, and the incidence of radiant heat on the outer peripheral portion of the wafer is reduced as much as possible. .

【0018】その結果、ウェーハの外周に「壁」がある
場合は、「壁」がない場合よりも、少ない輻射熱量でウ
ェーハ外周部が加熱されることになる。つまり、昇温時
は、温度の低いウェーハ中心部にウェーハ外周部から熱
伝導によって熱が伝わり、ウェーハ全面が均一な温度と
なるのであるが、「壁」があることによって、ウェーハ
外周部に入射する輻射熱量が低減されるために、増加輻
射熱量の時間的変化が小さくなり、温度上昇率の時間的
変化も小さくなり、ウェーハ外周部と中心部の温度差
が、「壁」がない場合よりも小さくなる。
As a result, when there is a “wall” on the outer periphery of the wafer, the outer peripheral portion of the wafer is heated with a smaller amount of radiation heat than when there is no “wall”. In other words, when the temperature rises, heat is transmitted from the outer peripheral portion of the wafer to the lower central portion of the wafer by heat conduction, so that the entire surface of the wafer has a uniform temperature. Because the amount of radiant heat to be reduced is reduced, the temporal change of the increased radiant heat is small, the temporal change of the temperature rise rate is also small, and the temperature difference between the wafer outer peripheral portion and the central portion is smaller than when there is no `` wall ''. Is also smaller.

【0019】一方、降温時は、入射する輻射熱量が少な
いために、減少輻射熱量の時間変化も「壁」がないとき
より小さくなり、ウェーハ外周部の輻射による温度減少
率も小さくなる。また、リングホルダの熱容量をウェー
ハとほぼ同等の熱容量をもつように設定した場合は、リ
ングホルダに入射する輻射熱量が、ウェーハに入射する
輻射熱量よりも大きくなるので、ちょうどウェーハの外
周部に熱の壁ができた状態となり、ウェーハの外周部か
ら外部への熱の逃げを軽減することができ、ウェーハ中
心部の温度の時間的変化とウェーハ外周部の温度の時間
的変化との差が小さくなる。つまり、ウェーハ面内の温
度差が減少する。
On the other hand, when the temperature is lowered, since the amount of incident radiant heat is small, the time change of the reduced radiant heat is smaller than when there is no "wall", and the rate of temperature decrease due to radiation at the outer peripheral portion of the wafer is also small. In addition, when the heat capacity of the ring holder is set to have substantially the same heat capacity as that of the wafer, the amount of radiant heat incident on the ring holder becomes larger than the amount of radiant heat incident on the wafer. Walls are formed, the escape of heat from the outer periphery of the wafer to the outside can be reduced, and the difference between the temporal change in the temperature at the center of the wafer and the temporal change in the temperature at the outer periphery of the wafer is small. Become. That is, the temperature difference in the wafer surface decreases.

【0020】[0020]

【発明の実施の形態】以下、本発明の実施形態を図面に
基づいて説明する。図1は実施形態の半導体製造装置と
しての縦型CVD装置の概略構成を示す断面図である。
この縦型CVD装置20においては、中空のヒータ21
内に均熱管22を介して縦型反応炉23が設置され、反
応炉23内に挿入したウェーハWを外周側から加熱でき
るようになっている。均熱管22は熱容量が大きい材料
から構成され、炉内の温度均一性を保つために使用され
ている。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view illustrating a schematic configuration of a vertical CVD apparatus as a semiconductor manufacturing apparatus according to an embodiment.
In this vertical CVD apparatus 20, a hollow heater 21 is provided.
A vertical reaction furnace 23 is installed therein via a soaking tube 22 so that the wafer W inserted into the reaction furnace 23 can be heated from the outer peripheral side. The heat equalizing tube 22 is made of a material having a large heat capacity, and is used for maintaining temperature uniformity in the furnace.

【0021】反応炉23にはガス導入通路24が設けら
れ、ガス導入通路24の先端が、反応炉23の天井部に
あるガスシャワー室25に接続されている。また、反応
炉23の下部には排気通路26が設けられており、ガス
シャワー室25から反応炉23内に吹き出された処理ガ
スが、反応炉23内を上から下に流れて、排気通路26
から炉外に排気されるようになっている。
The reaction furnace 23 is provided with a gas introduction passage 24, and the tip of the gas introduction passage 24 is connected to a gas shower room 25 at the ceiling of the reaction furnace 23. Further, an exhaust passage 26 is provided at a lower portion of the reaction furnace 23, and the processing gas blown out from the gas shower chamber 25 into the reaction furnace 23 flows through the inside of the reaction furnace 23 from the top to the bottom, and the exhaust passage 26 is formed.
From outside the furnace.

【0022】反応炉23は下端が開口して入口となって
おり、そこから縦型ボート30に装填された状態のウェ
ーハWを反応炉23に対し導入したり導出したりできる
ようになっている。ボート30は、ボートエレベータ
(図示せず)によって昇降されることにより、反応炉2
3内に導入され、また、反応炉23から取り出される。
ボート30はボートキャップ27上に立設されており、
ボートキャップ27は炉口蓋28上に設けられている。
The reaction furnace 23 has an opening with its lower end opened to serve as an entrance, from which the wafer W loaded in the vertical boat 30 can be introduced into or taken out of the reaction furnace 23. . The boat 30 is raised and lowered by a boat elevator (not shown), thereby
3 and taken out of the reaction furnace 23.
The boat 30 is erected on the boat cap 27,
The boat cap 27 is provided on the furnace lid 28.

【0023】この場合のボート30は、図2(a)、
(b)に示すように、3本(4本でもよい)の支柱31
に上下方向に一定の間隔をあけて、ウェーハWを載置す
るための多数枚の棚板状のリングホルダ32を取り付け
たものである。上下のリングホルダ23の間隔Hは、ツ
ィーザを挿入できる寸法(例えば2〜3mm)に設定さ
れており、各リングホルダ32の周方向の1箇所とリン
グホルダ32の内周部数カ所には、ツィーザの逃げとし
て切欠33A、33Bが設けられている。
The boat 30 in this case is shown in FIG.
As shown in (b), three (or four) columns 31 may be used.
A plurality of shelf-plate-shaped ring holders 32 for mounting wafers W are attached at regular intervals in the vertical direction. The interval H between the upper and lower ring holders 23 is set to a size (for example, 2 to 3 mm) into which the tweezers can be inserted, and the tweezers are provided at one location in the circumferential direction of each ring holder 32 and at several locations on the inner circumference of the ring holders 32. Cutouts 33A and 33B are provided as escapes for the above.

【0024】また、リングホルダ32の上面内周部に
は、ウェーハWの厚み以上の段差を持つウェーハ載置用
の凹部34が設けられている。このウェーハ載置用凹部
34で基板載置部を構成する。ウェーハWを凹部34の
底面34a上の定位置に載置するため、凹部34の周面
34bはテーパ面で構成されている。この場合、凹部3
4の径DはウェーハWの径より例えば2〜3mm程度大
きく設定されており、凹部34の幅tは例えば3〜4m
mに設定されている。また、リングホルダ32の外周縁
から凹部34の外周縁までの距離Aは、リングホルダ3
2の上下方向の間隔Hに基づいた所定値に設定されてい
る。例えば、リングホルダ32の上下間隔Hが小さいほ
ど、距離Aを小さくする。
In the inner peripheral portion of the upper surface of the ring holder 32, a concave portion 34 for mounting a wafer having a level difference larger than the thickness of the wafer W is provided. The wafer mounting concave portion 34 forms a substrate mounting portion. In order to place the wafer W at a fixed position on the bottom surface 34a of the concave portion 34, the peripheral surface 34b of the concave portion 34 is formed as a tapered surface. In this case, the recess 3
4 is set to be larger than the diameter of the wafer W by, for example, about 2 to 3 mm, and the width t of the concave portion 34 is set to, for example, 3 to 4 m.
m. The distance A from the outer peripheral edge of the ring holder 32 to the outer peripheral edge of the concave portion 34 is the ring holder 3.
It is set to a predetermined value based on the interval H in the up-down direction of No. 2. For example, the smaller the vertical interval H between the ring holders 32, the smaller the distance A.

【0025】ここで、凹部34の外周側の肉厚部分は、
ウェーハWの外周側にリング状の「壁」として存在する
部分であり、このリング状の「壁」の厚さAが、リング
ホルダ32の上下方向の間隔Hに基づいた所定値に設定
されることで、上下のリングホルダ32の隙間を通して
ウェーハWの外周部に入射する熱線の入射角θを所定値
以下に制限し、ウェーハ外周部へのヒータ21からの輻
射熱の入射を極力低減するようにしている。また、リン
グホルダ32の熱容量がウェーハWの熱容量とほぼ等し
くなるように、リングホルダ32の容積が設定されてい
る。この場合、距離Aを大きくすることで、入射角θを
小さくすることができる。また、距離Aを大きくするこ
とで、ウェーハWの周囲の熱容量を大きくすることがで
き、急冷時のウェーハ周囲の温度冷却を緩和することが
できるようになる。
Here, the thick portion on the outer peripheral side of the concave portion 34 is
This is a portion existing as a ring-shaped “wall” on the outer peripheral side of the wafer W, and the thickness A of the ring-shaped “wall” is set to a predetermined value based on the vertical interval H of the ring holder 32. Thus, the incident angle θ of the heat ray incident on the outer peripheral portion of the wafer W through the gap between the upper and lower ring holders 32 is limited to a predetermined value or less, and the incidence of radiant heat from the heater 21 to the outer peripheral portion of the wafer W is reduced as much as possible. ing. Further, the volume of the ring holder 32 is set such that the heat capacity of the ring holder 32 is substantially equal to the heat capacity of the wafer W. In this case, the incident angle θ can be reduced by increasing the distance A. In addition, by increasing the distance A, the heat capacity around the wafer W can be increased, and the temperature cooling around the wafer during rapid cooling can be eased.

【0026】なお、この装置においては、ヒータ21に
よる昇温速度が例えば+40℃/minの高速に設定され、
降温速度が例えば−20℃/minの高速に設定されてい
る。つまり、ウェーハ面内における熱伝導による熱の移
動速度よりも速い速度で昇温・降温が行われるように設
定されている。
In this apparatus, the heating rate by the heater 21 is set to a high speed of, for example, + 40 ° C./min.
The cooling rate is set to a high speed of, for example, -20 ° C./min. That is, the temperature is set to rise and fall at a speed higher than the speed of heat transfer by heat conduction in the wafer surface.

【0027】次に作用を説明する。ウェーハWの処理を
行う場合には、ウェーハWをボート30の各リングホル
ダ32の凹部34に載置し、ボートエレベータにより適
当な炉内温度に保持した反応炉23内に挿入する。次い
で、反応炉23内をガス交換すると共に炉内雰囲気を高
速で昇温させ、所定の温度を維持しながら、処理ガスを
反応炉23内に導入して、ウェーハWに所定の処理を施
す。次に反応炉23内を所定の高速で降温させ、所定温
度に下がったら、ボート30を炉外に取り出す。
Next, the operation will be described. When processing the wafer W, the wafer W is placed in the recess 34 of each ring holder 32 of the boat 30 and inserted into the reaction furnace 23 maintained at an appropriate furnace temperature by a boat elevator. Next, the inside of the reaction furnace 23 is exchanged with gas, and at the same time, the furnace atmosphere is heated at a high speed, and while maintaining a predetermined temperature, a processing gas is introduced into the reaction furnace 23 to perform predetermined processing on the wafer W. Next, the temperature inside the reaction furnace 23 is lowered at a predetermined high speed, and when the temperature has dropped to the predetermined temperature, the boat 30 is taken out of the furnace.

【0028】上記の高速昇温時には、ウェーハWを載置
している凹部34の外側の肉厚部分が、ヒータ21から
の輻射熱を遮る「壁」として機能するので、「壁」が存
在しない従来のボートを使用した場合よりも、少ない輻
射熱量でウェーハW外周部が加熱されることになる。つ
まり、昇温時は、温度の低いウェーハ中心部にウェーハ
外周部から熱伝導によって熱が伝わってウェーハ全面が
均一な温度となるのであるが、ウェーハWの外周に
「壁」があることによって、ウェーハ外周部に入射する
輻射熱量が低減されるため、増加輻射熱量の時間的変化
が小さくなり、温度上昇率の時間的変化も小さくなり、
ウェーハ外周部と中心部の温度差が、「壁」がない従来
の場合よりも小さくなる。
At the time of the above-mentioned high-speed heating, the thick portion outside the concave portion 34 on which the wafer W is placed functions as a "wall" for blocking the radiant heat from the heater 21, so that there is no conventional "wall". The outer peripheral portion of the wafer W is heated with a smaller amount of radiant heat than when the boat is used. In other words, at the time of temperature rise, heat is transmitted by heat conduction from the outer peripheral portion of the wafer to the lower central portion of the wafer, so that the entire surface of the wafer has a uniform temperature. Since the amount of radiant heat incident on the outer peripheral portion of the wafer is reduced, the temporal change of the increased radiant heat is reduced, and the temporal change of the temperature rise rate is also reduced,
The temperature difference between the outer peripheral portion and the central portion of the wafer is smaller than in the conventional case having no “wall”.

【0029】また、高速降温時には、入射する輻射熱量
が少ないために、減少輻射熱量の時間変化も「壁」がな
い従来のボートを使用した場合よりも小さくなり、ウェ
ーハ外周部の輻射による温度減少率も小さくなる。ま
た、リングホルダ32の熱容量がウェーハWとほぼ同等
の熱容量をもつように設定されているので、リングホル
ダ32に入射する輻射熱量が、ウェーハWに入射する輻
射熱量よりも大きくなり、ちょうどウェーハWの外周部
に熱の壁ができた状態となる。従って、ウェーハWの外
周部から外部への熱の逃げが軽減され、ウェーハ中心部
の温度の時間的変化とウェーハ外周部の温度の時間的変
化との差が小さくなり、ウェーハ面内の温度差が、
「壁」がない従来の場合よりも小さくなる。
At the time of high-speed cooling, the amount of incident radiant heat is small, so that the time variation of the reduced radiant heat is smaller than that in the case of using a conventional boat having no "wall", and the temperature decrease due to radiation at the outer peripheral portion of the wafer. The rate also gets smaller. Further, since the heat capacity of the ring holder 32 is set to have substantially the same heat capacity as that of the wafer W, the amount of radiant heat incident on the ring holder 32 becomes larger than the amount of radiant heat incident on the wafer W. A state in which a heat wall is formed on the outer peripheral portion of. Therefore, the escape of heat from the outer peripheral portion of the wafer W to the outside is reduced, and the difference between the temporal change of the temperature at the central portion of the wafer and the temporal change of the temperature at the outer peripheral portion of the wafer W is reduced, and the temperature difference within the wafer surface is reduced. But,
It is smaller than the conventional case without "walls".

【0030】そして、昇温・降温時のウェーハ面内温度
差を10〜20℃に低減することができるようになり、
ウェーハWに生じるストレスを低減できて、スリップの
発生を防止することができる。
Then, the temperature difference in the wafer surface at the time of raising and lowering the temperature can be reduced to 10 to 20 ° C.,
The stress generated on the wafer W can be reduced, and the occurrence of slip can be prevented.

【0031】なお、上記の実施形態では、本発明を縦型
CVD装置に適用した場合を示したが、本発明は縦型拡
散装置にも適用することができる。
In the above embodiment, the case where the present invention is applied to a vertical CVD apparatus has been described, but the present invention can also be applied to a vertical diffusion apparatus.

【0032】[0032]

【発明の効果】以上説明したように、本発明によれば、
多数の基板を搭載するボートに、基板を上下方向に所定
の間隔で載置する複数のリングホルダを設け、このリン
グホルダの上面内周部に基板の厚み以上の段差を持つ基
板載置部を設け、リングホルダの外周縁から基板載置部
の外周縁までの距離をリングホルダの上下方向の間隔に
基づいて設定したので、高速昇温時に基板の外周部に入
射する輻射熱を低減し、高速降温時に基板の外周部から
の放熱を低減することができ、高速昇温・降温時に基板
の面内に生じる温度差を小さくすることができる。従っ
て、通常よりも高速で昇温・降温処理する場合であって
も、スリップなしで半導体デバイス用の基板(ウェー
ハ)を生産することができ、スループットの向上が図れ
て、基板の低価格化を実現することができる。
As described above, according to the present invention,
On a boat on which a large number of substrates are mounted, a plurality of ring holders for mounting the substrates at predetermined intervals in the vertical direction are provided, and a substrate mounting portion having a step greater than the thickness of the substrate is provided on the inner peripheral portion of the upper surface of the ring holder. Since the distance from the outer edge of the ring holder to the outer edge of the substrate mounting portion is set based on the vertical spacing of the ring holder, radiant heat incident on the outer edge of the substrate during high-speed temperature rise is reduced, It is possible to reduce heat radiation from the outer peripheral portion of the substrate when the temperature is lowered, and to reduce the temperature difference generated in the surface of the substrate when the temperature is rapidly raised and lowered. Therefore, even when the temperature is raised or lowered at a higher speed than usual, a substrate (wafer) for a semiconductor device can be produced without slip, thereby improving the throughput and reducing the cost of the substrate. Can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態の半導体製造装置の概略構成
を示す断面図である。
FIG. 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor manufacturing apparatus according to an embodiment of the present invention.

【図2】同装置のボートの構成図で、(a)は図1のI
Ia−IIa矢視断面図、(b)は図2のIIb−II
b矢視断面図である。
FIG. 2 is a configuration diagram of a boat of the same apparatus, where (a) is the I of FIG. 1;
FIG. 2B is a sectional view taken along the line Ia-IIa, and FIG.
FIG.

【図3】従来の半導体製造装置の概略構成図である。FIG. 3 is a schematic configuration diagram of a conventional semiconductor manufacturing apparatus.

【図4】従来の半導体製造装置のボートの構成図で、
(a)は全体斜視図、(b)は(a)図のIVb矢視部
分の拡大図である。
FIG. 4 is a configuration diagram of a boat of a conventional semiconductor manufacturing apparatus;
4A is an overall perspective view, and FIG. 4B is an enlarged view of a portion taken along line IVb in FIG.

【符号の説明】[Explanation of symbols]

20 縦型CVD装置 21 ヒータ 23 反応炉 30 ボート 32 リングホルダ 34 凹部 W ウェーハ(基板) Reference Signs List 20 vertical CVD apparatus 21 heater 23 reactor 30 boat 32 ring holder 34 recess W wafer (substrate)

フロントページの続き (72)発明者 白鳥 和賀子 東京都中野区東中野三丁目14番20号 国際 電気株式会社内 (72)発明者 笠次 克尚 東京都中野区東中野三丁目14番20号 国際 電気株式会社内 (72)発明者 保坂 英二 東京都中野区東中野三丁目14番20号 国際 電気株式会社内 (72)発明者 大野 健治 東京都中野区東中野三丁目14番20号 国際 電気株式会社内 Fターム(参考) 4K030 FA10 GA02 KA04 KA23 LA15 5F031 CA02 FA01 FA12 HA64 HA65 MA28 5F045 BB01 DP19 EK06 EK30 EM08Continuing on the front page (72) Inventor Wakako 3-14-20 Higashinakano, Nakano-ku, Tokyo International Electric Co., Ltd. (72) Inventor Eiji Hosaka 3--14-20 Higashi-Nakano, Nakano-ku, Tokyo International Electric Co., Ltd. Reference) 4K030 FA10 GA02 KA04 KA23 LA15 5F031 CA02 FA01 FA12 HA64 HA65 MA28 5F045 BB01 DP19 EK06 EK30 EM08

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 下端開口より基板の搬入出が行われる縦
型反応炉と、該縦型反応炉の外側を囲繞するように設け
られ反応炉内に挿入された基板を加熱するヒータと、上
下方向に多数の基板を積層状態で搭載して前記縦型反応
炉内に出し入れされる縦型ボートとを備え、前記ヒータ
を制御することにより所定の高速で反応炉内の基板を昇
温及び降温させる半導体製造装置において、 前記縦型ボートに、基板を上下方向に所定の間隔で載置
する複数のリングホルダを設け、該リングホルダの上面
内周部に基板の厚み以上の段差を持つ基板載置部を設
け、前記リングホルダの外周縁から前記基板載置部の外
周縁までの距離をリングホルダの上下方向の間隔に基づ
いて設定したことを特徴とする半導体製造装置。
A vertical reactor for loading and unloading substrates from a lower end opening; a heater provided to surround the outside of the vertical reactor and heating a substrate inserted into the reactor; A vertical boat which is loaded with a large number of substrates in a stacked state in the direction and is taken in and out of the vertical reactor, and controls the heater to raise and lower the temperature of the substrates in the reactor at a predetermined high speed. In the semiconductor manufacturing apparatus, the vertical boat is provided with a plurality of ring holders on which substrates are placed at predetermined intervals in a vertical direction, and a substrate mounting having a step at least equal to the thickness of the substrate on the inner peripheral portion of the upper surface of the ring holder. A semiconductor manufacturing apparatus, wherein a mounting portion is provided, and a distance from an outer peripheral edge of the ring holder to an outer peripheral edge of the substrate mounting portion is set based on a vertical interval of the ring holder.
JP2000298107A 2000-09-29 2000-09-29 Semiconductor manufacturing apparatus, vertical boat, and semiconductor manufacturing method Expired - Lifetime JP4342096B2 (en)

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JP2000298107A JP4342096B2 (en) 2000-09-29 2000-09-29 Semiconductor manufacturing apparatus, vertical boat, and semiconductor manufacturing method

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JP2002110771A true JP2002110771A (en) 2002-04-12
JP4342096B2 JP4342096B2 (en) 2009-10-14

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007099786A1 (en) * 2006-02-23 2007-09-07 Hitachi Kokusai Electric Inc. Substrate processing apparatus and semiconductor device manufacturing method
CN109904058A (en) * 2017-12-11 2019-06-18 有研半导体材料有限公司 A method of reducing silicon polished front edge damage

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007099786A1 (en) * 2006-02-23 2007-09-07 Hitachi Kokusai Electric Inc. Substrate processing apparatus and semiconductor device manufacturing method
US8012888B2 (en) 2006-02-23 2011-09-06 Hitachi Kokusai Electric Inc. Substrate processing apparatus and semiconductor device manufacturing method
JP5043826B2 (en) * 2006-02-23 2012-10-10 株式会社日立国際電気 Substrate processing apparatus and semiconductor device manufacturing method
CN109904058A (en) * 2017-12-11 2019-06-18 有研半导体材料有限公司 A method of reducing silicon polished front edge damage

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