JP2002110727A - Method for manufacturing vertical mos transistor - Google Patents
Method for manufacturing vertical mos transistorInfo
- Publication number
- JP2002110727A JP2002110727A JP2000295899A JP2000295899A JP2002110727A JP 2002110727 A JP2002110727 A JP 2002110727A JP 2000295899 A JP2000295899 A JP 2000295899A JP 2000295899 A JP2000295899 A JP 2000295899A JP 2002110727 A JP2002110727 A JP 2002110727A
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- Prior art keywords
- source
- mos transistor
- vertical mos
- transistor
- chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、縦型ＭＯＳトラン
ジスタの製造方法に関し、特に、縦型ＭＯＳトランジス
タの製造コストを低減する製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a vertical MOS transistor, and more particularly, to a method of manufacturing a vertical MOS transistor at a reduced cost.
【０００２】[0002]
【従来の技術】従来の縦型ＭＯＳトランジスタを搭載し
た半導体チップの平面図を図２に示す。図２に示すよう
に、半導体チップ２００のトランジスタ領域２５１のソ
ース電極群に対して単一のソースパッド２０１を設け、
単一のソースパッド２０１を通して縦型ＭＯＳトランジ
スタの動作をテスターで確認し、良品とされた半導体チ
ップ２００のソースパッド２０１をボンディングワイヤ
２０４により、ゲートパッド２０５をボンディングヤイ
ヤ２０６により、それぞれパッケージのソース端子及び
ゲート端子と接続して、製品化していた。2. Description of the Related Art FIG. 2 is a plan view of a conventional semiconductor chip on which a vertical MOS transistor is mounted. As shown in FIG. 2, a single source pad 201 is provided for a source electrode group in a transistor region 251 of a semiconductor chip 200,
The operation of the vertical MOS transistor is confirmed by a tester through a single source pad 201, and the source pad 201 of the semiconductor chip 200, which has been regarded as a non-defective product, is connected to the bonding wire 204, the gate pad 205 is connected to the bonding wire 206, and the source terminal of the package is connected. And connected to the gate terminal.
【０００３】[0003]
【発明が解決しようとする課題】然るに、１チップ内で
１箇所でも欠陥のあるトランジスタがあればそのチップ
は不良となるためチップの歩留まり低下させ、結果とし
て製造コストの増大を招いていた。However, if there is a defective transistor even in one place in one chip, the chip becomes defective and the yield of the chip is reduced, resulting in an increase in manufacturing cost.
【０００４】本発明の目的は、縦型ＭＯＳトランジスタ
の製造方法において、チップ内に欠陥のあるトランジス
タを含む場合であっても、チップを良品として救済でき
る確率を高くし、結果として製造コストを低減できる縦
型ＭＯＳトランジスタの製造方法を提供することにあ
る。An object of the present invention is to increase the probability that a chip can be remedied as a non-defective product even when a defective transistor is included in a chip in a method of manufacturing a vertical MOS transistor, thereby reducing the manufacturing cost. An object of the present invention is to provide a method for manufacturing a vertical MOS transistor.
【０００５】[0005]
【課題を解決するための手段】本発明の縦型ＭＯＳトラ
ンジスタの製造方法は、一導電型の半導体基板をドレイ
ン、前記半導体基板の表面に形成した複数の逆導電型領
域をベース、前記ベース内に形成した一導電型領域をソ
ース、前記半導体基板表面に形成した第１絶縁膜をゲー
ト絶縁膜、前記ゲート絶縁膜の上にあって前記ソース及
び前記半導体基板に横方向に挟まれたベースを覆うゲー
ト電極、前記ドレインを半導体基板の裏面から取り出す
ドレイン電極、前記ゲート電極を一括して外部へ取り出
すゲート用パッド、前記ソースを所定の数に区分して、
区分された領域に含まれるソースを一括して取り出すソ
ース用パッドを備える縦型ＭＯＳトランジスタのチップ
に対して、前記ソース用パッドに接続する縦型ＭＯＳト
ランジスタのうち、正常に動作する良品縦型ＭＯＳトラ
ンジスタのみを前記チップ内で選別し、前記ゲート用パ
ッドの他に、前記良品縦型ＭＯＳトランジスタに接続す
るソース用パッドに対してソースリード端子との間でボ
ンディングを行い、前記良品縦型ＭＯＳトランジスタ以
外の不良品縦型ＭＯＳトランジスタに接続するソース用
パッドに対してはボンディングを行わないことを特徴と
し、前記不良品縦型ＭＯＳトランジスタに接続するソー
ス用パッドには、不良であることを示す不良印が印され
ており、前記チップを、印されている不良印のモード毎
にグループ分けし、前記グループ毎にグループに対応し
たボンディングプログラムを用いてボンディングを行
う、というものである。According to the present invention, there is provided a method of manufacturing a vertical MOS transistor, comprising the steps of: draining a semiconductor substrate of one conductivity type; a plurality of regions of opposite conductivity type formed on the surface of the semiconductor substrate; The source is a region of one conductivity type formed in the above, a first insulating film formed on the surface of the semiconductor substrate is a gate insulating film, and a base on the gate insulating film and laterally sandwiched between the source and the semiconductor substrate. A gate electrode to be covered, a drain electrode to take out the drain from the back surface of the semiconductor substrate, a gate pad to take out the gate electrode to the outside in a lump, and dividing the source into a predetermined number,
For a vertical MOS transistor chip having a source pad for taking out sources included in the divided regions at once, a non-defective vertical MOS transistor normally operating among the vertical MOS transistors connected to the source pad. Only the transistor is selected in the chip, and in addition to the gate pad, bonding is performed between a source lead terminal and a source pad connected to the non-defective vertical MOS transistor. The bonding is not performed to the source pad connected to the defective vertical MOS transistor other than the defective product, and the source pad connected to the defective vertical MOS transistor is defective. The chips are marked and the chips are grouped according to the mode of the marked defect. And bonding is performed using a bonding program corresponding to the group for each of the groups, is that.
【０００６】上記の縦型ＭＯＳトランジスタの製造方法
は、前記ドレイン電極は、チップを収容するパッケージ
のチップ搭載領域を通して外部に取り出され、また、前
記パッケージは、３端子のリード有するパッケージであ
り、前記パッケージは、放熱板を有するというものであ
る。In the above-mentioned method for manufacturing a vertical MOS transistor, the drain electrode is taken out through a chip mounting region of a package accommodating a chip, and the package is a package having three-terminal leads. The package has a heat sink.
【０００７】[0007]
【発明の実施の形態】本発明は、縦型ＭＯＳＦＥＴの製
造方法に関し、ソース電極を複数に分割し、選択的にワ
イヤボンディングを行って、従来不良となっていたチッ
プをグレード分けすることにより、良品として製品化す
ることができることを特徴とする。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a method for manufacturing a vertical MOSFET, in which a source electrode is divided into a plurality of parts and selectively wire-bonded to classify chips which have been defective in the past. It can be commercialized as a good product.
【０００８】次に、本発明の実施形態について、図１を
参照して説明する。図１（ａ）は、本実施形態の製造方
法を説明するための縦型ＭＯＳＦＥＴの平面図であり、
図１（ｂ）は、図１（ａ）の切断線Ａ−Ａ’における断
面図である。Next, an embodiment of the present invention will be described with reference to FIG. FIG. 1A is a plan view of a vertical MOSFET for explaining a manufacturing method of the present embodiment.
FIG. 1B is a cross-sectional view taken along a cutting line AA ′ in FIG.
【０００９】縦型ＭＯＳＦＥＴは、以下のような構造を
有している。The vertical MOSFET has the following structure.
【００１０】まず、図１（ａ）に示すように、縦型ＭＯ
ＳＦＥＴを搭載した半導体チップ１００は、ソース電極
群を２分割して、それぞれ第１トランジスタ領域５１及
び第２トランジスタ領域５２とする。第１トランジスタ
領域５１のソース電極群及び第２トランジスタ領域５２
のソース電極群に対して、外部端子との接続用にそれぞ
れ第１ソースパッド１及び第２ソースパッド２が設けら
れる。図においては、第１トランジスタ領域５１のソー
ス電極群の中に不良の個所が含まれているために、第１
ソースパッド１の上に不良印３がインクにより印されて
いる。First, as shown in FIG. 1A, a vertical MO
In the semiconductor chip 100 on which the SFET is mounted, the source electrode group is divided into two to form a first transistor region 51 and a second transistor region 52, respectively. Source electrode group of first transistor region 51 and second transistor region 52
Are provided with a first source pad 1 and a second source pad 2 for connection to external terminals. In the figure, the first transistor region 51 includes a defective portion in the source electrode group.
A defect mark 3 is marked on the source pad 1 with ink.
【００１１】従って、正常にトランジスタ動作する第２
トランジスタ領域５２は、第２ソースパッド２にボンデ
ィングしてパッケージのソース端子とボンディングワイ
ヤ４により接続される。Therefore, the second transistor which normally operates as a transistor can be used.
The transistor region 52 is bonded to the second source pad 2 and connected to the source terminal of the package by the bonding wire 4.
【００１２】半導体チップ１００には、上記の第１ソー
スパッド１及び第２ソースパッド２の他に、ゲートパッ
ド５が設けられており、ゲートパッド５にボンディング
してパッケージのゲート端子とボンディングワイヤ６に
より接続される。The semiconductor chip 100 is provided with a gate pad 5 in addition to the first source pad 1 and the second source pad 2 described above. Connected by
【００１３】以上の実施形態では、半導体チップ１００
のうち、第２トランジスタ領域５２のみが正常にトラン
ジスタ動作する例を説明したが、他に、半導体チップ１
００のうち第１トランジスタ領域５１のみが正常にトラ
ンジスタ動作するケース、第１トランジスタ領域５１及
び第２トランジスタ領域５２が共に正常にトランジスタ
動作するケースがあり、合計で３つのケースがある。In the above embodiment, the semiconductor chip 100
Among them, an example in which only the second transistor region 52 normally operates as a transistor has been described.
00, there is a case where only the first transistor region 51 normally operates as a transistor, and a case where both the first transistor region 51 and the second transistor region 52 operate normally as a transistor. There are three cases in total.
【００１４】第１トランジスタ領域５１のみが正常にト
ランジスタ動作するケースでは、第１ソースパッド１に
ボンディングしてパッケージのソース端子とボンディン
グワイヤにより接続され、第１トランジスタ領域５１及
び第２トランジスタ領域５２が共に正常にトランジスタ
動作するケースでは、第１ソースパッド１及び第２ソー
スパッド２共にボンディングしてパッケージのソース端
子とボンディングワイヤにより接続されることとなる。In the case where only the first transistor region 51 normally operates as a transistor, the first transistor region 51 and the second transistor region 52 are bonded to the first source pad 1 and connected to the source terminal of the package by a bonding wire. In the case where both operate normally as transistors, the first source pad 1 and the second source pad 2 are bonded together and connected to the source terminal of the package by a bonding wire.
【００１５】上記のようにソースパッド及びゲートパッ
ドがボンディングによりそれぞれパッケージのソース端
子及びゲート端子に接続されるボンディング工程の前
に、半導体チップ１００は、テスターによって３つの良
品グループに分けられる。ボンディング工程では、それ
らのグループ毎にボンディングプログラムを変えてボン
ディングを行い、例えば、第１トランジスタ領域５１及
び第２トランジスタ領域５２が共に正常にトランジスタ
動作する半導体チップは製品グループ１、第１トランジ
スタ領域５１のみが正常にトランジスタ動作する半導体
チップは製品グループ２、第２トランジスタ領域５２の
みが正常にトランジスタ動作する半導体チップは製品グ
ループ３にグループ分けされて製品出荷することとな
る。Prior to the bonding step in which the source pad and the gate pad are connected to the source terminal and the gate terminal of the package by bonding as described above, the semiconductor chip 100 is divided into three non-defective groups by a tester. In the bonding step, bonding is performed by changing a bonding program for each of the groups. For example, a semiconductor chip in which both the first transistor region 51 and the second transistor region 52 operate normally as transistors is the product group 1 and the first transistor region 51. Semiconductor chips that only normally operate as transistors operate in product group 2, and semiconductor chips in which only second transistor regions 52 operate normally as transistors are grouped into product group 3 and shipped as products.
【００１６】また、上述のパッケージは、具体的には、
例えば、３端子のリード有し、放熱板を有するパッケー
ジが挙げられる。The above-mentioned package is specifically,
For example, a package having three-terminal leads and having a heat sink may be mentioned.
【００１７】図１（ｂ）は、図１（ａ）の切断線Ａ−
Ａ’における断面図であり、縦型ＭＯＳＦＥＴの断面図
を示している。ここで、縦型ＭＯＳＦＥＴの構造を簡単
に説明しておく。FIG. 1B is a sectional view taken along a line A- in FIG.
It is sectional drawing in A ', and has shown sectional drawing of a vertical MOSFET. Here, the structure of the vertical MOSFET will be briefly described.
【００１８】まず、ｎ型エピタキシャル層を含むｎ型の
半導体基板２１の表面にｐ型のベース層２２を形成し、
ベース層２２を貫通して半導体基板２１に達するゲート
電極用の溝２３を掘り、溝２３の表面にはゲート酸化膜
２４を形成する。溝２３の両側のベース層２２にはｎ型
のソース層２５を形成する。溝２３にはゲート電極２６
が充填されてソース層２５の上方にまで延在するように
形成され、さらに、半導体チップ１００のゲートパッド
５に導出される。First, a p-type base layer 22 is formed on the surface of an n-type semiconductor substrate 21 including an n-type epitaxial layer,
A trench 23 for a gate electrode that penetrates the base layer 22 and reaches the semiconductor substrate 21 is dug, and a gate oxide film 24 is formed on the surface of the trench 23. An n-type source layer 25 is formed in the base layer 22 on both sides of the groove 23. The gate electrode 26 is formed in the groove 23.
Is formed so as to extend to above the source layer 25, and further to the gate pad 5 of the semiconductor chip 100.
【００１９】また、ソース電極２７は層間絶縁膜２８に
よりゲート電極２６から絶縁され、ソース電極２７を覆
う保護絶縁膜２９を開口して第２ソースパッド２が形成
される。さらに、第２ソースパッド２は、ボンディング
ワイヤ４によりパッケージのソース端子に接続される。The source electrode 27 is insulated from the gate electrode 26 by the interlayer insulating film 28, and the second source pad 2 is formed by opening a protective insulating film 29 covering the source electrode 27. Further, the second source pad 2 is connected to a source terminal of the package by a bonding wire 4.
【００２０】半導体チップ１００の底面は半導体基板２
１の底面であり、縦型ＭＯＳＦＥＴのドレインとして機
能する。半導体基板２１の底面は、パッケージの半導体
チップ搭載領域と接合金属により接続されており、さら
にパッケージのドレイン端子に導出される。The bottom surface of the semiconductor chip 100 is the semiconductor substrate 2
1 and functions as a drain of a vertical MOSFET. The bottom surface of the semiconductor substrate 21 is connected to a semiconductor chip mounting region of the package by a bonding metal, and is further led to a drain terminal of the package.
【００２１】縦型ＭＯＳＦＥＴを上記のような方法で製
造することにより、半導体チップ全体のソース電極群に
対して、単一のソースパッドを設けて製造する場合に比
べて、半導体チップの不良による廃棄率を減らすことが
でき、製品としての製造コストを下げることが可能とな
った。By manufacturing a vertical MOSFET by the above-described method, compared to a case where a single source pad is provided for a source electrode group of the entire semiconductor chip, the semiconductor chip is discarded due to defective semiconductor chips. The production rate as a product.
【００２２】上記の実施形態においては、半導体チップ
を２分割して製造する方法を示したが、電流容量特性の
許す限りの範囲において、３分割以上に拡張することも
できる。In the above embodiment, the method of manufacturing the semiconductor chip by dividing it into two parts has been described. However, the method can be extended to three or more parts as far as the current capacity characteristics allow.
【００２３】[0023]
【発明の効果】本発明の縦型ＭＯＳＦＥＴの製造方法に
よれば、半導体チップを２分割以上のトランジスタ領域
に分割し、それぞれのトランジスタ領域に対応するソー
スパッドを設け、複数のトランジスタ領域の内一つでも
良品があれば、そのトランジスタ領域に対応するソース
パッドをソース端子に接続して製品化するので、半導体
チップの不良による廃棄率を減らすことができ、製品と
しての製造コストを下げることが可能となった。According to the method of manufacturing a vertical MOSFET of the present invention, a semiconductor chip is divided into two or more transistor regions, and a source pad corresponding to each transistor region is provided. If there is at least one non-defective product, the source pad corresponding to the transistor area is connected to the source terminal and the product is commercialized, so the rejection rate due to semiconductor chip failure can be reduced and the manufacturing cost as a product can be reduced It became.
【図１】本発明による実施形態の縦型ＭＯＳＦＥＴの平
面図及び断面図である。FIG. 1 is a plan view and a sectional view of a vertical MOSFET according to an embodiment of the present invention.
【図２】従来の縦型ＭＯＳＦＥＴの平面図である。FIG. 2 is a plan view of a conventional vertical MOSFET.
１ 第１ソースパッド ２ 第２ソースパッド ３ 不良印 ４、６、２０４、２０６ ボンディングワイヤ ５、２０５ ゲートパッド ２１ 半導体基板 ２２ ベース層 ２３ 溝 ２４ ゲート酸化膜 ２５ ソース層 ２６ ゲート電極 ２７ ソース電極 ２８ 層間絶縁膜 ２９ 保護絶縁膜 ５１ 第１トランジスタ領域 ５２ 第２トランジスタ領域 １００、２００ 半導体チップ ２０１ ソースパッド ２５１ トランジスタ領域 DESCRIPTION OF SYMBOLS 1 1st source pad 2 2nd source pad 3 defect mark 4, 6, 204, 206 Bonding wire 5, 205 Gate pad 21 Semiconductor substrate 22 Base layer 23 Groove 24 Gate oxide film 25 Source layer 26 Gate electrode 27 Source electrode 28 Interlayer Insulating film 29 Protective insulating film 51 First transistor region 52 Second transistor region 100, 200 Semiconductor chip 201 Source pad 251 Transistor region
Claims (6)
半導体基板の表面に形成した複数の逆導電型領域をベー
ス、前記ベース内に形成した一導電型領域をソース、前
記半導体基板表面に形成した第１絶縁膜をゲート絶縁
膜、前記ゲート絶縁膜の上にあって前記ソース及び前記
半導体基板に横方向に挟まれたベースを覆うゲート電
極、前記ドレインを半導体基板の裏面から取り出すドレ
イン電極、前記ゲート電極を一括して外部へ取り出すゲ
ート用パッド、前記ソースを所定の数に区分して、区分
された領域に含まれるソースを一括して取り出すソース
用パッドを備える縦型ＭＯＳトランジスタのチップに対
して、前記ソース用パッドに接続する縦型ＭＯＳトラン
ジスタのうち、正常に動作する良品縦型ＭＯＳトランジ
スタのみを前記チップ内で選別し、前記ゲート用パッド
の他に、前記良品縦型ＭＯＳトランジスタに接続するソ
ース用パッドに対してソースリード端子との間でボンデ
ィングを行い、前記良品縦型ＭＯＳトランジスタ以外の
不良品縦型ＭＯＳトランジスタに接続するソース用パッ
ドに対してはボンディングを行わないことを特徴とする
縦型ＭＯＳトランジスタの製造方法。1. A semiconductor substrate of one conductivity type is formed as a drain, a plurality of regions of opposite conductivity type formed on the surface of the semiconductor substrate as a base, and a region of one conductivity type formed in the base as a source, formed on the surface of the semiconductor substrate. A gate insulating film, a gate electrode on the gate insulating film and covering the source and the base laterally interposed between the semiconductor substrate, a drain electrode for extracting the drain from the back surface of the semiconductor substrate, A vertical MOS transistor chip having a gate pad for collectively extracting the gate electrode to the outside and a source pad for dividing the source into a predetermined number and collectively extracting sources included in the divided regions. On the other hand, among the vertical MOS transistors connected to the source pad, only non-defective vertical MOS transistors operating normally are included in the chip. In addition to the gate pad, bonding is performed between a source lead terminal and a source pad connected to the non-defective vertical MOS transistor, and a defective vertical semiconductor transistor other than the non-defective vertical MOS transistor is performed. A method for manufacturing a vertical MOS transistor, wherein bonding is not performed on a source pad connected to the MOS transistor.
続するソース用パッドには、不良であることを示す不良
印が印されている請求項１記載の縦型ＭＯＳトランジス
タの製造方法。2. The method for manufacturing a vertical MOS transistor according to claim 1, wherein a defect mark indicating a defect is marked on a source pad connected to the defective vertical MOS transistor.
ード毎にグループ分けし、前記グループ毎にグループに
対応したボンディングプログラムを用いてボンディング
を行う請求項２記載の縦型ＭＯＳトランジスタの製造方
法。3. The manufacturing of the vertical MOS transistor according to claim 2, wherein the chips are divided into groups for each mode of the marked defect mark, and bonding is performed for each of the groups using a bonding program corresponding to the group. Method.
パッケージのチップ搭載領域を通して外部に取り出され
る請求項１、２又は３記載の縦型ＭＯＳトランジスタの
製造方法。4. The method for manufacturing a vertical MOS transistor according to claim 1, wherein said drain electrode is taken out through a chip mounting region of a package containing a chip.
るパッケージである請求項４記載の縦型ＭＯＳトランジ
スタの製造方法。5. The method according to claim 4, wherein the package is a package having three terminals.
項４又は５記載の縦型ＭＯＳトランジスタの製造方法。6. The method according to claim 4, wherein the package has a heat sink.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000295899A JP2002110727A (en) | 2000-09-28 | 2000-09-28 | Method for manufacturing vertical mos transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000295899A JP2002110727A (en) | 2000-09-28 | 2000-09-28 | Method for manufacturing vertical mos transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002110727A true JP2002110727A (en) | 2002-04-12 |
Family
ID=18778253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000295899A Pending JP2002110727A (en) | 2000-09-28 | 2000-09-28 | Method for manufacturing vertical mos transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002110727A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003107422A1 (en) * | 2002-06-13 | 2003-12-24 | 松下電器産業株式会社 | Semiconductor device and its manufacturing method |
| JP2006210777A (en) * | 2005-01-31 | 2006-08-10 | Nec Electronics Corp | Semiconductor device |
| JP5599388B2 (en) * | 2009-04-28 | 2014-10-01 | 三菱電機株式会社 | Power semiconductor device |
-
2000
- 2000-09-28 JP JP2000295899A patent/JP2002110727A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003107422A1 (en) * | 2002-06-13 | 2003-12-24 | 松下電器産業株式会社 | Semiconductor device and its manufacturing method |
| KR100700863B1 (en) * | 2002-06-13 | 2007-03-29 | 마츠시타 덴끼 산교 가부시키가이샤 | Semiconductor device and its manufacturing method |
| US7230273B2 (en) | 2002-06-13 | 2007-06-12 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device with a plurality of semiconductor elements each including a wide band-gap semiconductor |
| CN100403537C (en) * | 2002-06-13 | 2008-07-16 | 松下电器产业株式会社 | Semiconductor device and its manufacturing method |
| JP2010251772A (en) * | 2002-06-13 | 2010-11-04 | Panasonic Corp | Semiconductor device, and method of manufacturing the same |
| JP2006210777A (en) * | 2005-01-31 | 2006-08-10 | Nec Electronics Corp | Semiconductor device |
| JP5599388B2 (en) * | 2009-04-28 | 2014-10-01 | 三菱電機株式会社 | Power semiconductor device |
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