JP2002100748A - Dynamic storage device for matrix image displaying device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a displaying and storing device using a dynamic storage cell which can be loaded mixedly in a logic semiconductor device for image processing and has a high affinity to a standard CMOS logic process and having a small size and a large capacity. SOLUTION: The dynamic storage cell which has a high affinity to CMOS logic circuits and can be suppressed in manufacturing cost can be designed, without using special manufacturing techniques, etc. A dynamic storage element of the storage cell is constituted of a MOS capacitance element 404 and a MOS transistor 403, and the plate wiring 407 of the capacitance element 404 and the gate wiring of the transistor 403 are connected to word lines 405. In addition, such an arranging method is used with MOS capacitance elements 404 and MOS transistors 403 being arranged alternately in the configuration of two elements 404 by two transistors 403 in each row of a storage cell array. The positions of the elements 404 and transistors 403 in each row are shifted from those in adjacent rows, and then the drains are connected to bit lines 406.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor dynamic memory, and more particularly to a dynamic memory device in which dynamic memory cells composed of MOS transistors and MOS capacitors are arranged in an array in a standard CMOS logic process. Dynamic memory cell arrangement.

[0002]

2. Description of the Related Art Graphic control semiconductor devices for controlling the screen of a monitor for a personal computer, and semiconductor devices for controlling a flat display device using liquid crystal and EL (Electro-Luminescence) elements for portable equipment, etc. Such a semiconductor device for image processing requires a display storage circuit for storing information on the luminance level of each pixel.With the recent development of semiconductor process technology, a display storage circuit conventionally provided outside the control semiconductor device is required. It is required that the general-purpose semiconductor memory device be mixed inside the semiconductor device for image processing.

When a conventional semiconductor memory device is mixedly mounted inside a logic semiconductor device for image processing, a static storage device having a high affinity with a standard CMOS logic circuit is mixedly mounted as a display storage device inside the semiconductor device for image processing. Is common.

On the other hand, as the definition of the display device becomes higher, a large-capacity memory is also required for the display storage circuit.
Particularly, in flat display devices for portable devices, the demand for colorization or an increase in the number of color display colors has been remarkable in recent years, so that large-capacity display storage devices are also required for matrix-type image display devices for portable devices. If a monochrome flat display device is simply converted to color, three times as many display storage elements as three RGB colors are required, but the large-scale static type is required for the drive circuit and control device of the matrix type image display device. If a memory is mounted, the size of the chip is inevitably increased, which increases the manufacturing cost, which is not desirable.

In order to avoid a large increase in the chip size, a memory device which can be highly integrated is necessary.
Although it is desirable to use a semiconductor dynamic storage device using a dynamic storage cell composed of OS-type capacitance elements, dynamic memory elements are generally designed using special process technologies that are not used in standard CMOS logic processes (for example, trench capacitors and stack capacitors). (E.g., a process for a special capacitance element represented by a semiconductor device) is essential, so if it is attempted to mix them inside a semiconductor device for image processing, such a special process becomes necessary. Undesirably causes increase.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to realize a small and large-capacity display storage device using a dynamic memory cell having a high affinity with a standard CMOS logic process which can be embedded in a logic semiconductor device for image processing. Aim.

[0007] The MOS constituting the memory cell of the dynamic memory device without using a special capacitor process technology
A gate insulating film of a capacitive element also constitutes a memory cell
By using the same gate material as the MOS transistor, it is possible to avoid an increase in manufacturing cost, and to use a special layout to achieve a minimum cell area under such a cell structure, thereby achieving a small and large capacity. Realizing a dynamic storage device.

[0008]

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the main functional components constituting a dynamic storage device (100) embedded in a semiconductor device for image processing.
Cell array (101) in which N word lines commonly connected to the gates of type transistors and M bit lines commonly connected to the drains of MOS type transistors are arranged in rows and columns, and read to the bit lines. A sense amplifier circuit (102) for amplifying the output storage charge, and a column decoder circuit for selectively connecting information read to the sense amplifier and external data input / output in accordance with externally designated column address information (103), a row decode circuit (10) for selectively activating the word line according to row address information specified externally.
4) and a control circuit (105) for controlling them.

FIG. 2 shows an equivalent circuit diagram (201) of a dynamic memory cell and a sectional structural diagram (202) of a memory cell using a planar capacitor which is a structure generally used for a general-purpose dynamic memory device. The dynamic memory cell is a MOS transistor (203) and a MOS capacitor.
(204), a word line (205) commonly connected to the gate of the MOS transistor, a bit line (206) commonly connected to the drain of the MOS transistor,
In addition to the above-mentioned planar capacitor, a stack type capacitor or trench type capacitor is used as a general-purpose dynamic memory cell capacitor. Also in this case, different wiring materials are used for the word line (205) commonly connected to the gate of the MOS transistor and the plate line (207) which is a common counter electrode of the capacitor. It is a universal feature.

FIG. 3 is an arrangement layout (301) of a memory cell array in which dynamic memory cells used in a conventional example are arranged in a matrix and an equivalent circuit diagram corresponding to the arrangement layout (302). As shown, the drain of the MOS transistor of the memory cell in which the word line (205a) is connected to the gate is connected to the bit line (206a), and the memory cell in which the word line (205b) is connected to the gate. The drain of the MOS transistor is connected to the bit line (206b), and this `` folded bit-line method '' is generally the most noise-resistant in general-purpose dynamic memory devices using dynamic memory cells. It is a method and is generally used.

In the layout layout of a conventional memory cell array in which dynamic memory cells are arranged in a matrix as shown in FIG. 3, a MOS transistor of a memory cell connected to a word line of interest is generally used. The feature is that every other bit line to which the drain is connected is placed; that is, in a dynamic memory device composed of N word lines and 2M bit lines, n is an integer less than or equal to N and m Is an integer from 0 to M, and the drain of the MOS transistor of the memory cell connected to the nth word line is the 2mth bit line or 2m +
It is characterized by being connected to the first bit line,
Generally, it is used as the most efficient way to arrange general-purpose dynamic storage cells using dynamic storage cells.

In the conventional example described above, the MOS type of the dynamic memory cell, which is a main functional component of the dynamic memory device (100) embedded in the semiconductor device for image processing, is described.
A characteristic of the arrangement of a memory cell in which N word lines commonly connected to the gates of the type transistors and 2M bit lines commonly connected to the drains of the MOS type transistors are arranged in a matrix is connected to the word lines. MOS of damaged storage cell
The bit line to which the drain of the type transistor is connected is arranged every other line, and the gate line layer of the MOS type transistor of the dynamic memory cell and the plate line which is the common counter electrode of the MOS type capacitance element are in different line layers. It is explained that it is characterized by being formed as.

FIG. 4 shows an equivalent circuit diagram (401) of a dynamic memory cell constituting one embodiment of the present invention, and a cross section of the memory cell which can be realized by a logic process used in the dynamic memory device of the present invention. Structural drawing (402), plan view (400)
The dynamic memory cell is composed of a MOS transistor (403) and a MOS capacitor (404).
A word line (405) commonly connected to the gate of the OS transistor, a bit line (406) commonly connected to the drain of the MOS transistor, and a plate line (407) that is a common counter electrode of the capacitor. It is configured.

FIG. 4 is a sectional structural view of the memory cell shown in FIG.
As shown in the plan view (420), in the dynamic memory cell of the present invention, the word line (405) commonly connected to the gate of the MOS transistor of the memory cell and the plate line (407) which is a common counter electrode of the capacitor are used. Since the minimum cell area cannot be realized even if the memory cell of the present invention is arranged according to the method shown in the conventional example, the dynamic memory cell of the present invention is arranged. In doing so, we devised a completely different arrangement method from the conventional example.

FIG. 5 shows an arrangement layout (501) of a memory cell array in which dynamic memory cells used in the present invention are arranged in a matrix and an equivalent circuit diagram corresponding to the arrangement layout.
As shown in the figure, the drain of the MOS transistor of the memory cell in which the word line (405a) is connected to the gate is connected to the bit line (406a), and the word line (405a) is connected.
Since the drain of the MOS transistor of the memory cell whose b) is connected to the gate is connected to the bit line (406b), a `` folded bit-line '' structure generally used for dynamic storage devices It is possible to inherit the advantages of the conventional method in the electrical characteristics.

The arrangement layout (501) shown in FIG. 5 is characterized in that the word lines (405) are arranged between plate lines (407) formed in an island-like donut shape. For this reason, the equivalent circuit diagram (502) is characterized in that bit lines to which the drains of the MOS transistors of the memory cells connected to the word line of interest are connected are provided every two lines. In a dynamic memory device consisting of four word lines and 4M bit lines, n is an integer less than or equal to N and m is an integer greater than or equal to 0 and M. MOS
Type transistors have 4m and 4m + 1th drains respectively
And the 4m + 2, 4m + 3rd bit lines.By using the layout of the present application, the dynamic storage cells of the present application can be arranged most efficiently. A small and large-capacity display storage device using a dynamic memory element with high affinity with a CMOS logic circuit that can be embedded in a processing logic semiconductor device can be realized.

The arrangement layout (50) shown in FIG.
In (1), since the word lines (405) are arranged between the plate lines (407) formed in an island-like donut shape, it is necessary to connect each island-like word line with a wiring layer However, since logic semiconductor devices generally require two or more wiring layers, the first wiring layer should be used as a bit line and the second wiring layer should be used as a wiring layer to connect island-shaped word lines. Thus, it is possible to configure a memory cell array in which dynamic storage cells, which are the object of the present application, are arranged in a matrix.

FIG. 6 shows a cell area (6a) of a static memory cell generally designed by using the same minimum line width manufacturing technique, and a conventional memory cell using a dynamic memory cell. Cell area (6b), cell area when using the dynamic storage cell of the present application and the arrangement method of the present application (6c)
By using the dynamic storage cell and the cell arrangement of the present application, it is possible to integrate about four times the storage capacity in the same area as compared to the case where a static storage cell is used.

As described in the above embodiments, the present invention is applied to a MOS memory device constituting a memory cell of a dynamic memory device.
By using a dynamic storage element with a layout that allows the plate wiring layer, which is the common opposing electrode of the capacitive element, to be composed of the gate wiring layer of the MOS transistor that constitutes the storage cell, no special manufacturing technology is required. It is possible to design a dynamic memory cell that has high affinity with CMOS logic circuits and reduces manufacturing costs.
By using the storage cell arrangement method optimized for the dynamic storage cell of the present application as described in the embodiment,
The cell area can be reduced to 1/4 of the unit cell area of a static memory designed with the same minimum line width technology, which enables large-capacity semiconductor memory devices to be used for image processing. It is possible to mix them inside a logic semiconductor device.

In the above embodiment, the description has been made on the assumption that the MOS transistor and the MOS capacitor constituting the dynamic memory cell have the same electrical characteristics with respect to the characteristics thereof. If the process is formed simultaneously, even if the type of the conductor of each element, the threshold voltage, etc. are changed, there is no hindrance to the effect of the present application.

Similarly, in the above embodiment, description has been made on the assumption that the same thickness is used for the gate insulating films of the MOS transistor and the MOS capacitor constituting the dynamic memory cell. As long as each gate wiring is formed at the same time, even if the gate insulating film thickness or the material of the gate insulating film of each element is changed, the effect of the present invention is not affected at all.

Although the present invention has been described based on the embodiment, the present invention is not limited to the above-described embodiment, and can be freely modified and changed within the scope described in the claims. .

According to the present invention, it is possible to realize a small and large-capacity display storage device using a dynamic storage cell having a high affinity with a standard CMOS logic circuit. A graphic control semiconductor device that controls the screen of a monitor for a personal computer without causing an increase, and a liquid crystal and EL (Electro-
Luminescence) It is possible to mix a large-scale memory device with a semiconductor device for image processing such as a semiconductor device for controlling a flat display device using a device.

SUMMARY OF THE INVENTION The present invention is directed to a MOS-type capacitive element constituting a memory cell of a dynamic memory device without using a special capacitor process technology conventionally used for a general-purpose dynamic memory device. By using the same counter wiring as the plate wiring layer and the same gate wiring layer as the MOS transistor that constitutes the storage cell, it is possible to avoid an increase in manufacturing cost and achieve a minimum cell area under such a cell structure. Therefore, by arranging word lines in an island shape and arranging them every two cells between plate lines formed in a donut shape, the dynamic memory cells of the present invention can be arranged most efficiently. A small and large-capacity display storage device using a dynamic memory element with high affinity with CMOS logic circuits that can be embedded in a logic semiconductor device for image processing.

[Brief description of the drawings]

FIG. 1 shows an example of a configuration of a dynamic storage device and a main functional component mixedly mounted inside a semiconductor device for image processing according to the present invention.

FIG. 2 is an example of an equivalent circuit diagram of a conventional dynamic memory cell and a sectional structural view of a memory cell using a planar capacitor.

FIG. 3 is an example of an equivalent circuit corresponding to a layout layout of a conventional dynamic memory cell.

FIG. 4 is an embodiment of an equivalent circuit of a dynamic memory cell according to the present invention, and a sectional structure and a plan view of the memory cell.

FIG. 5 is an embodiment of an equivalent circuit corresponding to a layout layout of a dynamic memory cell according to the present invention;

FIG. 6 is a comparison table of the area of the memory cell between the conventional example and the present invention when designed using the same manufacturing technology.

[Explanation of symbols]

100 dynamic storage device embedded in a semiconductor device for image processing 101 storage cell array in which dynamic type memory cells are arranged in a matrix 102 sense amplifier circuit 103 column decoder circuit 104 row decode circuit 105 control circuit 201 control circuit 201 Equivalent circuit diagram of dynamic memory cell 202… Cross-sectional structure diagram of dynamic memory cell 203… MOS transistor 204… MOS capacitor 205… Word line 206… Bit line 207… Plate line 301… Layout layout of memory cell array 302 … Equivalent circuit diagram of a memory cell array 400… Plan view of a dynamic memory cell 401… Equivalent circuit diagram of a dynamic memory cell 402… Cross-sectional structure diagram of a dynamic memory cell 403… MOS transistor 404… MOS capacitor 405… Word line 406… Bit line 407… Plate line 501… Memory cell array layout Cell area of the cell area 6c ... dynamic memory cells and application of the arrangement scheme of the cell area 6b ... dynamic memory cell of the conventional example arrangement scheme of an equivalent circuit diagram 6a ... static storage cells out 502 ... memory cell array

Claims (9)

[Claims] A storage cell comprising a MOS transistor and a MOS capacitor is arranged in a matrix, and the memory cells are arranged in a row.
A matrix having a dynamic storage device composed of N word lines commonly connected to the gates of OS transistors and 4M bit lines commonly connected to the drains of the MOS transistors in the column direction. In the image display device, n is an integer of N or less and m is an integer of 0 to M, and the drains of the MOS transistors connected to the n-th word line are 4m and 4m + 1, respectively.
A dynamic storage device for a matrix image display device, wherein the dynamic storage device is connected to a 4th bit line or 4m + 2, 4m + 3th bit lines. 2. A dynamic storage device for a matrix image display device according to claim 1, wherein said MOS type transistor and said MOS type capacitance element are formed of the same conductor. 3. A dynamic storage device for a matrix image display device according to claim 1, wherein the wiring layers of the MOS gates of the MOS transistor and the MOS capacitor are formed simultaneously in a manufacturing process. . 4. A storage cell comprising a MOS transistor and a MOS capacitor is arranged in a matrix, and the memory cells are arranged in a row.
A matrix having a dynamic memory device composed of N word lines commonly connected to the gates of OS transistors and M bit lines commonly connected to the drains of the MOS transistors in the column direction. In the image display device, the MOS type transistor and the
The wiring layers of the respective MOS gates of the MOS capacitor are formed simultaneously in the manufacturing process, and the gate wiring layers of the MOS transistors are arranged in an island shape, and the MOS type is formed so as to surround the island-shaped gate wiring layer. A dynamic storage device for a matrix image display device, wherein a gate wiring layer of a capacitive element is arranged. 5. The MO according to claim 4, wherein the MOs are arranged in an island shape.
A dynamic memory device for a matrix image display device, wherein a gate wiring layer of an S-type transistor is continuously arranged as a gate wiring of the MOS transistor adjacent in a row direction. 6. The MO according to claim 4, wherein the MOs are arranged in an island shape.
The gate wiring layer of the S-type transistor is continuously arranged as the gate wiring of the MOS transistor adjacent in the row direction, and is adjacent to the bit direction in the column direction similarly arranged across the connection point with the bit line. A gate wiring layer of the MOS type capacitive element arranged so as to surround a pair of gate wiring layers composed of gate wiring layers of the MOS type transistors arranged in another island shape. For dynamic storage. 7. The MO according to claim 4, wherein the MOs are arranged in an island shape.
The gate wiring layer of the S-type transistor is continuously arranged as the gate wiring of the MOS transistor adjacent in the row direction, and is adjacent to the bit direction in the column direction similarly arranged across the connection point with the bit line. A gate wiring layer of the MOS capacitance element is arranged so as to surround a pair of gate wiring layers formed by the gate wiring layers of the MOS transistors arranged in different island shapes, and A dynamic storage device for a matrix image display device, wherein a wiring layer for connecting a gate wiring layer in a row direction is provided. 8. The MO according to claim 4, wherein the MOs are arranged in an island shape.
The gate wiring layer of the S-type transistor is continuously arranged as the gate wiring of the MOS transistor adjacent in the row direction, and is adjacent to the bit direction in the column direction similarly arranged across the connection point with the bit line. A gate wiring layer of the MOS type capacitance element is arranged so as to surround a pair of gate wiring layers composed of a gate wiring layer of the MOS transistor arranged in another island shape, and the first wiring layer is A dynamic storage device for a matrix image display device, wherein the dynamic storage device is used as a line, and the second wiring layer is used as a wiring layer connecting a gate wiring layer of the island-shaped MOS transistor in a row direction. 9. The MO according to claim 4, wherein the MOs are arranged in an island shape.
By selecting the gate wiring layer of the S-type transistor, the MO is connected to two bit lines adjacent in the row direction.
A dynamic storage device for a matrix image display device, wherein two sets of storage cells are arranged in rows and columns so that the charges charged in the S-type capacitance element are transferred.