JP2002100193A - Boosting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain stable boosting capability in a wide operation voltage region and to reduce current consumption when operation voltage is high, in a boosting circuit of an EEPROM. SOLUTION: This circuit is provided with a transmission gate 101 in which plural capacitors C1, C2 are connected in parallel in each stage, while at least one of the capacitors C1, C2 is selected as an object of coupling operation. Capacity of a whole circuit is switched in accordance with operation voltage VDD by controlling conduction of the transmission gate 101 by a signal F and selecting at least one of two capacitors C1, C2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit, for example, an EEPRO used for a wireless card or the like.
M booster circuit.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a conventional booster circuit of an EEPROM. This booster circuit 10
Is an initialization circuit 11 (n
-MOSFET) and boost clock Φ, / Φ (inverted Φ)
Shift circuit 12 (n-MO) that shifts the voltage boosted by the coupling operation of each stage to the right in the drawing.
SFET) and a capacitor C for boosting. In the conventional booster circuit 10, the booster clock Φ,
/ Φ is directly connected to the capacitors C, and the required boosted voltage VPP is obtained by the coupling operation of each capacitor C.

[0003]

FIG. 6 is a characteristic diagram showing the relationship between the operating voltage and the current consumption in the booster circuit 10 of FIG. When an operation at a low voltage of VDD = 1.8 V is to be guaranteed, the total capacity of the booster circuit required to secure the boosting capability is about 150 pF, and the current consumption is 20.
It is about 0 μA. However, VDD =
When operated at 3 V, the consumed current flows as much as about 550 μA. As described above, in the conventional booster circuit 10, since the capacity of the entire booster circuit is always constant, there is a problem that if the voltage is increased with the set capacity, the current consumption increases in proportion to the voltage. Was. By the way, VDD = 3
If the capacity is determined so that the current consumption is reduced at V, the boosting ability in the low voltage range cannot be secured, and the necessary boosted voltage cannot be obtained.

Therefore, the above-described booster circuit 10
For example, when applied to an LSI having a wide operating voltage range, the battery life is reduced, and when applied to an LSI using a weak current source such as a wireless card, the communication distance is reduced. there were.

An object of the present invention is to provide a booster circuit capable of obtaining a stable boosting capability in a wide operating voltage range and reducing current consumption even when the operating voltage is high.

[0006]

In order to achieve the above object, according to the first aspect of the present invention, a plurality of capacitors for boosting are arranged, and an input operating voltage is stepped by a coupling operation for each capacitor. In a booster circuit configured to boost the voltage, a plurality of capacitors are connected in parallel for each stage, and a selecting means is provided for selecting at least one of the plurality of capacitors as a target of a coupling operation. According to the input operating voltage,
Preferably, the selecting means selects at least one of the plurality of capacitors.

According to a second aspect of the present invention, in the first aspect, the selection means selects at least one of the plurality of capacitors according to a selection signal set according to an input operating voltage. Features.

[0008] In a preferred embodiment, the selecting means is n
A transmission gate in which a MOSFET and a p-MOSFET are combined, and at least one of a plurality of capacitors is selected by inputting an H or L level signal as the selection signal to the gate electrode of the MOSFET. .

In a preferred embodiment, the selection signal is supplied from a power supply detection circuit based on an input operating voltage.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a booster circuit according to the present invention will be described below with reference to the accompanying drawings.

Embodiment 1 FIG. 1 is a circuit diagram of a booster circuit according to Embodiment 1, and the same parts as those in FIG. 5 are denoted by the same reference numerals. In the booster circuit 100 according to the first embodiment, capacitors C1 and C2 for boosting are connected in parallel at the preceding stage of each shift circuit 12. Among these two capacitors, the capacitor C1 is connected to the transmission gate 101, and the capacitors C2 are alternately connected to the lines of the boost clocks Φ and / Φ every other. Here, the capacitance of the sum of the capacitors C1 and C2 is set to be substantially the same as the capacitance of the capacitor C shown in FIG.

The transmission gate 101 comprises an n-MOSFET and a p-MOSFET. And p-MO
The gate electrode of the SFET is connected to the line of the capacitance switching signal F (hereinafter, signal F), and the gate electrode of the n-MOSFET is connected to the line of the signal F inverted by the inverter 102. Thereby, the transmission gate 10
When an H (or L) level signal is applied to the gate electrode of one p-MOSFET, an L (or H) level signal is applied to the gate electrode of the n-MOSFET. Therefore, in the example of FIG. 1, when the signal F is at the L level, each transmission gate 101 is conductive, and when the signal F is at the H level, it is non-conductive.

The signal F is supplied from a power supply detection circuit (not shown). Here, the setting voltage of the capacitance switching is set to 2.3 V, and an L-level signal is supplied when VDD <2.3 V, and an H-level signal is supplied when VDD ≧ 2.3 V. However, the set voltage for switching the capacitance can be arbitrarily set by a power supply detection circuit (not shown).

According to the booster circuit 100 of the first embodiment, since the signal F is at L level when VDD is less than 2.3 V, the transmission gate 101 connected to each capacitor C1 becomes conductive and the capacitor C1 And the coupling operation is performed with the capacitance of the sum of C2 and C2. When VDD is in the range of 2.3 V or more, the signal F is at the H level, so that the transmission gate 1 connected to each capacitor C1
01 becomes non-conductive, and the coupling operation is performed with only the capacitance of the capacitor C2.

FIG. 2 is a characteristic diagram showing the relationship between operating voltage and current consumption in the booster circuit 100 of FIG. As shown in FIG. 2, when VDD is less than 2.3 V, the coupling operation is performed with the sum of the capacitances of the capacitors C1 and C2, so that the current consumption is the same as in the conventional example. However, when VDD is 2.3 V or more, the capacitor C2
Since the coupling operation is performed with only the capacitance, the current consumption during the coupling operation is reduced, and VDD is reduced.
= 3V, the current consumption is about 400μA,
The current consumption can be reduced as compared with the conventional example.

Second Embodiment FIG. 3 is a circuit diagram of a booster circuit according to a second embodiment, in which the same parts as those in FIG. The booster circuit 200 according to the second embodiment is configured such that the set voltage of the capacitance switching is set in two stages, and the capacitance of the capacitor can be switched more finely. For this purpose, the capacitors C1 and C2 for boosting are provided before the shift circuit 12.
And C3 are connected in parallel. Among these three capacitors, the capacitor C1 is connected to the transmission gate 201, the capacitor C2 is connected to the transmission gate 202, and the capacitor C2 is connected to the transmission gate 202.
Reference numeral 3 denotes alternately connected booster clocks Φ and / Φ lines. Here, the capacitance of the sum of the capacitors C1, C2 and C3 is set to be substantially the same as the capacitance of the capacitor C shown in FIG.

The transmission gates 201 and 202 are composed of n-MOSFETs and p-
It is composed of a MOSFET. Among them, the gate electrode of the p-MOSFET of the transmission gate 201 is connected to the line of the capacitance switching signal F1 (hereinafter, signal F1) and the n-MO
The gate electrode of the SFET is connected to the line of the signal F1 inverted by the inverter 203. The gate electrode of the p-MOSFET of the transmission gate 202 is connected to the line of the capacitance switching signal F2 (hereinafter, signal F2), and the gate electrode of the n-MOSFET is connected to the line of the signal F2 inverted by the inverter 204. .

Thus, the p-MO of the transmission gate 201
When an H (or L) level signal is applied to the gate electrode of the SFET, the gate electrode of the n-MOSFET is
(Or H) level signal. When a signal of H (or L) level is given to the gate electrode of the p-MOSFET of the transmission gate 202, n-
An L (or H) level signal is applied to the gate electrode of the MOSFET.

Therefore, in the example of FIG.
When the level is at the level, each transmission gate 201 becomes conductive,
During the H level, it is non-conductive. Similarly, when the signal F2 is L
At the level, each transmission gate 202 becomes conductive,
During the H level, it is non-conductive.

The signals F1 and F2 are provided from a power supply detection circuit (not shown). Here, the set voltage of the capacity switching is set to two steps of 2.2V and 2.6V.
That is, in the range of VDD <2.2 V, the signals F1 and F
2 are at the L level, and in the range of 2.2V ≦ VDD <2.6V, the signal F1 is at the H level and the signal F2 is at the L level. Further, in the range of VDD> 2.6 V, the signals F1 and F2 are both at the H level. Also in the second embodiment, the set voltage for switching the capacitance can be arbitrarily set by a power supply detection circuit (not shown).

According to the booster circuit 200 of the second embodiment, when VDD is less than 2.2 V, the signals F1 and F2 are both at the L level, so that the transmission gate 201 connected to each capacitor C1 and each capacitor Both the transmission gates 202 connected to C2 become conductive, and the coupling operation is performed with the sum of the capacitances of the capacitors C1, C2 and C3. VDD is 2.2 V to 2.6 V
In the range below, the signal F1 is at the H level and the signal F2 is at the L level, so that the transmission gate 201 connected to each capacitor C1 becomes non-conductive, and the capacitors C2 and C3
The coupling operation is performed with the capacitance of the sum of.
Further, when the VDD is in the range of 2.6 V or more, the signals F1,
Since both F2 are at the H level, the transmission gate 201 connected to each capacitor C1 and the transmission gate 202 connected to each capacitor C2 are both non-conductive,
The coupling operation is performed only by the capacitance of the capacitor C3.

FIG. 4 is a characteristic diagram showing the relationship between operating voltage and current consumption in booster circuit 200 of FIG. As shown in FIG. 4, when VDD is less than 2.2 V, the coupling operation is performed with the sum of the capacitances of the capacitors C1, C2, and C3, so that the current consumption is the same as that of the conventional example A. And, when VDD is in the range of 2.2 to 2.6 V,
Since the coupling operation is performed with the sum of the capacitance of the capacitors C2 and C3, the current consumption during the coupling operation is reduced, and the current consumption can be reduced to about 300 μA when VDD = 2.6V. it can. In addition, VDD
Is 2.6V or more, the coupling operation is performed only with the capacitance of the capacitor C3, so that the current consumption during the coupling operation is further reduced, and VDD =
Even in the case of 3V, the current consumption is about 300 μA, and the current consumption can be greatly reduced as compared with the conventional example.

In the second embodiment, 2.2 V ≦ VDD <
In the range of 2.6 V, the signal F1 is set to the H level,
2 is at the L level, but within the same VDD range, the signal F1 may be at the L level and the signal F2 may be at the H level. That is, in the range of 2.2V ≦ VDD <2.6V, the combination of the capacitors that perform the coupling operation may be the capacitors C2 and C3 or the capacitors C1 and C3.

Further, in the second embodiment, an example is described in which the set voltage for the capacitance switching is set in two steps. However, the set voltage can be set in multiple steps. In this case, a capacitor and a transmission gate are connected according to the set number of stages, and a capacity switching signal according to the number of stages is supplied from a power supply detection circuit (not shown).

Further, in the first and second embodiments, an example is shown in which the transmission gate is constituted by an n-MOSFET and a p-MOSFET, but any other logic gate may be used as long as the circuit functions equivalently. .

[0026]

As described above, in the booster circuit according to the present invention, since the capacity of the capacitor for boosting is switched according to the operating voltage, a stable boosting capability can be obtained in a wide operating voltage range. In addition to this, even when the operating voltage is increased, the current consumption can be significantly reduced as compared with the conventional case.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a booster circuit according to a first embodiment.

FIG. 2 is a characteristic diagram showing a relationship between operating voltage and current consumption in the booster circuit of FIG.

FIG. 3 is a circuit configuration diagram of a booster circuit according to a second embodiment.

FIG. 4 is a characteristic diagram showing a relationship between an operating voltage and current consumption in the booster circuit of FIG. 3;

FIG. 5 is a circuit diagram of a conventional booster circuit.

FIG. 6 is a characteristic diagram illustrating a relationship between an operating voltage and a current consumption in the booster circuit of FIG. 5;

[Explanation of symbols]

11: initialization circuit, 12: shift circuit, 101, 2
01, 202 ... transmission gate, 102, 203, 204 ...
Inverter

Claims (2)

[Claims] 1. A booster circuit in which a plurality of capacitors for boosting are arranged and configured to stepwise boost an input operating voltage by a coupling operation for each capacitor, wherein a plurality of capacitors are provided for each stage. A connecting means for connecting capacitors in parallel and selecting at least one of the plurality of capacitors as a coupling operation target is provided.
A booster circuit, wherein at least one of the plurality of capacitors is selected by the selection means according to an input operating voltage. 2. The booster circuit according to claim 1, wherein said selection means selects at least one of said plurality of capacitors according to a selection signal set according to an input operating voltage. .