JP2002099435A - Control method of multi-task and information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control method of multi-task and an information processor using the method capable of deciding in advance whether it is possible to perform a task within a performing capacity of a processor and capable of avoiding multi-task processing beyond the capacity. SOLUTION: In the method, when performing the task newly, at least the number of instruction code regarding to processing contents of the task is acquired from the task as a predicted load information using for a prediction of a load of the processor, so that the task decided to be performed within a reserve capacity of the processor based on the load information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a multitask control method and an information processing apparatus in a real-time multitask operating system.

[0002]

2. Description of the Related Art A real-time multitasking operating system (hereinafter, referred to as a real-time OS)
Is an operating system with a function to process a plurality of tasks in real time. In a real-time OS, particularly when high-speed responsiveness is required, there are cases where the processing cannot be completed within the processing time limit in which the result of the task is required. Therefore, a method of efficiently performing task scheduling has been proposed for a plurality of tasks so that the processing can be completed within the processing time of each task. Specifically, a means for achieving efficient task switching by constantly optimizing task priorities by dynamically calculating task priorities from task occurrence times and their processing time limits ( JP-A-8-163538) has been proposed.

[0003]

However, in the technology proposed in the past, there is no restriction on accepting tasks, the system attempts to execute a task exceeding the processing capability of the processor, and any or all of the tasks are executed. There is a problem that processing cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. When a new task is executed, it can be determined in advance whether or not the task can be executed within the processing capability of a processor. A multitask control method capable of avoiding multitask processing exceeding the processing capability of a processor and an information processing apparatus using the same are provided.

[0005]

SUMMARY OF THE INVENTION The present invention is to execute a plurality of different information processings in a multitasking process. When a new task is executed, at least the processing contents of the task are required. The number of instruction codes is obtained from the task as predicted load information used for predicting the load on the processor, and a task determined to be executable within the remaining capacity of the processor is executed based on the predicted load information, thereby creating a new task. Can be determined in advance whether or not the task can be executed within the processing capacity of the processor, and multitask processing exceeding the processing capacity of the processor can be avoided.

For a task determined to be unexecutable based on the predicted load information, a parameter for changing the processing content of the task is changed, and as a result, the predicted load information of the changed task is obtained. By determining whether or not the task can be executed, when a new task is executed, it can be determined in advance whether or not the task can be executed within the processing capacity of the processor. When a real-time property is required, multitask processing exceeding the processing capability of the processor can be avoided by changing the processing content of a task that is indispensable for execution. Further, the choice of the execution task increases due to the change of the parameter, and the multitask processing can be efficiently executed by the processor within its processing capacity.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

[0008] First of the multitask control method according to the present invention
Will be described with reference to the flowchart shown in FIG.

In the following, in the first to third embodiments, a task is a single module that performs different types of information processing, and a plurality of tasks executed by a processor include, for example, an encoder process. Or a task to execute a decoder process.

The estimated load information of each task is, for example, the number (approximate value) of instruction codes related to the processing content of the task, and estimates the worst load amount applied to the processor when executing the task. This is an index amount. If the parameter set in advance for the task (a parameter that changes the processing content) changes, the number of instruction codes also changes, so the predicted load information also changes. Such parameters are for changing the processing contents of the task at the application level, and include, for example, parameters for changing the sampling frequency and the filter coefficient for the processing target data of the task.
If there are a plurality of parameters, the predicted load information is held by the task itself or calculated in accordance with the parameters. In this case, it is assumed that the task is divided into a part that holds or calculates the predicted load information in association with the parameter and a part that performs the original processing of the task. In the following embodiments, for the sake of simplicity, the task associates one or more parameters with the number of instruction codes of the task itself (or the number of instruction codes plus the overhead depending on the processor). Shall be held in advance.

When there is a task generation (execution) request for a task (step S3), the kernel 1 requests the task 2 to provide predicted load information. The task 2 passes the number of instruction codes corresponding to the parameters set at the present time of the task to the kernel 1 as predicted load information (step S7). When the kernel 1 acquires the predicted load information from the task 2 (step S4), the predicted load information and the MIPS (Million Instruction) of the processor are acquired.
ons Per Second) value and the current operating status of the processor (for example, here, for simplicity of description, the current value of the number of instruction codes (processing capacity) executable by the processor within a predetermined time, which is obtained from the MIPS value, The total value of the number of instruction codes of all tasks executed in the multitask process (the actual value may be used, or the total value of the instruction codes presented from each task as the predicted load information) Percentage), the feasibility of task 2 within the processor's spare capacity is determined,
Are determined (step S5). At this time, the kernel 1 may modify the number of instruction codes as unpredictable information received from the task 2 depending on the hardware configuration of the processor. For example, the overhead depending on the processor may be added to the number of instruction codes received from Tact2.

When the number of instruction codes of task 2 is the number of instruction codes that can be executed within the available capacity of the processor, it is determined that the task code can be executed based on the predicted load information of task 2 and the operating state of the processor. To task 2, while
When the number of executable instruction codes exceeds the number of executable instruction codes within the remaining capacity of the processor, it is determined that the executable code is low and the task 2 is given a low priority. Thereafter, task 2 is generated (executed) based on the priority order (step S6), and task 2 performs task processing (step S8).

For example, as shown in FIG. 4, it is assumed that the processor 20 is executing the encoder task 21 and the decoder task 22 and a request to generate the filter A task 23 is generated (step S25). The kernel 1 is informed of the predicted load information from the filter A / task 23, and the kernel receives the filter A / task 2 based on the predicted load information.
The priority of 3 is determined to be “10”. On the other hand, filter B
When a request to generate the task 24 is issued (step S2
6) Assuming that the priority of the filter B / task 24 obtained in the same manner is “20” (see FIG. 7), the kernel generates (executes) the filter B / task 24 having a higher priority.

Second Embodiment of Multitask Control Method According to the Present Invention
An embodiment will be described with reference to the flowchart shown in FIG.

When there is a task generation (execution) request for a task (step S3), the kernel 1 requests the task 2 to provide predicted load information. The task 2 passes the number of instruction codes corresponding to the parameters set at the present time of the task to the kernel 1 as predicted load information (step S7). When the kernel 1 acquires the predicted load information from the task 2 (step S4), the predicted load information, the MIPS value of the processor, and the current operating status of the processor (for example, here, it is obtained from the MIPS value for simplicity of explanation). The total value of the number of instruction codes of all the tasks currently being executed in the multitask processing at the present time (the actual load and the predicted load It may be determined whether or not the task 2 can be executed within the remaining capacity of the processor (step S9) based on the ratio of the number of instruction codes presented from each task as information). At this time, the kernel 1 may modify the number of instruction codes received as unpredictable information from the task 2 depending on the hardware configuration of the processor. For example, an overhead depending on the processor may be added to the number of instruction codes received from Tact2. When the number of instruction codes of the task 2 is the number of instruction codes executable within the remaining capacity of the processor, it is determined that the task 2 is executable from the predicted load information of the task 2 and the operation state of the processor.
On the other hand, when the number of executable instruction codes exceeds the number of executable instructions within the remaining capacity of the processor, it is determined that the task 2 cannot be executed. If executable (step S10), generate task 2 (execute)
(Step S6). If the task 2 cannot be executed (step S9), the generation (execution) of the task 2 is rejected (step S12).

For example, consider a case where the processor 20 is executing the encoder task 21 and the decoder task 22 as shown in FIG. 4, and a generation (execution) request 25 of the filter A / task 23 is generated (step S25). . Here, the number of instruction codes executable by the processor within a predetermined time from the MIPS value of the processor 20 is defined as the processing capability of the processor. Here, for example, “10
0 ". The predicted load information of each task, that is, the number of instruction codes is given as shown in FIG. 6, and the filter A uses the parameter “2”. At this time, the processor 20 is performing the processing with the load of “80” between the encoder task 21 and the decoder task 22, so that the remaining processing capacity of the processor 20 is “20”.
That is, the processor 20 can execute the task if the number of instruction codes is within “20”.

First, kernel 1 is composed of filter A and task 2
3 informs that the predicted load is "30",
Since it is found that the execution is impossible, the generation (execution) of the filter A / task 23 is rejected.

On the other hand, under the same conditions, filter B and task 2
Consider a case where a request for generation (execution) of No. 4 occurs (step S26). Then, kernel 1 becomes filter B and task 2
4 informs that the predicted load is "10",
Since it is found that the execution is possible, the filter B / task 24 is generated (executed).

Third Embodiment of the Multitask Control Method According to the Present Invention
The embodiment will be described with reference to the flowchart shown in FIG.

When there is a task generation (execution) request for a task (step S3), the kernel 1 requests the task 2 for predicted load information. The task 2 passes the number of instruction codes corresponding to the parameters set at the present time of the task to the kernel 1 as predicted load information (step S7). When the kernel 1 acquires the predicted load information from the task 2 (step S4), the predicted load information, the MIPS value of the processor, and the current operation status of the processor (for example, here, for simplicity of explanation, the MIPS value The sum of the numbers of instruction codes of all the tasks currently being executed in the multitask processing with respect to the number of instruction codes executable by the processor within a predetermined time (processing capacity) (in the case where an actual measurement value is used, (It may be the total value of the number of instruction codes presented from each task as load information.)
Task 2 within the processor's spare capacity based on
It is determined whether or not is executable (step S9). At this time, the kernel 1 may modify the number of instruction codes received as unpredictable information from the task 2 depending on the hardware configuration of the processor. For example, Takuk 2
May be added to the number of instruction codes received from the processor. If the number of instruction codes that can be executed within the remaining capacity of the processor, the task 2 is determined to be executable. Judge.

If executable (step S10), task 2 is generated (executed) (step S6). If the task cannot be executed (step S9), the parameter of the task 2 is changed (step S13), the presentation of the predicted load information is requested to the task 2 again (step S7), and the feasibility of the task 2 is determined (step S7). Step S9). This operation is repeated until task 2 becomes executable.

For example, consider the case where the processor 20 is executing the encoder task 21 and the decoder task 22 as shown in FIG. 5 and a request to generate (execute) the filter A task 23 is generated (step S25). here,
The number of instruction codes executable by the processor within a predetermined time from the MIPS value of the processor 20 is defined as the processing capability of the processor. Here, for example, “100” is set. The predicted load information of each task, that is, the number of instruction codes is given as shown in FIG.
3 uses parameter "2". At this time, the processor 20 is performing the processing with the load of “80” between the encoder task 21 and the decoder task 22, and the processing capacity of the processor 20 is “20”.
It is. That is, the processor 20 can execute the task if the number of instruction codes executable within a predetermined time is within “20”.

First, kernel 1 is composed of filter A and task 2
3 informs that the predicted load information is “30”,
Since it is found that the execution is impossible, the parameters of the filter A / task 23 are changed (step S27). For example, consider a case where the parameter of the filter A / task 23 is changed to “1”. With this change, filter A
When the generation (execution) request of the task 23 occurs again (step S28), the kernel 1 requests the filter A / task 23 to provide the predicted load information again. , And it is known that the process is executable, so that the filter A / task 23 is generated (executed).

It should be noted that the present invention is not limited to the above-described embodiment, and that various modifications can be made in the implementation stage without departing from the scope of the invention. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriate combinations of a plurality of disclosed configuration requirements. For example, even if some components are deleted from all the components shown in the embodiment, (at least one of) the problems described in the column of the problem to be solved by the invention can be solved, and the effect of the invention can be solved. If at least one of the effects described in (1) is obtained, a configuration from which this component is deleted can be extracted as an invention.

[0025]

As described above, according to the present invention, when a new task is executed, it can be determined in advance whether or not the task can be executed within the processing capability of the processor.
Multitask processing exceeding the processing capability of the processor can be avoided.

[Brief description of the drawings]

FIG. 1 is a flowchart for explaining a second embodiment of the multitask control method according to the present invention.

FIG. 2 is a flowchart for explaining a first embodiment of a multitask control method according to the present invention.

FIG. 3 is a flowchart for explaining a third embodiment of the multitask control method according to the present invention.

FIG. 4 is a diagram for specifically explaining the processing operations of FIGS. 1 and 2;

FIG. 5 is a diagram for specifically explaining the processing operation of FIG. 3;

FIG. 6 is an explanatory diagram for describing an embodiment of the processing operation of FIGS. 1 and 3;

FIG. 7 is a diagram for specifically explaining the processing operation of FIG. 2;

[Explanation of symbols]

 1 Kernel 2 Task 20 Processor 21 Encoder task 22 Decoder task 23 Filter A task 24 Filter B task

Claims (4)

[Claims] In a multitask control method for executing a plurality of different information processes in a multitask process, when a new task is executed, at least the number of instruction codes related to the processing content of the task is determined by a processor. A multi-task control method comprising: acquiring from a task as predicted load information used for predicting a load; and executing a task determined to be executable within the remaining capacity of a processor based on the predicted load information. 2. For a task determined to be unexecutable based on the predicted load information, a parameter that changes the processing content of the task is changed, and as a result, the changed predicted load information of the task is obtained. 2. The multitask control method according to claim 1, wherein it is determined whether the task can be executed. 3. An information processing apparatus for executing a plurality of different information processings by multitask processing, wherein when a new task is executed, at least the number of instruction codes related to the processing content of the task is estimated by predicting the load of the processor. Means for acquiring from the task as predicted load information used for performing the task, and means for executing a task determined to be executable within the remaining capacity of the processor based on the predicted load information. Processing equipment. 4. When it is determined that the task cannot be executed,
Means for changing a parameter for changing the processing content of the task, acquiring predicted load information of the task changed as a result, acquiring predicted load information again from the task whose parameter is changed, 4. The information processing apparatus according to claim 3, wherein it is determined whether the task can be executed.