JP2002099336A - Band gap reference circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a band gap reference circuit, which is composed of only an enhancement type MOS transistor, capable of obtaining a reference voltage Vref of a little power supply voltage dependency and obtaining a satisfactory lowest operating power supply voltage. SOLUTION: This circuit is composed of P-type MOS transistors P1-P3, N-type MOS transistors N1, N2 and N6, a diode D1 and resistors R1 and R2, and the fixed reference voltage Vref is obtained from given high potential side power source VDD and low potential side power source GND at an output terminal ref.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a band gap reference circuit, and more particularly to a band gap reference circuit mounted on a CMOS type semiconductor device and having little dependency on a power supply voltage.

[0002]

2. Description of the Related Art Conventionally, as a band gap reference circuit of the first conventional example, Japanese Patent No. 2994 shown in FIG.
A band gap reference circuit disclosed in Japanese Patent Publication No. 293 is known. The first conventional band gap reference circuit shown in FIG. 7 is a band gap reference circuit that obtains a constant reference voltage Vref from an applied high-potential power supply VDD and low-potential power supply GND at an output terminal ref. And the source is the high potential side power supply V
A P-channel field-effect transistor (hereinafter, referred to as a P-type MOS transistor) P1 connected to the DD, a drain and a gate connected to the drain of the P-type MOS transistor P1, and a source connected to the lower potential power supply GND; Channel type field effect transistor (hereinafter, N-type MOS)
N1) and the source is a high potential side power supply V
A P-type MOS transistor P2 whose drain and gate are connected to the gate of the P-type MOS transistor P1 and whose drain and gate are connected to the drain of the P-type MOS transistor P2 and whose gate is an N-type MOS transistor N1;
An N-type MOS transistor N2 connected to the gate of
Resistance element R1 having one end connected to the source of N-type MOS transistor N2 and the other end connected to low-potential-side power supply GND
And the source is connected to the high potential side power supply VDD and the gate is P
A P-type MOS transistor P3 having a drain connected to the reference voltage output terminal ref and a drain connected to the gate of the P-type MOS transistor P2;
A resistor R2 connected to the drain of the resistor R2, an anode connected to the other end of the resistor R2, and a cathode connected to the low potential side power supply G.
A diode D1 connected to the ND. With the above-described configuration, the gate lengths and the gate widths of the P-type MOS transistors P1, P2 and P3 are the same, and the N-type MOS transistor N1 is different from the N-type MOS transistor N1.
If the gate length of the transistor N2 is set to the same size and the gate width is set to M (hereinafter, M is a natural number other than 0) times, N is obtained from the output terminal ref as (the resistance value of R2) ÷
A reference voltage Vref expressed by Equation 1 is obtained by using (resistance value of R1), q as an electron charge amount, k as a Boltzmann constant, T as an absolute temperature, and VF (D1) as a forward voltage of the diode D1. Vref = N × (k × T ÷ q) × lnM + VF (D1) (Equation 1) However, the band gap of the first conventional example shown in FIG.
The reference circuit has a problem that when the voltage between the high-potential power supply VDD and the low-potential power supply GND fluctuates, the reference voltage Vref also changes. This is because, for example, the high-potential power supply VDD and the low-potential power supply GND have a problem. As the voltage between them increases, the drain-source voltage of the P-type MOS transistor P1 increases, and the drain current flowing into the N-type MOS transistor N1 increases due to the Early effect. As a result, the drain current of the N-type MOS transistor N2 forming a mirror together with the N-type MOS transistor N1 increases with the current due to the Early effect of the N-type MOS transistor N1.
The drain current of the OS transistor P2 also increases. Therefore, the drain current of P-type MOS transistor P3 forming a mirror together with P-type MOS transistor P2 also increases. This current increase is defined as Δid (1).
The drain current increases due to the Early effect of the P-type MOS transistor P3 itself.
Assuming (2), the current increase Δid of the drain current of the P-type MOS transistor P3 is expressed by Expression 2. Δid = Δid (1) + Δid (2) (Expression 2) The current increase Δid is equal to the resistance element R2 and the diode D.
1 causes the reference voltage Vref to fluctuate. The amount of the fluctuation is defined as ΔVref, and the drain current of the P-type MOS transistor P3 before receiving the dependency on the power supply voltage is I.
Assuming that DS (P3), ΔVref is expressed by Expression 3. ΔVref = Δid × R2 + (k × T ÷ q) × ln ((Δid + IDS (P3)) ÷ IDS (P3)) (Equation 3) The band of the second conventional example which eliminates this power supply voltage dependency
As the gap reference circuit, a band gap reference circuit shown in FIG. 8 and disclosed in Japanese Patent No. 2994293 is also known. The band gap reference circuit of the second conventional example shown in FIG.
Given high-potential power supply VDD and low-potential power supply GND
A gap reference circuit for obtaining a constant reference voltage Vref at the output terminal ref from the P-type MOS transistor P1 whose source is connected to the high-potential-side power supply VDD, and the source is connected to the drain of the P-type MOS transistor P1. A connected P-type MOS transistor P7, an N-type MOS transistor N1 having a drain and a gate connected to the drain of the P-type MOS transistor P7 and a source connected to the low-potential power supply GND, and a source connected to the high-potential power supply VDD A P-type MOS transistor P2 whose drain and gate are connected to the gate of the P-type MOS transistor P1, and a drain is connected to the drain of the P-type MOS transistor P2 and the gate is an N-type MOS transistor N
Depletion type N-type MOS connected to one gate
A transistor N4, an N-type MOS transistor N2 having a drain connected to the source of the N-type MOS transistor N4 and a gate connected to the gate of the N-type MOS transistor N1, and one end connected to the source of the N-type MOS transistor N2 and the other end Is connected to the low-potential-side power supply GND, a P-type MOS transistor P3 having a source connected to the high-potential-side power supply VDD and a gate connected to the gate of the P-type MOS transistor P2, and a P-type MOS transistor A P-type MOS transistor P5 connected to the drain of the transistor P3 and having the drain connected to the output terminal ref;
A resistor R2 having one end connected to the drain of the P-type MOS transistor P5; a diode D1 having an anode connected to the other end of the resistor R2 and a cathode connected to the low-potential power supply GND; A P-type MOS transistor P4 connected to VDD and having a gate connected to the drain, and a P-type MOS transistor having a source connected to the drain of the P-type MOS transistor P4 and having a drain and gate connected to the gates of the P-type MOS transistors P5 and P7. A transistor P6, a depletion-type N-type MOS transistor N5 having a drain connected to the drain of the P-type MOS transistor P6 and a gate connected to the gate of the N-type MOS transistor N1, and a drain connected to the source of the N-type MOS transistor N5 The source is connected to the low-potential-side power supply GND. Over door N-type MOS transistor N1
An N-type MOS transistor N3 connected to the gate of
It has.

With the above configuration, the reference voltage V
ref is obtained, and for example, the high-potential-side power supply VDD
Even if the voltage between the low-potential-side power supply GND and the low-potential-side power supply GND fluctuates, the voltage between the drain and source of the P-type MOS transistor P1 is suppressed by the source potential of the P-type MOS transistor P7, Is suppressed by the source potential of the P-type MOS transistor P5, the respective drain-source voltages do not fluctuate. Similarly, the drain-source voltage of the N-type MOS transistor N2 is N Source of the MOS transistor N4
Since the drain-source voltage of the N-type MOS transistor N3 is suppressed by the source potential of the N-type MOS transistor N5, each drain-source voltage does not change. Therefore, without being affected by the Early effect, Δid (1) = 0, Δid
(2) = 0, ΔVref = 0 in Equation 3, and a reference voltage Vref having no power supply dependency is obtained. P-type MOS transistors P4 and P6 and N-type MOS
A bias stage composed of transistors N3 and N5 is provided to bias the gate potentials of the P-type MOS transistors P5 and P7 with the gate potential of the P-type MOS transistor P6, and a depletion type N-type having a threshold voltage VT of 0 V or less. By using the MOS transistors N4 and N5, the minimum operating power supply voltage (the voltage between the high-potential power supply VDD and the low-potential power supply GND) equivalent to the band gap reference circuit of the first conventional example shown in FIG.
Is obtained.

[0004]

However, the above-mentioned second method
In the conventional band gap reference circuit, the depletion type N-type MOS transistors N4 and N5 must be used in order to secure the minimum operating power supply voltage. As an example, a depletion type N-type MOS transistor has a P concentration of 10 ¹⁴ to 10 ¹⁵ cm ⁻³ .
If an N-type MOS transistor is formed directly on a mold substrate, it can be realized without an additional process. However, for example, in an inexpensive DRAM process in which the number of masks is reduced by simplifying the process, first, the concentration is 10 ^{17 over the} entire surface of the substrate. ~ 10 ¹⁸
Since a P-well of cm ^-3 is formed, there is a problem that a depletion type N-type MOS transistor cannot be formed without an additional process.

Further, even if a depletion type N-type MOS transistor can be realized without adding a process, the depletion type MOS transistor has a large gate length L (L> 10 μm) because of a large leak current at a high temperature.
m), and furthermore, a drain current IDS (IDS> 1 μA) needs to be supplied. Therefore, a depletion type MOS transistor is required for a product requiring low current consumption and a small chip size such as a battery-powered clock. However, there is a problem that the band gap reference circuit including the above cannot be applied.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made up of only an enhancement type MOS transistor and has a reference voltage V s with low power supply voltage dependence.
An object of the present invention is to provide a band gap reference circuit that can obtain ref and a good minimum operation power supply voltage.

[0007]

A band gap reference circuit according to the present invention is a band gap reference circuit that obtains a constant reference voltage from an applied high-potential power supply and a low-potential power supply to an output terminal. A first conductivity-type first field-effect transistor having a source connected to the high-potential-side power supply; a drain and a gate connected to the drain of the first conductivity-type first field-effect transistor; A second conductivity type first field effect transistor connected to the low potential side power supply; a source connected to the high potential side power supply and a drain and a gate connected to the gate of the first conductivity type first field effect transistor A first conductive type second field effect transistor connected to the first conductive type second field effect transistor; a drain connected to the first conductive type second field effect transistor; Serial and sixth field-effect transistor of the second conductivity type connected to an output terminal, the drain is second
A second conductive type second field effect transistor having a gate connected to the source of the conductive type sixth field effect transistor and a gate connected to the gate of the second conductive type first field effect transistor; A first resistance element connected to the source of the second field-effect transistor of the second conductivity type and the other end connected to the low-potential-side power supply; a source connected to the high-potential-side power supply; A first conductivity type third field effect transistor having a drain connected to the output terminal and a first conductivity type third field effect transistor connected to the gate of the second conductivity type field effect transistor; A second resistor connected to the drain of the first resistor, a first diode having an anode connected to the other end of the second resistor, and a cathode connected to the low potential side power supply;
It is characterized by having.

A band gap reference circuit for obtaining a constant reference voltage from an applied high-potential power supply and a low-potential power supply at an output terminal, wherein a first source is connected to the high-potential power supply. A first conductivity-type field effect transistor; a second conductivity-type first field-effect transistor having a drain and a gate connected to the drain of the first conductivity-type first field-effect transistor and a source connected to the low potential side power supply; A first conductivity type second field effect transistor having a source connected to the high potential side power supply and a drain and a gate connected to the gate of the first conductivity type first field effect transistor; , A drain of the second field effect transistor of the first conductivity type and a gate of the second field effect transistor having a gate connected to the output terminal.
And a second conductivity type of which the drain is connected to the source of the sixth field effect transistor of the second conductivity type and the gate is connected to the gate of the first field effect transistor of the second conductivity type. A second field-effect transistor; a first resistance element having one end connected to the source of the second conductivity-type second field-effect transistor and the other end connected to the low-potential-side power supply; A first conductivity type third field effect transistor having a gate connected to the potential side power supply and a gate connected to the gate of the first conductivity type second field effect transistor; and a source having the first conductivity type third field effect transistor.
A first conductivity type fifth field effect transistor having a drain connected to the output terminal and a drain connected to the output terminal; and one end connected to the drain of the first conductivity type fifth field effect transistor. A second resistance element, a first diode having an anode connected to the other end of the second resistance element and a cathode connected to the low-potential-side power supply, and a source connected to the high-potential-side power supply A fourth field-effect transistor of the first conductivity type, a source connected to the drain of the fourth field-effect transistor of the first conductivity type, and a drain and a gate of the fifth field-effect transistor of the first conductivity type. And a drain connected to the drain of the sixth field effect transistor of the first conductivity type and having a source connected to the low field-effect transistor. Position gate is connected to the power supply is characterized in that it comprises a third field effect transistor of the second conductivity type connected to a gate of the first field effect transistor of the second conductivity type.

Further, instead of a direct connection between the drain of the first field-effect transistor of the first conductivity type and the drain and gate of the first field-effect transistor of the second conductivity type, the source is changed to the first conductivity-type. And a drain connected to the drain and gate of the first field effect transistor of the second conductivity type and a gate connected to the gate of the sixth field effect transistor of the first conductivity type. And a seventh field-effect transistor of the first conductivity type connected to the first transistor.

Further, instead of the direct connection between the drain and the gate of the sixth field effect transistor of the first conductivity type and the drain of the third field effect transistor of the second conductivity type, the source is replaced with the second conductivity type. A third field effect transistor of the second conductivity type, a drain connected to the drain and gate of the sixth field effect transistor of the first conductivity type, and a gate connected to the output terminal; And a field effect transistor.

A band gap reference circuit for obtaining a constant reference voltage from an applied high-potential-side power supply and a low-potential-side power supply at an output terminal, wherein a source is connected to the high-potential-side power supply. A first conductivity-type first field-effect transistor, and a first conductivity-type eighth field-effect transistor whose source is connected to the drain of the first conductivity-type first field-effect transistor.
A second conductivity type first field effect transistor having a drain and a gate connected to the drain of the first conductivity type eighth field effect transistor and a source connected to the low potential side power supply; A first conductivity type second field effect transistor having a source connected to the high potential side power supply and a drain and a gate connected to the gate of the first conductivity type first field effect transistor; A sixth field effect transistor of a second conductivity type connected to a drain of a second field effect transistor of one conductivity type and a gate connected to the output terminal; and a sixth field effect transistor of a drain type of the second conductivity type A second field-effect transistor of a second conductivity type connected to the source of the transistor and having a gate connected to the gate of the first field-effect transistor of the second conductivity type A first resistance element having one end connected to the source of the second field-effect transistor of the second conductivity type and the other end connected to the low-potential-side power supply; and a source connected to the high-potential-side power supply. A third field-effect transistor of the first conductivity type having a gate connected to the gate of the second field-effect transistor of the first conductivity type; and a source connected to the drain of the third field-effect transistor of the first conductivity type. A ninth field-effect transistor of a first conductivity type connected and having a drain connected to the output terminal; a second resistance element having one end connected to the drain of the ninth field-effect transistor of the first conductivity type; A first diode having an anode connected to the other end of the second resistance element and a cathode connected to the low-potential-side power supply, the first diode being connected to the high-potential-side power supply and the low-potential-side power supply; of A starting unit for pulling down the gate of the second field effect transistor, characterized in that it comprises a.

The activation unit may include a source connected to the high-potential-side power supply and a gate connected to the gate of the second field-effect transistor of the first conductivity type. A transistor and a source are connected to the drain of the tenth field effect transistor of the first conductivity type, and the drain and the gate are the eighth and ninth transistors of the first conductivity type.
An eleventh field-effect transistor of the first conductivity type connected to the gate of the field-effect transistor of the first type; a drain and a gate connected to the drain of the eleventh field-effect transistor of the first conductivity type; An eighth field-effect transistor of a second conductivity type connected to a power supply, a third resistance element having one end connected to the high-potential-side power supply,
A drain of the second conductivity type, a drain connected to the other end of the third resistance element, a source connected to the low potential side power supply, and a gate connected to the gate of the eighth field effect transistor of the second conductivity type; And a drain connected to the gate of the second field effect transistor of the first conductivity type, a source connected to the lower potential side power supply, and a gate connected to the ninth field effect transistor of the second conductivity type. And a tenth field-effect transistor of the second conductivity type connected to the drain of the transistor.

A band gap reference circuit for obtaining a constant reference voltage from an applied high-potential power supply and a low-potential power supply to an output terminal, wherein a first source having a source connected to the high-potential power supply A twelfth field-effect transistor of a conductivity type, and a thirteenth field-effect transistor of a first conductivity type having a source connected to the high potential side power supply and a drain and a gate connected to the gate of the twelfth field effect transistor of the first conductivity type
A field-effect transistor having a source connected to the high-potential-side power supply, a drain connected to the output terminal, and a gate connected to the drain of the twelfth field-effect transistor of the first conductivity type. A fourteenth field-effect transistor of the second conductivity type having a drain connected to the drain of the twelfth field-effect transistor of the first conductivity type and a gate connected to the output terminal; A fourteenth field effect transistor of a second conductivity type connected to the drain of the thirteenth field effect transistor of the first conductivity type and a gate connected to the output terminal; and a fourth field effect transistor of one end connected to the output terminal. A second diode having an anode connected to the other end of the fourth resistance element and a cathode connected to the low-potential-side power supply; A fifth resistor connected to the output terminal and the other end connected to the node, a sixth resistor connected at one end to the node, and an anode connected to the other end of the sixth resistor; A third diode having a cathode connected to the low-potential-side power supply; a third diode having a drain connected to the source of the thirteenth field-effect transistor of the second conductivity type and a gate connected to the anode of the second diode. 2
An eleventh field effect transistor of a conductivity type, a twelfth field effect transistor of a second conductivity type having a drain connected to the source of the fourteenth field effect transistor of the second conductivity type and a gate connected to the node; A constant current source having one end connected to the sources of the eleventh and twelfth field effect transistors of the second conductivity type and the other end connected to the low potential side power supply.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a band gap reference circuit according to a first embodiment of the present invention. As shown in FIG. 1, the band gap reference circuit according to the first embodiment of the present invention includes P-type MOS transistors P1 to P3 and an N-type MOS transistor N1,
N2 and N6, a diode D1, and resistance elements R1 and R2.
And a constant reference voltage Vref is obtained from the low-potential-side power supply GND at the output terminal ref.

The source of the P-type MOS transistor P1 is connected to the high potential power supply VDD. The drain and the gate of the N-type MOS transistor N1 are connected to the drain of the P-type MOS transistor P1.
1 is connected to the low potential power supply GND.

The source of the P-type MOS transistor P2 is connected to the high potential side power supply VDD, and the drain and gate of the P-type MOS transistor P2 are connected to the P-type MOS transistor P2.
1 gate. N-type MOS transistor N6
Is connected to the drain of the P-type MOS transistor P2, and the gate of the N-type MOS transistor N6 is connected to the output terminal ref.

The drain of the N-type MOS transistor N2 is connected to the source of the N-type MOS transistor N6, and the gate of the N-type MOS transistor N2 is connected to the gate of the N-type MOS transistor N1. One end of the resistance element R1 is connected to the source of the N-type MOS transistor N2, and the other end of the resistance element R1 is connected to the low potential power supply GND.

The source of the P-type MOS transistor P3 is connected to the high potential power supply VDD, the gate of the P-type MOS transistor P3 is connected to the gate of the P-type MOS transistor P2, and the drain of the P-type MOS transistor P3 is the output terminal ref. Connected to. One end of the resistance element R2 is connected to the drain of the P-type MOS transistor P3, the anode of the diode D1 is connected to the other end of the resistance element R2,
The cathode of the diode D1 is connected to the lower potential power supply GND.

In the above configuration, for example, a P-type M
The gate length and the gate width of the OS transistors P1, P2 and P3 are the same size, the gate length of the N-type MOS transistor N2 is the same size as the N-type MOS transistor N1, the gate width is M times, and the N-type MOS transistor The gate length and gate width of N1 and N6 are the same.

Next, the operation will be described. With the above configuration,
For example, even if the voltage between the high-potential-side power supply VDD and the low-potential-side power supply GND fluctuates to increase, the drain potential of the N-type MOS transistor N2 changes from the reference voltage Vref to the N-type M
Since the potential is fixed at a lower potential by the gate-source voltage of the OS transistor N6 and the drain-source voltage fluctuation of the N-type MOS transistor N2 is suppressed, Δid in the expression 2 is obtained.
(1) is reduced, ΔVref in Equation 3 is reduced, the influence of the Early effect is reduced, and the reference voltage Vref shown in Equation 1 with less power supply voltage dependence is obtained.

Further, for example, the reference voltage Vref is set to 1.
25V, the threshold voltage of the depletion type N-type MOS transistor N4 is set to 0V, and the enhancement type N
Assuming that the threshold voltage of the MOS transistor N6 is 0.6 V, the drain potential of the N-type MOS transistor N2 in the band gap reference circuit of the present embodiment and the band gap of the second conventional example shown in FIG. Since the drain potential of the N-type MOS transistor N2 in the reference circuit has substantially the same bias, the band gap reference circuit of the present embodiment has the same good minimum potential as the second conventional band gap reference circuit. An operating power supply voltage is obtained.

As described above, according to the present configuration, only the enhancement type MOS transistors are used.
A band gap reference circuit with low power supply voltage dependency and a good minimum operation power supply voltage can be realized.

FIG. 2 is a configuration diagram of a band gap reference circuit according to a second embodiment of the present invention. The band gap reference circuit according to the second embodiment of the present invention includes P-type MOS transistors P1 to P6.
And N-type MOS transistors N1, N2, N3 and N6
, A diode D1, and resistance elements R1 and R2, and obtains a constant reference voltage from an applied high-potential power supply VDD and low-potential power supply GND to an output terminal.

The source of the P-type MOS transistor P1 is connected to the high potential power supply VDD. The drain and the gate of the N-type MOS transistor N1 are connected to the drain of the P-type MOS transistor P1.
1 is connected to the low potential power supply GND.

The source of the P-type MOS transistor P2 is connected to the high potential power supply VDD, and the drain and gate of the P-type MOS transistor P2 are connected to the P-type MOS transistor P2.
1 gate. N-type MOS transistor N6
Is connected to the drain of the P-type MOS transistor P2, and the gate of the N-type MOS transistor N6 is connected to the output terminal ref.

The drain of the N-type MOS transistor N2 is connected to the source of the N-type MOS transistor N6, and the gate of the N-type MOS transistor N2 is connected to the gate of the N-type MOS transistor N1. One end of the resistance element R1 is connected to the source of the N-type MOS transistor N2, and the other end of the resistance element R1 is connected to the low potential power supply GND.

The source of the P-type MOS transistor P3 is connected to the high potential power supply VDD, and the gate of the P-type MOS transistor P3 is connected to the gate of the P-type MOS transistor P2. The source of the P-type MOS transistor P5 is P
The drain of the p-type MOS transistor P3 is connected to the drain of the p-type MOS transistor P3, and the drain of the p-type MOS transistor P5 is connected to the output terminal ref. One end of the resistance element R2 is connected to the drain of the P-type MOS transistor P5. The anode of the diode D1 is connected to the other end of the resistor R2,
1 is connected to the low-potential-side power supply GND.

The source of the P-type MOS transistor P4 is connected to the high potential power supply VDD, and the gate of the P-type MOS transistor P4 is connected to the drain of the P-type MOS transistor P4. The source of the P-type MOS transistor P6 is connected to the drain of the P-type MOS transistor P4.
The drain and the gate of the p-type MOS transistor P6 are connected to the gate of the p-type MOS transistor P5. N type M
The drain of the OS transistor N3 is connected to the drain of the P-type MOS transistor P6, the source of the N-type MOS transistor N3 is connected to the lower potential power supply GND, and the gate of the N-type MOS transistor N3 is connected to the gate of the N-type MOS transistor N1. Connected.

In the above configuration, for example, a P-type M
The gate lengths and the gate widths of the OS transistors P1 to P6 are the same, and the N-type MOS transistor N1
In contrast, the gate length of the N-type MOS transistor N2 is the same size, the gate width is M times, and the gate length and the gate width of the N-type MOS transistors N1, N3 and N6 are the same size.

Next, the operation will be described. With the above configuration,
For example, even if the voltage between the high-potential-side power supply VDD and the low-potential-side power supply GND fluctuates so as to increase, the drain-source voltage VDS (P3) of the P-type MOS transistor P3 and the gate-source of the P-type MOS transistor P2 Intermediate voltage VGS
(P2) becomes equal, Δid (2) in equation 2 becomes 0, and the drain potential of the N-type MOS transistor N2 changes from the reference voltage Vref to the N-type MOS transistor N6.
Is fixed at a potential lower by the gate-source voltage of
Since the drain-source voltage fluctuation of the OS transistor N2 is suppressed, Δid (1) in Equation 2 is reduced, ΔVref in Equation 3 is reduced, the influence of the Early effect is reduced, and the power supply voltage dependence is reduced. The reference voltage Vref shown in FIG.

Further, the N-type MOS transistor N in the band gap reference circuit of the present embodiment
2 in the band gap reference circuit shown in FIG. 1 according to the first embodiment of the present invention.
Since the drain potential of the type MOS transistor N2 is the same, the band gap reference circuit of the present embodiment is the same good as the band gap reference circuit of the first embodiment of the present invention shown in FIG. A minimum operating power supply voltage can be obtained.

As described above, according to the present embodiment, only the enhancement type MOS transistor is used, and the power supply voltage dependency is lower than that of the first embodiment of the present invention. A good band gap reference circuit can be realized.

Next, FIG. 3 is a configuration diagram of a band gap reference circuit according to a third embodiment of the present invention. The difference between the band gap reference circuit according to the third embodiment of the present invention and the band gap reference circuit according to the second embodiment of the present invention shown in FIG. P7 is added and P
Instead of the direct connection between the drain of the P-type MOS transistor P1 and the drain and gate of the N-type MOS transistor N1, the source of the P-type MOS transistor P7 is a P-type MOS transistor.
The drain of the P-type MOS transistor P7 is connected to the drain of the transistor P1 and the N-type MOS transistor N
1 are connected to the drain and gate of the P-type MOS transistor P7, and the gate of the P-type MOS transistor P7 is connected to the gate of the P-type MOS transistor P6, and the other parts are the same. The description is omitted.

In the above structure, for example, a P-type M
The gate length and the gate width of the OS transistors P1 to P7 are the same, and the N-type MOS transistor N1
In contrast, the gate length of the N-type MOS transistor N2 is the same size, the gate width is M times, and the gate length and the gate width of the N-type MOS transistors N1, N3 and N6 are the same size.

Next, the operation will be described. With the above configuration,
For example, even if the voltage between the high-potential-side power supply VDD and the low-potential-side power supply GND fluctuates so as to increase, the drain-source voltage VDS (P3) of the P-type MOS transistor P3 and the gate-source of the P-type MOS transistor P2 Intermediate voltage VGS
(P2) becomes equal, Δid (2) in equation 2 becomes 0, and the drain potential of the N-type MOS transistor N2 changes from the reference voltage Vref to the N-type MOS transistor N6.
Is fixed at a potential lower by the gate-source voltage of
The fluctuation of the drain-source voltage of the OS transistor N2 is suppressed, and the drain-source voltage VDS (P1) of the P-type MOS transistor P1 is equal to the gate-source voltage VGS (P2) of the P-type MOS transistor P2. As a result, Δid (1) in equation (2) further decreases, ΔVref in equation (3) further decreases, the effect of the Early effect is reduced, and the reference voltage Vref shown in equation (1) with less power supply voltage dependence is obtained.

Further, the N-type MOS transistor N in the band gap reference circuit of the present embodiment
2 and the N in the band gap reference circuit of the second embodiment of the present invention shown in FIG.
Since the drain potential of the type MOS transistor N2 is the same, the band gap reference circuit of the present embodiment is the same as the band gap reference circuit of the second embodiment of the present invention shown in FIG. A minimum operating power supply voltage can be obtained.

As described above, according to the present embodiment, only the enhancement type MOS transistor is used, and the power supply voltage dependency is further reduced as compared with the second embodiment of the present invention, and the minimum operation power supply voltage is also reduced. A good band gap reference circuit can be realized.

FIG. 4 is a block diagram of a band gap reference circuit according to a fourth embodiment of the present invention. The difference between the band gap reference circuit according to the fourth embodiment of the present invention and the band gap reference circuit according to the third embodiment of the present invention shown in FIG. N7 is added and P
Instead of the direct connection between the drain and gate of the N-type MOS transistor P6 and the drain of the N-type MOS transistor N3, the source of the N-type
The drain of the N-type MOS transistor N7 is connected to the drain of the transistor N3.
6 is a portion connected to the drain and gate of the N-type MOS transistor N7 and the gate of the N-type MOS transistor N7 is connected to the output terminal ref, and the other portions are the same. Is omitted.

In the above structure, for example, a P-type M
The gate length and the gate width of the OS transistors P1 to P7 are the same, and the N-type MOS transistor N1
On the other hand, the gate length of the N-type MOS transistor N2 is the same size, the gate width is M times, and the gate length and the gate width of the N-type MOS transistors N1, N3, N6 and N7 are the same size.

Next, the operation will be described. With the above configuration,
For example, even if the voltage between the high-potential-side power supply VDD and the low-potential-side power supply GND fluctuates so as to increase, the drain-source voltage VDS (P3) of the P-type MOS transistor P3 and the gate-source of the P-type MOS transistor P2 Intermediate voltage VGS
(P2) becomes equal, Δid (2) in equation 2 becomes 0, and the drain potential of the N-type MOS transistor N2 changes from the reference voltage Vref to the N-type MOS transistor N6.
Is fixed at a potential lower by the gate-source voltage of
The fluctuation of the drain-source voltage of the OS transistor N2 is suppressed, and the drain-source voltage VDS (P1) of the P-type MOS transistor P1 is equal to the gate-source voltage VGS (P2) of the P-type MOS transistor P2. Further, the drain potential of the N-type MOS transistor N3 is fixed to a potential lower than the reference voltage Vref by the voltage between the gate and the source of the N-type MOS transistor N7, so that the fluctuation of the drain-source voltage of the N-type MOS transistor N3 is suppressed. Δid (1) in equation 2 becomes 0, and ΔVref in equation 3 becomes 0, so that the reference voltage V shown in equation 1 is not affected by the Early effect and has no power supply voltage dependency.
ref is obtained.

Further, the N-type MOS transistor N in the band gap reference circuit of the present embodiment
2 and N in the band gap reference circuit of the third embodiment of the present invention shown in FIG.
Since the drain potential of the type MOS transistor N2 is the same, the band gap reference circuit of the present embodiment is the same as the band gap reference circuit of the third embodiment of the present invention shown in FIG. A minimum operating power supply voltage can be obtained.

As described above, according to the present embodiment, only the enhancement type MOS transistors are used, and the power supply voltage dependency and the minimum operating power supply voltage are lower than those of the third embodiment of the present invention. A good band gap reference circuit can be realized.

Next, FIG. 5 is a configuration diagram of a band gap reference circuit according to a fifth embodiment of the present invention. As shown in FIG. 5, the band gap reference circuit according to the fifth embodiment of the present invention comprises P-type MOS transistors P1 to P3, P8 and P9, N-type MOS transistors N1, N2 and N6, a diode D1, resistance elements R1 and R2, and reference voltage Vref at power-on.
And a starting unit ST for shortening the starting time of the starting device. The starting unit ST includes P-type MOS transistors P10 and P11, N-type MOS transistors N8 to N10, and a resistance element R3. Constant reference voltage Vr from the supplied high-potential power supply VDD and low-potential power supply GND.
ef is obtained at the output terminal ref.

The source of the P-type MOS transistor P1 is connected to the high potential power supply VDD. The source of the P-type MOS transistor P8 is connected to the drain of the P-type MOS transistor P1. The drain and the gate of the N-type MOS transistor N1 are connected to the drain of the P-type MOS transistor P8, and the source of the N-type MOS transistor N1 is connected to the lower potential power supply GND.

The source of the P-type MOS transistor P2 is connected to the high potential side power supply VDD, and the drain and gate of the P-type MOS transistor P2 are connected to the P-type MOS transistor P2.
1 gate. N-type MOS transistor N6
Is connected to the drain of the P-type MOS transistor P2, and the gate of the N-type MOS transistor N6 is connected to the output terminal ref. N-type MOS transistor N2
Is connected to the source of an N-type MOS transistor N6, and the gate of the N-type MOS transistor N2 is connected to an N-type MOS transistor N6.
Connected to the gate of OS transistor N1. One end of the resistance element R1 is connected to the source of the N-type MOS transistor N2, and the other end of the resistance element R1 is connected to the low potential power supply GND.

The source of the P-type MOS transistor P3 is connected to the high potential power supply VDD, and the gate of the P-type MOS transistor P3 is connected to the gate of the P-type MOS transistor P2. The source of the P-type MOS transistor P9 is P
The drain of the p-type MOS transistor P3 is connected to the drain of the p-type MOS transistor P3, and the drain of the p-type MOS transistor P9 is connected to the output terminal ref. One end of resistance element R2 is connected to the drain of P-type MOS transistor P9. The anode of the diode D1 is connected to the other end of the resistor R2,
1 is connected to the low-potential-side power supply GND.

Further, the starting unit ST includes a high-potential-side power supply VD
When D and the low-potential-side power supply GND are turned on, the gate of the P-type MOS transistor P2 is pulled down.

Then, in the starting section ST, the P-type MOS
The source of the transistor P10 is connected to the high potential side power supply VDD, and the gate of the P-type MOS transistor P10 is connected to the gate of the P-type MOS transistor P2. P type M
The source of the OS transistor P11 is connected to the drain of the P-type MOS transistor P10, and the drain and gate of the P-type MOS transistor P11 are connected to the gates of the P-type MOS transistors P8 and P9. The drain and the gate of the N-type MOS transistor N8 are connected to the drain of the P-type MOS transistor P11, and the source of the N-type MOS transistor N8 is connected to the lower potential power supply GND.

One end of the resistance element R3 is connected to the high potential side power supply VDD.
Connected to. The drain of the N-type MOS transistor N9 is connected to the other end of the resistance element R3, the source of the N-type MOS transistor N9 is connected to the lower potential power supply GND, and
The gate of the N-type MOS transistor N9 is connected to the gate of the N-type MOS transistor N8. The drain of the N-type MOS transistor N10 is connected to the gate of the P-type MOS transistor P2, the source of the N-type MOS transistor N10 is connected to the lower potential power supply GND, and the gate of the N-type MOS transistor N10 is connected to the N-type MOS transistor N9.
Connected to the drain of

In the above structure, for example, a P-type M
The gate lengths and gate widths of the OS transistors P1 to P3 and P8 to P11 are the same size, the gate length of the N-type MOS transistor N2 is the same size as the N-type MOS transistor N1, the gate width is M times, and the N-type MOS transistor N1 is N-type. M
The gate length and the gate width of the OS transistors N1, N6, N8 to N10 are the same size.

Next, the operation will be described. With the above configuration,
For example, even if the voltage between the high-potential-side power supply VDD and the low-potential-side power supply GND fluctuates so as to increase, the drain potential of the P-type MOS transistor P3 changes from the low-potential-side power supply GND potential to the gate of the N-type MOS transistor N8. Source voltage V
GS (N8) and the gate of the P-type MOS transistor P9
When the potential becomes the sum of the source-source voltage VGS (P9) and the drain-source voltage VDS (P3) of the P-type MOS transistor P3, the potential VDS (P3) is reduced.
(2) is reduced, and the drain potential of the N-type MOS transistor N2 is fixed to a potential lower than the reference voltage Vref by the voltage between the gate and source of the N-type MOS transistor N6. The fluctuation of the inter-voltage is suppressed, and the drain potential of the P-type MOS transistor P1 is changed from the low-potential-side power supply GND potential to the gate-source voltage VGS (N8) of the N-type MOS transistor N8 and the gate and source of the P-type MOS transistor P8. The potential VDS (P1) of the P-type MOS transistor P1 can be kept low by setting the potential to the sum of the potential VDS (P8) and the drain-source voltage VDS (P1) of the P-type MOS transistor P1.
(1) is reduced, ΔVref in Equation 3 is reduced, the influence of the Early effect is reduced, and the reference voltage Vref shown in Equation 1 with less power supply voltage dependence is obtained.

Further, the N-type MOS transistor N in the band gap reference circuit of the present embodiment
2 and the N in the band gap reference circuit of the second embodiment of the present invention shown in FIG.
Since the drain potential of the type MOS transistor N2 is the same, the band gap reference circuit of the present embodiment is the same as the band gap reference circuit of the second embodiment of the present invention shown in FIG. A minimum operating power supply voltage can be obtained.

Next, the operation of the starting unit ST will be described. At the moment when the power is turned on, the gate potentials of the P-type MOS transistors P1 to P3 and P10 forming the current mirror are changed to the high potential side power supply VDD via the respective gate-source capacitances.
Similarly, the gate potentials of the N-type MOS transistors N1 and N2 forming the current mirror are set to the low-potential power supply GND potential via the respective gate-source capacitances.

However, immediately after the power is turned on, the gate of the N-type MOS transistor N10 is pulled up to the high-potential-side power supply VDD potential by the resistance element R3.
The transistor N10 is reliably turned on, the gate potentials of the P-type MOS transistors P1 to P3 and P10 are pulled down, and the P-type MOS transistors P1 to P3 and P10
, Each bias current is generated, forcibly activated as a band gap reference circuit, and the activation time is shortened.

When a bias current flows through the P-type MOS transistor P10, the P-type MOS transistor P1
1 and the N-type MOS transistors N8 and N9, a bias current also flows. Therefore, the drain potential of the N-type MOS transistor N9 becomes the low potential side power supply GND potential,
The S transistor N10 returns to the off state.

As described above, according to the present embodiment, only the enhancement type MOS transistor is used, and the power supply voltage dependency is lower than that of the second embodiment of the present invention. It is possible to realize a band gap reference circuit which is favorable and has a reduced start-up time at power-on.

FIG. 6 is a block diagram of a band gap reference circuit according to a sixth embodiment of the present invention. As shown in FIG. 6, the band gap reference circuit according to the sixth embodiment of the present invention includes P-type MOS transistors P12 to P14 and an N-type MOS transistor N.
11 to N14, diodes D2 and D3, resistance elements R4 to R6, and a constant current source I1, and outputs a constant reference voltage Vref from a given high-potential power supply VDD and low-potential power supply GND. Obtain at terminal ref.

N-type MOS transistors N11 and N12
Constitutes a differential pair in the differential amplifier stage, and P-type MOS transistors P12 and P13 constitute an active load of the differential pair.

The source of the P-type MOS transistor P12 is connected to the high potential power supply VDD. The source of the P-type MOS transistor P13 is connected to the high potential side power supply VDD,
The drain and the gate of the P-type MOS transistor P13 are connected to the gate of the P-type MOS transistor P12.

The source of the P-type MOS transistor P14 is connected to the high potential side power supply VDD, the drain of the P-type MOS transistor P14 is connected to the output terminal ref, and the gate of the P-type MOS transistor P14 is connected to the drain of the P-type MOS transistor P12. Connected to.

The drain of the N-type MOS transistor N13 is connected to the drain of the P-type MOS transistor P12, and the gate of the N-type MOS transistor N13 is connected to the output terminal ref. The drain of the N-type MOS transistor N14 is connected to the drain of the P-type MOS transistor P13, and the gate of the N-type MOS transistor N14 is connected to the output terminal ref.

One end of the resistance element R4 is connected to the output terminal ref. The anode of the diode D2 is connected to the other end of the resistance element R4, and the cathode of the diode D2 is connected to the low potential power supply GND.

One end of the resistor R5 is connected to the output terminal ref, and the other end of the resistor R5 is connected to the node A. One end of resistance element R6 is connected to node A. Diode D
The anode of the diode 3 is connected to the other end of the resistor R6, and the cathode of the diode D3 is connected to the low-potential-side power supply GND.

The drain of the N-type MOS transistor N11 is connected to the source of the N-type MOS transistor N13.
The gate of the N-type MOS transistor N11 is a diode D
2 anodes. N-type MOS transistor N
The drain of the transistor 12 is connected to the source of the N-type MOS transistor N14, and the gate of the N-type MOS transistor N12 is connected to the node A.

One end of the constant current source I1 is connected to the sources of N-type MOS transistors N11 and N12.
The other end of 1 is connected to the low potential side power supply GND.

In the above configuration, for example, a P-type M
The OS transistors P12 to P14 have the same gate length and gate width, and the N-type MOS transistors N11 to N14 have the same gate length and gate width.

Next, the operation will be described. With the above configuration,
For example, even if the voltage between the high-potential-side power supply VDD and the low-potential-side power supply GND fluctuates to increase, the drain potential of the N-type MOS transistor N11 changes from the reference voltage Vref to the gate-source voltage of the N-type MOS transistor N13. The drain potential of the N-type MOS transistor N12 is fixed to a potential lower than the reference voltage Vref, and the drain potential of the N-type MOS transistor N12 is lower than the reference voltage Vref by the gate-source voltage of the N-type MOS transistor N14. N-type MOS transistor N1 fixed at potential
2 can suppress the voltage fluctuation between the drain and the source.
The N-type MOS transistors N11 and N12 are not affected by the Early effect, and the gate potentials of the N-type MOS transistors N11 and N12 are always equal to each other.

Therefore, the resistance value of the resistance elements R4 and R5 is set to N 'times the resistance value of the resistance element R6, and the diode D
Assuming that M ′ is connected in parallel to M ′ diodes D2, q is the charge of electrons, k is the Boltzmann constant, T is the absolute temperature, VF (D2) is the forward voltage of the diode D2 from the output terminal ref. Equation 4 having no power supply voltage dependency
The reference voltage Vref shown in FIG. Vref = N ′ × (k × T ÷ q) × lnM ′ + VF (D2) (Equation 4) Further, the N-type MOS transistors N11 and N1 in the band gap reference circuit of the present embodiment.
2 in the band gap reference circuit shown in FIG. 1 according to the first embodiment of the present invention.
Since the drain potential of the type MOS transistor N2 is the same, the band gap reference circuit of the present embodiment is the same good as the band gap reference circuit of the first embodiment of the present invention shown in FIG. A minimum operating power supply voltage can be obtained.

As described above, according to the present embodiment, it is possible to realize a band gap reference circuit which is composed of only the enhancement type MOS transistors, has no power supply voltage dependence, and has a good minimum operation power supply voltage.

[0070]

As described above, the band of the present invention
The first effect of the gap reference circuit is that it is composed of only enhancement-type MOS transistors,
A second effect is that a band gap reference circuit that can obtain a reference voltage Vref with little power supply voltage dependency and a good minimum operation power supply voltage can be realized. The third effect is that a reference circuit can be realized. The third effect is that an inexpensive band gap reference circuit can be realized because a depletion type MOS transistor is not used. The fourth effect is that a depletion type MOS transistor is used. Therefore, a band gap reference circuit applicable to products requiring low current consumption and a small chip size, such as a battery-powered timepiece, can be realized.

[0071]

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a band gap reference circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a band gap reference circuit according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a band gap reference circuit according to a third embodiment of the present invention.

FIG. 4 is a configuration diagram of a band gap reference circuit according to a fourth embodiment of the present invention.

FIG. 5 is a configuration diagram of a band gap reference circuit according to a fifth embodiment of the present invention.

FIG. 6 is a configuration diagram of a band gap reference circuit according to a sixth embodiment of the present invention.

FIG. 7 is a configuration diagram of a first conventional band gap reference circuit.

FIG. 8 is a configuration diagram of a band gap reference circuit of a second conventional example.

[Explanation of symbols]

 P1 to P14 P-type MOS transistor N1 to N14 N-type MOS transistor R1 to R6 Resistance element D1 to D3 Diode I1 Constant current source ST Starter

Claims (7)

[Claims] 1. A band-gap reference circuit for obtaining a constant reference voltage from an applied high-potential power supply and a low-potential power supply to an output terminal, wherein a first source is connected to the high-potential power supply. A first conductivity-type field effect transistor; a second conductivity-type first field-effect transistor having a drain and a gate connected to the drain of the first conductivity-type first field-effect transistor and a source connected to the low potential side power supply; And a drain of the first conductivity type having a source connected to the high potential side power supply and a drain and a gate connected to the gate of the first field effect transistor of the first conductivity type.
A sixth field-effect transistor of the second conductivity type, the drain of which is connected to the drain of the second field-effect transistor of the first conductivity type and the gate of which is connected to the output terminal; A second conductivity-type second field-effect transistor having a gate connected to the source of the sixth field-effect transistor of the second conductivity type and a gate connected to the gate of the first field-effect transistor of the second conductivity type; Is connected to the source of the second field-effect transistor of the second conductivity type, and the other end is connected to the low-potential-side power supply, and the source is connected to the high-potential-side power supply and the gate is A third field-effect transistor of the first conductivity type connected to the gate of the second field-effect transistor of the first conductivity type and a drain connected to the output terminal;
A second resistance element having one end connected to the drain of the third field effect transistor of the first conductivity type, an anode connected to the other end of the second resistance element, and a cathode connected to the low potential side power supply And a first diode to be used. 2. A band gap reference circuit for obtaining a constant reference voltage from an applied high-potential power supply and a low-potential power supply to an output terminal, wherein a first source is connected to the high-potential power supply. A first conductivity-type field effect transistor; a second conductivity-type first field-effect transistor having a drain and a gate connected to the drain of the first conductivity-type first field-effect transistor and a source connected to the low potential side power supply; And a drain of the first conductivity type having a source connected to the high potential side power supply and a drain and a gate connected to the gate of the first field effect transistor of the first conductivity type.
A sixth field-effect transistor of the second conductivity type, the drain of which is connected to the drain of the second field-effect transistor of the first conductivity type and the gate of which is connected to the output terminal; A second conductivity-type second field-effect transistor having a gate connected to the source of the sixth field-effect transistor of the second conductivity type and a gate connected to the gate of the first field-effect transistor of the second conductivity type; Is connected to the source of the second field-effect transistor of the second conductivity type, and the other end is connected to the low-potential-side power supply, and the source is connected to the high-potential-side power supply and the gate is A third field-effect transistor of the first conductivity type connected to the gate of the second field-effect transistor of the first conductivity type; and a third field-effect transistor of the source having the first conductivity type. A fifth field effect transistor of a first conductivity type, the drain of which is connected to the output terminal, and a second end, one end of which is connected to the drain of the fifth field effect transistor of the first conductivity type. A resistance element, a first diode having an anode connected to the other end of the second resistance element and a cathode connected to the low-potential-side power supply, and a first conductivity type having a source connected to the high-potential-side power supply And the source is the first field effect transistor.
A sixth field-effect transistor of the first conductivity type, connected to the drain of a fourth field-effect transistor of the first conductivity type, the drain and the gate of which are connected to the gate of the fifth field-effect transistor of the first conductivity type; Are connected to the drain of the sixth field-effect transistor of the first conductivity type, the source is connected to the low potential side power supply, and the gate is the second
A third field effect transistor of a second conductivity type connected to the gate of the first field effect transistor of the conductivity type. 3. The semiconductor device according to claim 1, wherein a source of the first field-effect transistor of the first conductivity type is directly connected to a drain and a gate of the first field-effect transistor of the second conductivity type. And a drain connected to the drain and gate of the first field effect transistor of the second conductivity type and a gate connected to the gate of the sixth field effect transistor of the first conductivity type. 3. The band gap reference circuit according to claim 2, further comprising a seventh field-effect transistor of a first conductivity type connected to the first transistor. 4. A method according to claim 1, wherein the source and the drain of the sixth field effect transistor of the first conductivity type are directly connected to the drain of the third field effect transistor of the second conductivity type. A third field effect transistor of the second conductivity type, a drain connected to the drain and gate of the sixth field effect transistor of the first conductivity type, and a gate connected to the output terminal; 4. The band gap reference circuit according to claim 3, further comprising: a field effect transistor. 5. A band gap reference circuit for obtaining a constant reference voltage from an applied high-potential power supply and a low-potential power supply to an output terminal, wherein a first source is connected to the high-potential power supply. A first conductivity-type first field-effect transistor; a first conductivity-type eighth field-effect transistor whose source is connected to the drain of the first conductivity-type first field-effect transistor; 1
A second conductivity type first field effect transistor having a source connected to the low potential side power supply and a source connected to the drain of the eighth conductivity type field effect transistor; a drain having a source connected to the high potential side power supply; A second field-effect transistor of the first conductivity type having a gate connected to the gate of the first field-effect transistor of the first conductivity type; and a drain connected to the drain of the second field-effect transistor of the first conductivity type. A sixth field effect transistor of a second conductivity type connected to the output terminal and a gate connected to the output terminal; a drain connected to a source of the sixth field effect transistor of the second conductivity type and a gate connected to the second conductivity type; A second field-effect transistor of a second conductivity type connected to the gate of the first field-effect transistor, and one end of the second field-effect transistor of the second conductivity type A first resistance element connected to a source and the other end connected to the low-potential-side power supply; a source connected to the high-potential-side power supply and a gate connected to the gate of the second field-effect transistor of the first conductivity type A first conductive type third field effect transistor connected to the first conductive type third field effect transistor; a first conductive type third field effect transistor having a source connected to the drain of the first conductive type third field effect transistor and a drain connected to the output terminal; Nine field effect transistors, a second resistance element having one end connected to the drain of the ninth field effect transistor of the first conductivity type, and an anode connected to the other end of the second resistance element and a cathode connected to the other end. A first diode connected to the low-potential power supply, and activation for pulling down a gate of the second field-effect transistor of the first conductivity type when the high-potential power supply and the low-potential power supply are turned on. Band gap reference circuit which is characterized in that it comprises, and. 6. The first conductive type tenth transistor of which the source is connected to the high potential side power supply and the gate is connected to the gate of the first conductive type second field effect transistor.
And the source is connected to the drain of the tenth field effect transistor of the first conductivity type, and the drain and gate are connected to the gates of the eighth and ninth field effect transistors of the first conductivity type. An eleventh field-effect transistor of the first conductivity type; and a second conductivity type of which the drain and the gate are connected to the drain of the eleventh field-effect transistor of the first conductivity type and the source is connected to the low potential side power supply. An eighth field-effect transistor, a third resistance element having one end connected to the high-potential-side power supply, a drain connected to the other end of the third resistance element, and a source connected to the low-potential-side power supply A ninth field-effect transistor of the second conductivity type, the gate of which is connected to the gate of the eighth field-effect transistor of the second conductivity type; A second conductivity type tenth field effect transistor having a source connected to the gate of the field effect transistor, a source connected to the low potential side power supply, and a gate connected to the drain of the second conductivity type ninth field effect transistor; The band gap reference circuit according to claim 5, comprising: 7. A band gap reference circuit for obtaining a constant reference voltage from an applied high-potential-side power supply and a low-potential-side power supply to an output terminal, wherein a source is connected to the high-potential-side power supply. A twelfth field-effect transistor of a conductivity type, and a thirteenth field-effect transistor of a first conductivity type having a source connected to the high potential side power supply and a drain and a gate connected to the gate of the twelfth field effect transistor of the first conductivity type A field-effect transistor having a source connected to the high-potential-side power supply, a drain connected to the output terminal, and a gate connected to the drain of the twelfth field-effect transistor of the first conductivity type. 14 field-effect transistors, and a second conductor having a drain connected to the drain of the twelfth field-effect transistor of the first conductivity type and a gate connected to the output terminal. A thirteenth field-effect transistor of a second conductivity type, a drain connected to the drain of the thirteenth field-effect transistor of the first conductivity type, and a gate connected to the output terminal; A fourth diode having one end connected to the output terminal, a second diode having an anode connected to the other end of the fourth resistor, and a cathode connected to the low potential side power supply; Is connected to the output terminal, the other end is connected to the node, a fifth resistance element is connected to the node, the sixth resistance element, the anode is connected to the other end of the sixth resistance element A third diode having a cathode connected to the low-potential-side power supply, and a drain connected to a first diode of the second conductivity type.
An eleventh field-effect transistor of the second conductivity type, the gate of which is connected to the source of the third field-effect transistor and the gate of which is connected to the anode of the second diode; A second conductive type twelfth field effect transistor having a gate connected to the node and a second conductive type twelfth field effect transistor having one end connected to the source of the second conductive type eleventh and twelfth field effect transistors. And a constant current source connected to the low-potential-side power supply.