JP2002099260A - Signal line driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high-speed operation without increasing manufacturing costs and power consumption. SOLUTION: The signal line driving circuit is provided with a signal processing part SGP for outputting two video signals varying time sequentially, and a signal distribution part SGS for sequentially distributing the two video signals outputted from the signal processing part SGP to plural signal lines X1-X6 on a two-by-two lines basis. Especially, the signal processing part SGP is arranged to output the two video signals so that they are those of the positive and negative polarities, respectively, and the signal distribution part SGS comprises a polarity selection circuit 15 for selecting the signal line drive polarity and a time division switch circuit 16 which replaces these signals of the positive and negative polarities by each other with respect to the two signal lines based on the polarity selected by this polarity selection circuit 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device in which a plurality of liquid crystal pixels display an image corresponding to a video signal supplied through a plurality of signal lines, and more particularly to a liquid crystal display device in which the polarity of these signal lines is inverted. The present invention relates to a signal line driving circuit that performs split driving.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device is lightweight, thin and consumes low power, and is capable of displaying a clear image at a resolution comparable to or higher than that of a CRT. Widely used as. A typical active matrix type liquid crystal display device includes a liquid crystal display panel for displaying an image and a display control circuit for controlling the operation of the liquid crystal display panel. The liquid crystal display panel includes a plurality of display pixels arranged in a matrix, a plurality of scanning lines arranged along rows of these display pixels, a plurality of signal lines arranged along columns of these display pixels, A plurality of pixel switch elements are provided near the intersection of the line and the scanning line. A display control circuit for supplying a scanning signal to a plurality of scanning lines sequentially for each vertical scanning period; and supplying a video signal to a plurality of signal lines for each horizontal scanning period when the scanning signal is supplied to one scanning line. And a timing control circuit for controlling operation timings of the scanning line driving circuit and the signal line driving circuit. Each pixel switch element is a thin film transistor (T) using a semiconductor thin film such as amorphous silicon or polycrystalline silicon.
FT) or a thin film diode (TFD), and applies the potential of the corresponding signal line to the corresponding display pixel in response to a scanning signal from the corresponding scanning line. A display pixel has a structure in which a liquid crystal layer is sandwiched between a pixel electrode and a counter electrode, and the light transmittance of the liquid crystal layer is set by a signal line potential applied to the pixel electrode with respect to the counter electrode potential. When the above-described pixel switch element is provided in a liquid crystal display panel, a high-quality image with reduced crosstalk between display pixels can be displayed.

In recent years, instead of mounting the above-described scanning line driving circuit and signal line driving circuit as driver IC chips at the ends of a liquid crystal display panel, these driving circuits are constituted by, for example, thin film transistors like pixel switch elements. The development of a drive circuit built-in type liquid crystal display panel integrated with the liquid crystal display panel is under development. This liquid crystal display panel can reduce the manufacturing cost while alleviating the restriction on the effective screen area depending on the area occupied by the external wiring terminal group.
On the other hand, the demand for liquid crystal display devices is shifting to high resolution and high definition in recent years, and it is necessary to arrange more fine pixel electrodes at a high density on a liquid crystal display panel. Increasing the number of pixel electrodes in each row in order to increase the resolution in the horizontal direction requires not only increasing the number of signal lines in proportion thereto, but also completing the driving of all signal lines within the horizontal scanning period. Thus, it is necessary to reduce the driving time of each signal line. In addition, when the number of pixel electrodes in each column is increased to increase the resolution in the vertical direction, it is necessary not only to increase the number of scanning lines in proportion thereto, but also to drive all the scanning lines during the vertical scanning period. The horizontal scanning period needs to be shortened to complete. Since the driving time of each signal line greatly depends on the operating speed of the signal line driving circuit, a portion of the signal line driving circuit that requires high speed is constituted by a driver IC chip, and the rest of the signal line driving circuit is currently used. It has become popular to integrate a part and the entire scanning line driving circuit with a liquid crystal display panel.

However, this configuration has a problem that it becomes difficult to mount a driver IC chip due to the number of external wiring terminals which increases in proportion to the number of signal lines. For this reason, a time division driving technique is used to solve this problem. In this time-division driving technique, for example, all signal lines are divided into a plurality of signal line blocks each composed of three adjacent signal lines, and these three adjacent signal lines are sequentially driven by approximately 1/3 horizontal scanning period. Is done. Specifically, the signal line driving circuit is, for example, as shown in FIG.
A signal distribution unit S formed on the liquid crystal display panel as shown in FIG.
S and a video signal processing unit SP formed as a driver IC chip connected to the signal distribution unit SS. The video signal processing unit SP converts a serial digital video signal into a parallel format corresponding to a plurality of signal line blocks and latches them, and converts these digital video signals into analog video based on a reference voltage for γ correction. Into a plurality of output buffers BF1, BF2,.
Accordingly, these analog video signals are level-converted in a dynamic range from the power supply potential VL of negative polarity to the potential Vcom of the common electrode to the power supply potential VH of positive polarity with respect to the potential of the common electrode Vcom. The signal distribution unit receives a video signal supplied from each of the output buffers BF1,... To the external wiring terminal PD of the liquid crystal display panel, and receives this video signal via the first to third analog switches SW1, SW2, SW3. Three adjacent signal lines X (X1, X2,
X3; ...). These analog switches SW
1, SW2 and SW3 are switch control signals CSW1, CS
Approximately 1 / different from each other under the control of W2 and CSW3.
It conducts in each of three horizontal scanning periods.

[0005]

The above-described signal line driving circuit has an advantage that the number of external wiring terminals can be reduced to about 1/3 of the number of signal lines. However, each output buffer BF
Are configured to invert the polarity of the pixel electrode with respect to the potential of the counter electrode in order to reduce the polarization action of the liquid crystal molecules and prevent the charging of the liquid crystal molecules or the charging of the insulating surface of the electrodes. Are increasing in amplitude. That is, as shown in FIG. 6, each output buffer BF1,... Drives a load obtained by adding the pixel capacitance Clc and the auxiliary capacitance Cs to the signal line capacitance, and changes the pixel potential from the negative potential level Vm to the positive potential level Vm. To the potential level Vs. Therefore, the idle current of the output buffers BF1,. Furthermore, many transistors are required for DA conversion. Therefore,
When such a signal line driving circuit is applied to time-division driving of a large-sized high-definition liquid crystal display panel or multiple-time-division driving of a small-to-medium-sized high-definition liquid crystal display panel, it is necessary to operate the driver IC chip with high precision and at high speed. A simple circuit configuration tends to increase the manufacturing cost and the power consumption, and it is an important design issue to suppress them.

An object of the present invention is to provide a signal line driving circuit which can operate at high speed without increasing the manufacturing cost and the power consumption.

[0007]

According to the present invention, there is provided a signal line drive circuit for driving a plurality of signal lines constituting a signal line block in a liquid crystal display panel in a time-division manner. A signal processing unit that outputs a signal; and a signal distribution unit that sequentially distributes two video signals output from the signal processing unit to a plurality of signal lines two by two. And a signal distribution unit that outputs a positive polarity signal and a negative polarity signal based on the polarity selected by the polarity selection circuit. A signal line driver circuit including a switch circuit for replacing a signal line is provided.

In this signal line drive circuit, the switch circuit exchanges the positive and negative signals for two signal lines based on the polarity selected by the polarity selection circuit. Therefore, even when the polarity of the signal line is periodically inverted, the signal processing unit can transition the potential of the signal line in a short time without requiring a large video signal amplitude. Further, since the output polarity of the signal processing unit does not change, power consumption and manufacturing cost can be reduced.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An active matrix type liquid crystal display according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a circuit configuration of the liquid crystal display device. The liquid crystal display device includes a liquid crystal display panel 1 for displaying an image.
And a display control circuit 2 for controlling the operation of the liquid crystal display panel 1. The liquid crystal display panel 1 has a structure in which the liquid crystal layer LQ is held between the array substrate AR and the counter substrate CT. The array substrate AR includes a plurality of pixel electrodes PE arranged in a matrix and each defining a display pixel of the display screen DS, a plurality of scanning lines Y (Y1 to Ym) formed along a row of the plurality of pixel electrodes PE, A plurality of pixel switch elements W arranged near the intersection of a plurality of signal lines X (X1 to Xn), signal lines X1 to Xn, and scanning lines Y1 to Ym formed along a column of a plurality of pixel electrodes PE are arranged. Have. The counter substrate CT has a single counter electrode C facing a plurality of pixel electrodes PE.
E. The display control circuit 2 includes a scanning line driving circuit 3 for sequentially supplying a scanning signal to the scanning lines Y1 to Ym every vertical scanning period, and a video signal for each horizontal scanning period when the scanning signal is supplied to one scanning line Y. A signal line driving circuit 4 for supplying X1 to Xn, a timing control circuit 5 for controlling operation timings of the scanning line driving circuit 3 and the signal line driving circuit 4 are provided. The signal lines X1 to Xn are divided into a plurality of signal line blocks each including six adjacent signal lines.
For example, two signal lines of each signal line block are sequentially driven every ３ period of the horizontal scanning period. Each pixel switch element W is composed of a thin film transistor (TFT) using a semiconductor thin film such as amorphous silicon or polycrystalline silicon, and responds to a scanning signal from the corresponding scanning line Y to respond to the potential of the corresponding signal line X. Apply to the pixel electrode PE. The display pixel has a structure in which a liquid crystal layer LQ is sandwiched between the pixel electrode PE and the counter electrode CE, and is, for example, DC set to the counter electrode CE.
With respect to the potential Vcom of 5 V, the pixel electrode P is connected via the signal line X.
The light transmittance of the liquid crystal layer LQ is set by the potential applied to E.

The scanning line driving circuit 3 comprises a shift register SR and a level converter LV formed on the array substrate AR by combining a plurality of thin film transistors. The shift register SR is connected to receive the trigger signal YST and the basic clock signal YCK supplied from the timing control circuit 5 to the external wiring terminal PD, and shift the trigger signal YST in response to the basic clock signal YCK. The level converter LV converts the level of the trigger signal YST shifted by the shift register SR and sequentially supplies the trigger signal YST to the scanning lines Y1 to Ym as a scanning signal for turning on the pixel switch W. The shift register SR has m connected in cascade.
The level converter LV includes output terminals of these flip-flops and scanning lines Y1 to Ym.
It is composed of m output buffers connected between them.

The signal line drive circuit 4 includes a signal distribution unit SGS formed on the array substrate AR by combining a plurality of thin film transistors, and a signal distribution unit SGS fixed to an end of the array substrate AR via an external wiring terminal PD. And a signal processing unit SGP formed as at least one driver IC chip connected to the signal processing unit SGP. The signal processing unit SGP outputs two video signals that change in time series for each signal line block, and the signal distribution unit SGS converts the two video signals output from the signal processing unit SGP into six adjacent signals of the signal line block. Distribute two lines at a time.

The signal processing unit SGP includes a timing control circuit 5
-Parallel converter 1 for converting a serial digital video signal VD supplied from the
0, a plurality of flip-flops 11 which respectively latch digital video signals output in parallel from the serial-parallel converter 10 in response to a latch signal LT supplied from the timing control circuit 5, and output from the flip-flops 11 D / A converters 12 for converting digital video signals into analog video signals based on a reference voltage VR for γ correction, and an output buffer circuit for level-converting the analog video signals output from these DA converters 12, respectively. 13. Here, two adjacent DA converters 12 are assigned to each signal line block, and output two video signals that change in time series. The output buffer circuit 13 includes a positive output buffer 13P for outputting one of these two video signals as a positive signal and a negative output buffer 13N for outputting the other of the two video signals as a negative signal for each signal line block. . Output buffer 13 for all signal line blocks
P has a power supply potential VC (= 5 V) equal to the common potential Vcom set for the common electrode CE and this power supply potential VC.
A higher power supply potential VH (= 10 V) is supplied in a rail-to-rail format. In the output buffers 13P for all signal line blocks, the power supply potential VC (= 5V) and the power supply potential VL lower than the power supply potential VC (H == 0V) are Rail-t.
Supplied in o-Rail format. Each output buffer 13P operates at a voltage between the power supply potential VC (= 5V) and the power supply potential VH (= 10V), and converts the level of the video signal in a dynamic range from 5V to 10V. Output buffer 13N
Are the power supply potential VC (= 5 V) and the power supply potential VL (= 0
V), and performs level conversion of the video signal in a dynamic range from 0V to 5V.

The signal distribution unit SGS includes a polarity selection circuit 15 for selecting a signal line drive polarity, and a positive output buffer 13P and a negative output buffer 1 for each signal line block.
A positive / negative signal output from the 3N is switched based on the polarity selected by the polarity selection circuit 15 and a time division switch circuit 16 is applied to two signal lines.

The time division switch circuit 16 includes a P-channel transistor AWP and an N-channel transistor AW
N to the first to sixth analog switch units A
W is provided for each signal line block. The signal line X of each signal line block is connected to the corresponding positive output buffer 13P via six P-channel transistors AWP and to the corresponding negative output buffer 13N via six N-channel transistors AWN. .

The polarity selection circuit 15 outputs 1/1 of one horizontal scanning period.
The switch control signals CSW1, CSW2, and CSW1, which are set to a high level alternately by a predetermined period Tw slightly shorter than three periods,
And CSW3, and polarity control signals POLU and POL whose levels are complementarily inverted in, for example, one field cycle.
It is connected to the timing control circuit 5 so as to receive U bar, and has first to sixth NAND gates SG for each signal line block. The switch control signal CSW1 is supplied to first input terminals of the first and second NAND gates SG, and the switch control signal CSW2 is supplied to the third and fourth NAND gates S.
G is supplied to the first input terminal of the switch control signal CSW3.
Are supplied to the first input terminals of the fifth and sixth NAND gates SG. The polarity control signal POLU has the first, third, and 5Nth
The polarity control signal POLU is supplied to the second input terminal of the AND gate SG, and the polarity control signal POLU is supplied to the second input terminal of the second, fourth, and sixth NAND gates. The output terminals of the first to sixth NAND gates SG are connected as follows for each signal line block. That is, the output terminal of the first NAND gate SG is connected to the transistor AW of the first analog switch unit AW.
The transistor AW of the second analog switch unit AW is directly connected to the gate of the P
Connected to N gate. The output terminal of the second NAND gate SG is connected to the transistor AW of the second analog switch unit AW.
The transistor AW of the first analog switch unit AW is directly connected to the gate of the P
Connected to N gate. The output terminal of the third NAND gate SG is connected to the transistor AW of the third analog switch unit AW.
The transistor AW of the fourth analog switch unit AW is connected directly to the gate of the P
Connected to N gate. The output terminal of the fourth NAND gate SG is connected to the transistor AW of the fourth analog switch unit AW.
The transistor AW of the third analog switch unit AW is connected directly to the gate of the P
Connected to N gate. The output terminal of the fifth NAND gate SG is connected to the transistor AW of the fifth analog switch unit AW.
The transistor AW of the sixth analog switch unit AW is connected directly to the gate of the P
Connected to N gate. The output terminal of the sixth NAND gate SG is connected to the transistor AW of the sixth analog switch unit AW.
The transistor AW of the fifth analog switch unit AW is directly connected to the gate of the P
Connected to N gate.

Next, the operation of the liquid crystal display device will be described with reference to FIG. Here, focusing on the signal line blocks of the signal lines X1 to X6, the scanning line driving circuit 3 supplies the signal to the scanning line Y1, for example, in one horizontal scanning period corresponding to the basic clock signal YCK, and the polarity control signal POLU is high during this period. Let it be a level. Polarity control signal POLU
Continuously selects the first, third, and fifth NAND gates SG during this horizontal scanning period. After the start of the horizontal scanning period, the switch control signals CSW1, CSW2, and CSW3 sequentially become high for each period Tw. When the switch control signal CSW1 rises, the first NAND gate SG is enabled, and the first analog switch unit AW
And the transistor AWN of the second analog switch section are turned on. During this time, the signal line X1
Is driven by a positive video signal output from the positive output buffer 13P, for example, a negative potential level Vm
To the positive potential level Vs. On the other hand, the signal line X2 is driven by the negative video signal output from the negative output buffer 13N, and transitions, for example, from the positive potential level Vs to the negative potential level Vm. continue,
When the switch control signal CSW2 rises, the third NAND
The gate SG is enabled, and the transistor AWP of the third analog switch unit AW and the transistor AWN of the fourth analog switch unit are turned on. During this time, the signal line X3 is driven by the positive video signal output from the positive output buffer 13P, and the signal line X4 is driven by the negative video signal output from the negative output buffer 13N. Subsequently, when the switch control signal CSW3 rises, the fifth NAND gate SG is enabled, and the fifth NAND gate SG is enabled.
The transistor AWP of the analog switch unit AW and the transistor AWN of the sixth analog switch unit are turned on. During this time, the signal line X5 is driven by the positive video signal output from the positive output buffer 13P, and the signal line X6 is driven by the negative video signal output from the negative output buffer 13N.

Incidentally, the potential of each signal line X is equal to the scanning line Y1.
Is applied to the corresponding pixel electrode PE via the pixel switch element W which is turned on by the scanning signal supplied via
Positive output buffer 13P and negative output buffer 1
3N are the parasitic capacitance of the signal line X, the liquid crystal capacitance Clc between the pixel electrode PE and the counter electrode CE, and the pixel electrode PE.
The auxiliary capacitance Cs of the auxiliary capacitance line capacitively coupled to the capacitor Cs is charged and discharged. The potential of the pixel electrode PE is the liquid crystal capacitance Clc in one frame period after the pixel switch element W is turned off and before the pixel switch element W is turned on again.
And the auxiliary capacitance Cs.

Here, the NAND gate SG of the signal distribution unit SGS, the inverter R, the transistors AWP and AW
A supplementary explanation of a plurality of thin film transistors that are combined to form N is given. Each thin film transistor is formed on the array substrate AR in the same manufacturing process as the pixel switch element W and the thin film transistor of the scanning line drive circuit 2,
For example, it is formed using a semiconductor thin film of polysilicon.
In this case, the thin film transistor may have either a bottom gate structure shown in FIG. 3 or a top gate structure shown in FIG. FIGS. 3 and 4 each show a configuration example in which the polysilicon thin film transistor is an N-channel type.

In the bottom gate structure shown in FIG. 3, a thin film transistor has a gate electrode 32 formed on a glass substrate 31, a gate insulating film 33 covering the gate electrode 32, and a thin film transistor on the gate insulating film 33 so as to overlap the gate electrode 32. And a polysilicon semiconductor layer 34 covered with an insulating film 35. The polysilicon semiconductor layer 34 has a source region 36 of an N ⁺ diffusion layer disposed on both sides of the gate electrode 32.
And a drain region 37, and a source electrode 38 and a drain electrode 39 are formed on the source region 36 and the drain region 37.

In the top gate structure shown in FIG. 4, a thin film transistor is formed on a glass substrate 31 by a polysilicon semiconductor layer 34, a gate insulating film 33 formed on the polysilicon semiconductor layer 34, Has a gate electrode 32 covered with an insulating film 35 formed on the substrate. The polysilicon semiconductor layer 34 has a source region 36 and a drain region 37 of N ⁺ diffusion layers disposed on both sides of the gate electrode 32, and the source electrode 38 and the drain electrode 39 are formed by the source region 36 and the drain region 3.
7 is formed.

In the liquid crystal display device of the present embodiment, the time division switch circuit 16 exchanges the positive and negative signals for the two signal lines X based on the polarity selected by the polarity selection circuit 15. For this reason, even when the polarity of the signal line X is periodically inverted, each of the output buffers 13P and 13N of the signal processing unit SGP requires only half the signal amplitude of the conventional video signal. Transition can be made in a short time. In such a case, as the rise time (settling time) of the output buffers 13P and 13N is shortened, the number of time divisions in the horizontal scanning period can be increased to reduce the number of driver IC chips. Furthermore, since the output polarities of the output buffers 13P and 13N do not change, the withstand voltage of the driver IC chip can be set low, thereby reducing power consumption and manufacturing cost. Incidentally, the output buffer circuit 13 is connected to the power supply potentials VL and VH in addition to the power supply potential VC.
, Which has little effect on the manufacturing cost of the driver IC chip.

UXGA (ultra XGA) in the future
When a display method with an enormous number of pixels such as QXGGA (Quad XGA) is adopted, it is necessary to drive a signal line corresponding to a video signal in a shorter time.
Since the above-described driver IC chip output can be settled at high speed, it is possible to easily cope with the reduction of the signal line driving time.

For the above reasons, it is possible to reduce the module size of the entire liquid crystal display device while maintaining good image quality, and to realize color display requiring a large number of pixels at low cost.

The present invention is not limited to the configuration of the above-described embodiment, and can be variously modified without departing from the gist thereof.

In the above-described embodiment, each signal line block is constituted by six adjacent signal lines, and two signal lines are divided into three and time-divisionally driven. However, it is possible to set the adjacent signal lines of each signal line block to 2k (k: a positive integer) and to perform the time-division driving by dividing each of the signal lines into k times.

The present invention can be easily applied to a normally black liquid crystal display panel. Further, the pixel switch element W may be replaced with an active element other than the thin film transistor.
The liquid crystal display panel may be of a display system without the pixel switch element W. Further, the characteristics of the liquid crystal material and the power supply output potential are not particularly limited.

The output buffer circuit 13 operates with three power supply potentials VL, VC and VH, but has four power supply potentials, for example, a positive low potential VPL (= 6 V) and a positive high potential VP.
H (= 10 V), a low potential VNL for negative polarity (= 4 V), and a high potential VNH (= 0 V) for negative polarity are prepared, and the output buffer 13P is operated with a voltage between the potential VPL and the potential VPH. With the potential VNL and the potential V
The operation may be performed with a voltage between NH. In this case, the withstand voltage of the output buffers 13P and 13N can be further reduced.

Although the signal processing circuit SGP employs a digital latch system in which a serial-parallel converter 10 and a plurality of flip-flops 11 are combined, an analog latch system in which a shift register and an analog sample-and-hold element are combined is used. You may change it. In this case, the DA converter 12 becomes unnecessary. However, with such a configuration, it is relatively difficult to balance the reduction in manufacturing cost and power consumption of the signal line drive circuit with the increase in operating speed.

[0030]

As described above, according to the present invention, it is possible to provide a signal line driving circuit which can operate at high speed without increasing the manufacturing cost and the power consumption.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an active matrix liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the liquid crystal display device shown in FIG.

FIG. 3 is a cross-sectional view showing a bottom gate structure of a polysilicon thin film transistor applied to the signal distribution unit shown in FIG.

FIG. 4 is a cross-sectional view showing a top gate structure of a polysilicon thin film transistor applied to the signal distribution unit shown in FIG.

FIG. 5 is a circuit diagram showing a configuration example of a conventional signal line driving circuit.

FIG. 6 is a time chart for explaining an operation of the signal line driving circuit shown in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display panel 4 ... Signal line drive circuit 15 ... Polarity selection circuit 16 ... Switch circuit X ... Signal line SGP ... Signal processing part SGS ... Signal distribution part

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 3/20 623 G09G 3/20 623X F term (Reference) 2H093 NA16 NA31 NA34 NA41 NC11 NC22 NC34 NC49 NC52 ND15 ND39 ND54 5C006 BB16 BB17 BC13 BC20 BF24 FA11 FA46 5C080 AA10 BB05 DD07 DD08 DD26 DD27 FF11 JJ02 JJ04 JJ06

Claims (6)

[Claims] 1. A signal line driving circuit for time-divisionally driving a plurality of signal lines constituting a signal line block in a liquid crystal display panel, the signal processing unit outputting two video signals changing in time series, A signal distribution unit that sequentially distributes two video signals output from the signal processing unit to the plurality of signal lines two by two, and the signal processing unit outputs the two video signals as a positive polarity signal and a negative polarity signal, respectively. The signal distribution unit is configured to select the signal line driving polarity, and to output the positive and negative signals to the two signal lines based on the polarity selected by the polarity selection circuit. A signal line driver circuit including a switch circuit for switching. 2. The signal line driving circuit according to claim 1, wherein the signal processing unit is formed as a driver IC chip disposed outside the liquid crystal display panel. 3. The signal line driving circuit according to claim 1, wherein the two signal lines are adjacent to each other as odd and even numbers in the liquid crystal display panel. 4. The signal processing unit includes a positive output buffer for level-converting one of the two video signals as a positive signal and a negative output buffer for level-converting the other of the two video signals as a negative signal. The signal line drive circuit according to claim 1, wherein: 5. The positive output buffer and the negative output buffer are wired so as to operate at a voltage between the first and second power supply potentials and a voltage between the third and fourth power supply potentials, respectively. The signal line driving circuit according to claim 4. 6. The positive output buffer and the negative output buffer are wired to operate at a voltage between first and second power supply potentials and a voltage between second and third power supply potentials, respectively. The signal line driving circuit according to claim 4.