JP2002094872A - Electronic still camera - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem where a long time is necessary for signal processing when the number of picture elements is increased, and the operation of an electronic still camera becomes slow. SOLUTION: A video signal input output control part 5 which is connected with an internal memory 6 is provided with a plurality of buffers (5a-5f) constituted of capacity equivalent to 256 words. When data are delivered to the internal memory 6, the buffers operate at 90 MHz. When data are delivered to constitution for signal processing, the buffers operate at 180 MHz. Thereby the plurality of buffers are used simultaneously and a plurality of data processings are enabled in parallel, so that data processing time can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic still camera for recording a still image picked up by a solid-state image sensor on a recording medium such as a semiconductor memory.

[0002]

2. Description of the Related Art The spread of personal computers to ordinary households has been remarkable, and accordingly, electronic still cameras have been spreading. This electronic still camera performs a data compression coding process on a still image captured using a solid-state imaging device to reduce the amount of data, and compresses the still image into a semiconductor recording medium such as a solid state floppy disk card (SSFDC). The recorded still image can be displayed on a monitor of a personal computer or printed by a home printer. The number of pixels of a still image that can be imaged by the electronic still camera is increasing year by year, assuming printing by a printer.

[0003]

However, such an increase in the number of pixels imposes a heavy burden on the internal signal processing circuit. In other words, if the number of pixels increases, a longer time is required for signal processing, so that the interval between capturing still images becomes longer, and the interval from when a still image is captured to when the next operation is performed becomes longer. Problem had arisen.

In general, an electronic still camera is provided with a line buffer for signal processing, and stores and processes data for each line. However, when the number of pixels is increased, the number of pixels per line is also reduced. To increase. Therefore, it is necessary to mount a larger line buffer, which has led to an increase in circuit scale.

[0005] Recently, there has been a type capable of outputting a still image not only to a monitor of a personal computer but also to a television receiver. However, when outputting a still image to a television receiver, the number of pixels is greatly reduced. Since the output is reduced, there is a problem that the image cannot be displayed with the original image quality of the still image.

[0006] In view of these problems, an electronic still camera according to the present invention aims to speed up a signal processing circuit without using a large-capacity line buffer.
It is an object of the present invention to output a still image to a television receiver while maintaining the image quality of the still image.

[0007]

In order to solve the above problems, an electronic still camera according to the present invention converts an incoming subject light into an electric signal in the form of an analog signal and outputs it. ) And an A / D which converts an electric signal output from the image pickup device (1) into a digital signal and outputs the digital signal.
A conversion unit (3) and a memory (6) that operates with a first clock having a predetermined frequency and temporarily holds a digital signal output from the A / D conversion unit (3) with the first clock; ) And a second clock having a frequency equal to or less than half the frequency of the first clock, and the memory (6)
A signal processing unit (4, 7) for performing predetermined signal processing on the digital signal read out from the second clock with the second clock, and outputting the processed digital signal for writing in the memory; And an input / output control unit (5) for changing the data rate of the digital signal when writing the digital signal to the memory (6) or reading the digital signal from the memory (6). The input / output control unit (5) includes a plurality of buffers (5a to 5f) each having a capacity smaller than a data amount of data for one horizontal line in the image sensor (1). When transferring data to and from the memory (1), the buffer (5a to 5f) is operated by the first clock while the signal processing unit (4) is operated. When the transfer of data to and from the 7) is characterized in that operating the buffer (5a to 5f) in the second clock.

[0008] The input / output control unit (5) of the electronic still camera according to the present invention includes a plurality of buffers (5a to 5f).
And an HD output buffer (5d) for outputting a high-definition video signal, and when writing data from the memory (6) to the HD output buffer (5d), The HD output buffer (5d) is operated by one clock while the HD output buffer (5d) is operated.
When data is read from d), the HD signal is read by a third clock corresponding to the data rate of the high-definition video signal.
The output buffer (5d) is operated.

[0009]

FIG. 1 is a block diagram for explaining an electronic still camera according to an embodiment of the present invention.
Denotes a solid-state imaging device (CCD) that converts incoming subject light into an electric signal and outputs the signal, and 2 outputs a signal output from the solid-state imaging device 1 after performing processing such as correlated double sampling and automatic gain adjustment. The analog signal processing unit 3 is an A / D conversion unit that converts an analog signal output from the analog signal processing unit 2 into a digital signal and outputs the digital signal.

Reference numeral 4 denotes a digital signal processing unit for performing various signal processing on the digital signal output from the A / D conversion unit 3 or the digital signal from the video signal input / output control unit 5 as described later. A video signal input / output control unit for changing a digital signal data rate when writing or reading a digital signal to or from the internal memory 6 as described later;
Reference numeral 6 denotes an internal memory which is connected to the video signal input / output control unit 5 and temporarily stores a digital signal from the video signal input / output control unit 5, and 7 is connected to the video signal input / output control unit 5 and controls the video signal input / output. JPEG for digital signal from unit 5
(Joint Photographic Coding Experts Group) A JPEG processing unit that performs compression / decompression processing.

Reference numeral 8 denotes a CCD drive control unit for driving the solid-state imaging device 1; 9 is connected to the video signal input / output control unit 5;
In addition to controlling the operation of the CD drive control unit 8, the digital signal from the video signal input / output control unit 5 is transmitted to an external recording medium 10.
Is a control unit for inputting and outputting data to and from the computer. In addition, as the external recording medium 10, a removable recording medium such as the above-mentioned SSFDC can be used. Reference numeral 11 denotes a D / A converter that converts a digital signal from the video signal input / output controller 5 into an analog signal and outputs the analog signal to an internal monitor or an external monitor (not shown).

The A / D conversion unit 3, digital signal processing unit 4, and control unit 9 are supplied with a clock of 18 MHz, and perform A / D conversion processing in the A / D conversion unit 3, digital The digital signal processing in the signal processing unit 4 and the control in the control unit 9 are all operated by a clock of 18 MHz. In addition, the JPEG processing unit 7 includes 45
MHz clock is supplied and the JPEG processing unit 7
The compression and decompression processing in the above is operated with a clock of 45 MHz.

Hereinafter, the operation of the electronic still camera according to the embodiment of the present invention will be described. First, an analog signal output from the solid-state imaging device 1 based on a drive signal generated by the CCD drive control unit 8 is processed by the analog signal processing unit 2 and supplied to the A / D conversion unit 3. The analog video signal output from the analog signal processing unit 2 is an analog signal having an RGB signal form, and the A / D conversion unit 3 converts the analog signal into a digital signal. The signal converted into the digital signal is temporarily stored in the internal memory 6 via the video signal input / output control unit 5.

When a digital signal for one screen is stored in the internal memory 6, reading of the digital signal having the RGB signal form is started. The read digital signal is output to the digital signal processing unit 4 via the video signal input / output control unit 5, and the digital signal processing unit 4
A digital signal having a GB signal form is converted into a digital signal having a luminance and color difference signal form. Then, the converted digital signal is written into the internal memory 6 again via the video signal input / output control unit 5.

The solid-state image sensor 1 outputs a still image of 2048 × 1536 pixels in the horizontal and vertical directions. If it is necessary to reduce the image size to a smaller image, the solid-state imaging device 1 performs this reduction processing digitally. This is performed by the signal processing unit 4. Therefore, in such a case, a still image is read from the internal memory 6 again, and this still image is output to the digital signal processing unit 4 via the video signal input / output control unit 5. Then, the still image that has been reduced by the digital signal processing unit 4 is written to the internal memory 6 via the video signal input / output control unit 5.

When a captured still image is to be displayed on an internal monitor (not shown), a still image having a size suitable for display on the internal monitor is generated by the digital signal processing unit 4 through a reduction process. The reduced still image is written in the internal memory 6 and further displayed on the internal monitor via the video signal input / output control unit 5 and the D / A conversion unit 11. Similarly, when a captured still image is output to an external monitor as a standard definition television signal such as NTSC or PAL, a still image having a size corresponding to the television signal is generated and written to the internal memory 6. It is.

The still image of 2048 × 1536 pixels in the horizontal and vertical directions stored in the internal memory 6 or the still image which has been subjected to reduction processing as required is input to a video signal input terminal in order to reduce the data amount. J via output control unit 5
The data is output to the PEG processing unit 7 and subjected to JPEG compression processing. When the compression processing is completed, the still image is written into the internal memory 6 again via the video signal input / output control unit 5. After that, the still image after the JPEG compression processing is read out by the video signal input / output control unit 5 and recorded on the external recording medium 10 via the control unit 9 by DMA (Direct Memory Access) transfer.

When a still image recorded in the external recording medium 10 is displayed on the internal monitor or the external monitor, when the still image compressed by the JPEG system is read from the external recording medium 10, the control unit 9 The data is written to the internal memory 6 via the video signal input / output control unit 5. Then J
This still image is output via the video signal input / output control unit 5 for the PEG expansion process.

When the decompression processing in the JPEG processing unit 7 is completed, the data is written into the internal memory 6 again via the video signal input / output control unit 5, and thereafter, as described above, the digital signal processing unit 4 performs the reduction processing. A still image of a size suitable for display on the internal monitor or a still image of a size corresponding to a standard definition television signal is generated. The still image reduced in this way is output from the D / A conversion unit 11 via the video signal input / output control unit 5.

As described above, in the electronic still camera shown in FIG. 1, the data is once written in the internal memory 6 each time one process is completed. This is performed via the output control unit 5. When a still image captured by the solid-state imaging device 1 is displayed on an internal monitor without being recorded on the external recording medium 10, a signal output from the solid-state imaging device 1 after being decimated line by line is A / A. The signal is supplied from the D conversion unit 3 to the digital signal processing unit 4. Then, the still image, which is thinned out in the horizontal direction in the digital signal processing unit 4 and reduced to a size suitable for display on the internal monitor, passes through the video signal input / output control unit 5 and the D / A conversion unit 11, Output to the internal monitor.

Next, the configuration of the video signal input / output control unit 5 will be described with reference to FIGS. As shown in FIG. 2, the video signal input / output control unit 5 includes an internal memory write buffer 5.
a, internal memory read buffers 5b and 5c, HD read buffer 5d, control unit buffer 5e, JPEG processing buffer 5f, and internal memory input / output control unit 5g.

Here, the buffers 5a to 5d are shown in FIG.
As shown in the figure, the buffers 5h and 5i and the switch SW1
And SW2, the switch SW1 and the switch SW2 are operated so that when writing is performed in one buffer, reading is performed from the other buffer.

The buffers 5e and 5f have the same configuration as the buffers 5a to 5d shown in FIG. 3, but are provided with additional changeover switches so that data can be transferred bidirectionally. That is, although FIG. 3 shows that data is output from the switch SW1 to the switch SW2, the control unit buffers 5e and J in FIG.
Only in the PEG processing buffer 5f, data can be transferred bidirectionally, and for this purpose, a changeover switch (not shown) is additionally provided. Buffer 5
Each of h and 5i has a capacity enough to hold data for 256 words (256 pixels in a digital signal having a signal form of luminance and color difference). Therefore, in order to output data for one line in the horizontal direction (for 2048 pixels), writing and reading operations are performed eight times.

Here, the internal memory input / output control unit 5g is connected to the internal memory 6, and the internal memory write buffer 5a,
Control unit buffer 5e or JPEG processing buffer 5f
From the internal memory 6 and the data from the internal memory 6 to the internal memory read buffer 5.
b, an internal memory read buffer 5c, an HD read buffer 5d, a control unit buffer 5e, and a JPEG processing buffer 5f.

The internal memory write buffer 5a has A
The digital signal from the / D converter 3 or the digital signal processor 4 is written, and the internal memory read buffer 5b
The data read from the HD read buffer 5d is output to the digital signal processing unit 4 or the D / A conversion unit 11, and the data read from the HD read buffer 5d is output to the D / A conversion unit 1.
1 is output. Although only one D / A converter 11 is shown in FIG. 1, a plurality of D / A converters may be used to convert digital signals of various data rates into analog signals. Needless to say.

The control unit buffer 5e is bidirectionally connected to the control unit 9, and the JPEG processing buffer 5f is
Since it is bidirectionally connected to the EG processing unit 7, the control unit buffer 5e and the JPEG processing buffer 5f can exchange data with these components.

When the video signal input / output control unit 5 exchanges data with the internal memory 6, the video signal input / output control unit 5 operates at 90 MHz.
Data is transferred with the clock of the clock, and when the data is transferred with the other configuration, 18 MHz is used.
Data is transferred with a clock of z, 45 MHz or 72.25 MHz. Therefore, the internal memory 6 can perform input / output of a plurality of data in parallel in a time-division manner.

To this end, each of the buffers 5a to 5 shown in FIG.
f, when the data written in the buffer is read out to the internal memory input / output control unit 5g side, or when the data from the internal memory input / output control unit 5g side is written to the buffer, the data is clocked at 90 MHz. Reading or writing is performed.

On the other hand, from the outside of the video signal input / output control unit 5, an internal memory writing buffer 5a, a control unit buffer 5e, J
When writing data to the PEG processing buffer 5f, or when reading data from the internal memory read buffer 5b, the internal memory read buffer 5c, and the control unit buffer 5e to the outside of the video signal input / output control unit 5, 18 MHz
The reading or writing of data is performed by the clock of. When data is read from the JPEG processing buffer 5f to the JPEG processing unit 7, data is read at a clock of 45 MHz. When data is read from the HD reading buffer 5d to the D / A conversion unit 11, 74 is read. .2
Data reading is performed with a 5 MHz clock.

FIG. 4 is a diagram for explaining the parallel processing of a plurality of data in the internal memory 6. In FIG.
(A) is a horizontal synchronization signal in an NTSC television signal, (b) is an operation of writing data to the internal memory writing buffer 5a, and (c) is an operation of reading data from the internal memory writing buffer 5a. , (D) shows the operation of writing data to the internal memory read buffer 5b,
(E) is a data read operation from the internal memory read buffer 5b, (f) is a data write operation to the JPEG process buffer 5f, (g) is a data read operation from the JPEG process buffer 5f, and (h) FIG. 3 is a diagram for explaining an operation in the internal memory 6.

Here, the digital signal having the luminance and chrominance signal forms stored in the internal memory 6 is reduced by the digital signal processor 4 and the digital signal having the luminance and chrominance signal forms is compressed by the JPEG method. For processing, the video signal input / output control unit 5 reads out a still image from the internal memory 6 and outputs the still image to the digital signal processing unit 4 and the JPEG processing unit 7. It is necessary to simultaneously perform the operation of outputting an image to the internal memory 6.

The operation at that time will be described below. First, FIG.
As shown in (d), 25 still images from the internal memory 6 are stored.
The data of 256 words written into the internal memory read buffer 5b at a clock of 90 MHz by six words at a time, and written into the internal memory read buffer 5b is shown in FIG.
As shown in (e), the signal is output to the digital signal processing unit 4 with a clock of 18 MHz.

Further, the still image from the internal memory 6 is written into the JPEG processing buffer 5f at a clock of 90 MHz in 256 words, and the 256-word data written in the JPEG processing buffer 5f is shown in FIG. As shown, it is output to the JPEG processing unit 7 at a clock of 45 MHz.

As described above, the digital signal processing unit 4 and the JP
A still image is output to the EG processing unit 7 in 256 words at a time, but the processing in the digital signal processing unit 4 is sequentially completed before all the still images for one screen are output.
The processed data is written in the internal memory 6 in parallel. That is, as shown in FIG. 4B, the processed data is written to the internal memory write buffer 5a at a clock of 18 MHz, and the data written to the internal memory write buffer 5a is written in FIG. ),
The data is written to the internal memory 6 with a clock of 90 MHz.

Then, in the internal memory 6, FIG.
As shown in the figure, processing for the internal memory writing buffer 5a, processing for the internal memory reading buffer 5b,
Since the twist for the JPEG processing buffer 5f is performed in a time-division manner, all of these processes can be performed in parallel.

As shown in FIGS. 4 (b), 4 (e) and 4 (g), data is written to the internal memory write buffer 5a, data is read from the internal memory read buffer 5b, and JPEG processing is performed. While reading data from the buffer 5f for reading is performed with a clock of 18 MHz or 45 MHz, respectively, the data reading from the buffer 5a for writing into the internal memory is performed as shown in FIGS. , The writing of data to the internal memory reading buffer 5b, and the writing of data to the JPEG processing buffer 5f are each performed with a clock of 90 MHz.

Therefore, the calculation shows that 90 MHz / 18 MHz
= 5, and five processes can be performed in parallel. However, the SDRAM (Synchronous Dynamic
When a random access memory (Random Access Memory) is used, a refresh operation or the like is required, so that up to four processes can be actually performed in parallel. In the example shown here, the operating frequency of the internal memory 6 is set to 90 MHz.
Needless to say, if the frequency is set to 36 MHz or more, which is twice the frequency of MHz, a plurality of processes can be performed in parallel.

In the electronic still camera shown in FIG.
A configuration may be adopted in which a plurality of still images are stored in the internal memory 6 and these still images can be combined. In order to combine a plurality of still images into one still image in this manner, for example, a plurality of still images output by the video signal input / output control unit 5 can be simultaneously input, and the combined still image is input to the video signal. What is necessary is just to provide a video synthesizing unit that can return to the output control unit 5.

To combine a plurality of still images into one still image in this manner, the internal memory 6 is read from the internal memory 6 using the internal memory read buffer 5b and the internal memory read buffer 5c shown in FIG. It is sufficient to read out two still images and write the synthesized still image into the internal memory 6 using the internal memory writing buffer 5a. By using this function, for example, a still image in which a picture of a frame is combined with a still image is generated, a still image in which a person is combined with a background image is generated, and collage, chroma key, Processing such as luminance key becomes possible.

Next, the operation of outputting a still image stored in the internal memory 6 to an external monitor (not shown) will be described with reference to FIG. In the figure, (a) is a horizontal synchronization signal in an NTSC television signal, (b) is a data write operation to an internal memory read buffer 5b,
(C) A data read operation from the internal memory read buffer 5b, (d) is a horizontal synchronizing signal in the HDTV signal, (e) is a data write operation to the HD read buffer 5d, and (f) is an HD read buffer. FIG. 11 is a diagram for explaining an operation of reading data from 5d.

First, the operation of outputting an NTSC television signal to an external monitor will be described.
As shown in FIG. 5B, a still image of a size corresponding to the NTSC television signal stored in
The data of 256 words written into the internal memory read buffer 5b at a clock of 90 MHz by 56 words at a time is written in FIG.
As shown in (c), the signal is output to the D / A converter 11 with a clock of 18 MHz.

Here, a still image having a size corresponding to an NTSC television signal is a still image having 640 pixels in the horizontal direction and 480 pixels in the vertical direction. Needs to write data to the internal memory read buffer 5b three times. By repeating this for 480 lines, a still image for one screen can be obtained.

On the other hand, when a high-vision television signal is output to an external monitor, the still images stored in the internal memory 6 before the reduction processing are performed, as shown in FIG. The data is written into the HD read buffer 5d with a clock of 90 MHz, and the HD read buffer 5d is written.
The data of 256 words written in d is as shown in FIG.
As shown in the figure, the data is read out with a clock of 72.45 MHz.

Here, the still images, which have not been subjected to the reduction processing, are stored in the internal memory 6 in the horizontal direction.
Since it is a still image having 8 pixels and 1536 pixels in the vertical direction, it is necessary to write data to the internal memory read buffer 5b eight times to obtain one line of data.
Then, 108 of the 1536 lines near the center of the screen
By selecting and outputting two lines, a high-definition signal can be output.

[0045]

According to the first aspect of the present invention, when the input / output control unit exchanges data with the memory,
When the buffer is operated by the first clock and data is transferred to and from the signal processing unit, the buffer is operated by the second clock having a frequency equal to or less than half of the first clock. High-speed processing of data using a plurality of buffers in parallel can be performed. Further, since the capacity of the buffer is smaller than the data amount of data for one horizontal line in the image sensor, the circuit scale can be reduced.

According to the second aspect of the present invention, since the input / output control unit includes the HD output buffer and can output the high-definition video signal, the image which the still image originally has in the television receiver is also provided. There is an effect that an image can be displayed while maintaining the quality.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an electronic still camera according to the present invention.

FIG. 2 is a diagram showing a configuration of a video signal input / output control unit 5;

FIG. 3 is a diagram showing an internal configuration of each buffer.

FIG. 4 is a diagram for explaining parallel processing of a plurality of data;

FIG. 5 is a diagram for describing output of a still image to an external monitor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device (CCD) 2 ... Analog signal processing part 3 ... A / D conversion part 4 ... Digital signal processing part 5 ... Video signal input / output control parts 5a to 5f ... Buffer 5g ... Internal memory input / output control part 6 ... Internal memory 7 JPEG processing unit 8 CCD drive control unit 9 Control unit 10 External recording medium 11 D / A conversion unit

Continued on front page F term (reference) 2H054 AA01 5C022 AA13 AC00 AC69 5C052 AA17 GA02 GA07 GB05 GB06 GC05 GD02 GD03 GD09 GE06 5C053 FA08 FA17 FA27 GA08 GA10 GB17 GB36 HA25 HA33 KA04 KA18

Claims (2)

[Claims] 1. An imaging device that converts an incoming subject light into an electric signal in the form of an analog signal and outputs the same, and an A / D converter that converts an electric signal output from the imaging device into a digital signal and outputs the digital signal. Operating with a first clock having a predetermined frequency;
A memory for temporarily holding a digital signal output from the / D conversion unit at the first clock, and a second memory having a frequency equal to or less than half of the first clock.
A signal processing unit that operates on the clock of the second clock, performs predetermined signal processing on the digital signal read from the memory with the second clock, and outputs the processed digital signal for writing in the memory; An electronic still camera connected to the memory, comprising: an input / output control unit that changes a data rate of the digital signal when writing a digital signal to the memory or reading a digital signal from the memory; The output control unit includes a plurality of buffers each having a capacity smaller than a data amount of data for one horizontal line in the image sensor. When the buffer is operated and data is transferred to and from the signal processing unit, the second clock is used. Electronic still camera, characterized in that for operating the buffer. 2. The input / output control unit, as one of a plurality of buffers, an HD for outputting a high-definition video signal.
An output buffer for storing data from the memory in the H
When writing to the D output buffer, the HD output buffer is operated with the first clock, and when reading data from the HD output buffer, the third output is adjusted to the data rate of the high definition video signal. 2. The electronic still camera according to claim 1, wherein the HD output buffer is operated by the clock of (1).