JP2002094078A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the OFF-current of a TFT. SOLUTION: This semiconductor device is provided with a shielding film, lower layer capacitance wiring and lower layer wiring formed on an insulation surface, a planarized insulation film formed on the insulation surface covering the shielding film, the lower layer capacitance wiring and the lower-layer wiring, a thin-film transistor provided with an active layer, formed in contact with the planarized insulation film and capacitance wiring formed in contact with the planarized insulation film. The active layer is provided with a channel- forming region, the shielding film is overlapped with the entire channel-forming region holding the planarized insulation film in-between, and the lower layer capacitance wiring is overlapped with the capacitance wiring, holding the planarized insulation film in-between. A gate electrode provided in the thin-film transistor is electrically connected with the lower layer wiring, and the planarized insulation film is polished by a CMP method before the active layer is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device using a semiconductor element (an element using a semiconductor film), and more particularly to a liquid crystal display. The present invention also relates to an electronic device using a liquid crystal display for a display unit.

[0002]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor film (having a thickness of several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and semiconductor devices, and are particularly rapidly developed as switching elements for liquid crystal displays.

An active matrix type liquid crystal display has a TFT (pixel TFT) and a liquid crystal cell in each of a plurality of pixels included in a pixel portion. The liquid crystal cell is
The pixel has a pixel electrode, a counter electrode, and a liquid crystal provided between the pixel electrode and the counter electrode. By controlling the voltage applied to the pixel electrode by the pixel TFT, an image is displayed on the pixel portion.

Since a TFT (crystalline TFT) using a semiconductor film having a crystalline structure for an active layer can provide high mobility, a liquid crystal display that integrates functional circuits on the same substrate to display a high-definition image is provided. Can be realized.

[0005] In this specification, the semiconductor film having a crystal structure includes a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor.
JP-A-8-78329, JP-A-10-78329
JP-A-135468 or JP-A-10-135469
And the semiconductor disclosed in Japanese Patent Publication No.

In order to construct an active matrix type liquid crystal display, 1 to 2 million crystalline TFTs are required even in the pixel portion alone, and more functional TFTs provided on the periphery require more crystalline TFTs. Met. The specifications required for liquid crystal displays are strict, and in order to stably display images, individual crystalline T
It was necessary to ensure the reliability of the FT.

The characteristics of a TFT can be considered in two states, an on state and an off state. From the characteristics in the ON state, characteristics such as ON current, mobility, S value, and threshold value can be known. In the characteristics in the OFF state, emphasis is placed on OFF current.

[0008]

A liquid crystal display using the thin film transistor (TFT) is frequently used as a light valve of a liquid crystal projector or the like.

[0009] The projection light used in the projector generally has an intensity of about one million lux. Most of the projected light is applied to the pixel electrode, but a part of the projected light is incident on the active layer of the TFT provided on the active matrix substrate. In particular, when the projection light enters the channel formation region of the active layer, a photocurrent is generated in this region by the photoelectric effect, and the off-state current of the TFT increases.

Therefore, it is indispensable to dispose a shielding film (black matrix) having a light shielding property so that light from the outside does not enter the active layer of the TFT. In general, the shielding film may be provided on an opposing substrate or provided on an active matrix substrate.

However, when a shielding film is provided on the counter substrate,
With the current bonding technique, when a shielding film is provided on the counter substrate side, the alignment margin is too large, and it is not possible to suppress a decrease in aperture ratio. For this reason, it is suggested that there is a possibility that the semiconductor device will not be able to cope with the miniaturization of the semiconductor element which will be advanced in future.

On the other hand, when a shielding film is provided on an active matrix substrate, the shielding film is generally formed above a transistor or wiring that does not need to transmit visible light via an interlayer insulating film. With the above configuration, it is possible to suppress the alignment margin when forming the shielding film,
The aperture ratio can be improved.

However, the reflected light from the surface of the active matrix substrate when the projection light passes through the liquid crystal display, and the light that has passed through another liquid crystal display when a plurality of liquid crystal displays are used for color display. May enter the active layer of the TFT from the active matrix substrate side. In this case, it is difficult to suppress the off-state current of the TFT with the above-described shielding film.

In view of the above, the present invention provides a semiconductor device having a shielding film that suppresses an increase in the off-state current of a TFT due to the incidence of light from the active matrix substrate side.

[0015]

SUMMARY OF THE INVENTION The present inventors have proposed an active matrix substrate and a TFT in order to prevent light from the active matrix substrate from being incident on the active layer of the TFT.
The formation of a shielding film between the active layer and the active layer was considered. Then, it was considered that the shielding film was covered with an insulating film and an active layer of the TFT was formed on the insulating film.

However, if there is unevenness on the surface of the insulating film due to the effect of the shielding film, the active layer of the TFT is distorted due to the unevenness, and the characteristics of the TFT formed on the insulating film are deteriorated. Specifically, mobility will increase.

If the thickness of the insulating film is increased, the surface of the insulating film can be made flatter. However, it takes time to form an insulating film having a large film thickness. It is difficult to reduce the overall time. Further, as the film thickness is increased, the risk of the substrate being warped by the stress of the insulating film or the insulating film itself being separated from the substrate is increased.

Therefore, the present inventors formed a shielding film on an active matrix substrate, formed an insulating film so as to cover the shielding film, and then performed a CMP (Chemical-Mechanical Political) method.
shing), that is, polishing the insulating film using a so-called chemical / mechanical polishing method.

The CMP method is based on the surface of the object to be polished,
Following this, it is a method of chemically or mechanically planarizing the surface. Generally, a platen (Platen or Polishing Plat
e) A polishing cloth or a polishing pad (hereinafter, collectively referred to as a “pad”) is attached on the polishing pad, and the platen and the polishing pad are supplied while supplying a slurry between the polishing target and the pad. In this method, the object is rotated or rocked, and the surface of the object to be polished is polished by a combined action of chemical and mechanical.

With the above structure, the surface of the insulating film can be flattened, and deterioration of the characteristics of the TFT formed on the insulating film can be suppressed. In addition, warping of the substrate due to the stress of the insulating film can be eliminated to some extent by polishing by the CMP method.

Further, the TF from the active matrix substrate side
Since light applied to the T channel formation region can be blocked by the blocking film, it is possible to prevent the off-current of the TFT from increasing due to the light. And since the shielding film is formed on the active matrix substrate side, it is possible to suppress the alignment margin when forming the shielding film,
The aperture ratio can be improved.

Note that, in addition to the structure of the present invention in which a shielding film is provided between the active layer of the TFT and the substrate, the shielding film is formed above the TFT and the wiring via an interlayer insulating film, so that the active layer of the active layer is formed. In particular, it becomes more reliable to prevent light from entering the channel formation region.

When a shielding film is formed between the active matrix substrate and the active layer of the TFT, wiring may be formed simultaneously with the shielding film. When the wiring and the shielding film are formed of the same material, and the wiring is a gate signal line or a source signal line, disturbance (disclination) of an image due to a disorder in orientation of a liquid crystal material between pixels is observed. Can be prevented.

In the present invention, the insulating film formed to cover the shielding film may be an inorganic or organic material. Where C
It is important to use a material that can be polished by the MP method. Note that the insulating film may be two or more layers. The first insulating film is polished by a CMP method, and the second and subsequent insulating films are stacked over the polished first insulating film. May be. Also, after laminating several insulating films, C
Polishing may be performed using the MP method.

The configuration of the present invention will be described below.

According to the present invention, a shielding film formed on an insulating surface, a planarized insulating film formed on the insulating surface to cover the shielding film, and a semiconductor formed in contact with the planarized insulating film Wherein the shielding film overlaps the semiconductor layer with the planarizing insulating film interposed therebetween, and the planarizing insulating film is formed by a CMP method before the semiconductor layer is formed. And a semiconductor device characterized by being polished by the following method.

According to the present invention, a shielding film formed on an insulating surface, a planarized insulating film formed on the insulating surface to cover the shielding film, and an active layer formed in contact with the planarized insulating film. And a thin film transistor including a layer, wherein the active layer has a channel formation region, and the shielding film overlaps the entire channel formation region with the planarization insulating film interposed therebetween. A semiconductor device is provided in which the planarizing insulating film is polished by a CMP method before the formation of the active layer.

According to the present invention, a lower capacitor wiring formed on an insulating surface, a flattening insulating film formed on the insulating surface to cover the lower capacitor wiring, and formed in contact with the flattening insulating film. Wherein the lower layer capacitor wiring overlaps the capacitor wiring with the planarizing insulating film interposed therebetween, and the planarizing insulating film is formed before the capacitor wiring is formed. And a semiconductor device polished by a CMP method.

According to the present invention, a shielding film, a lower capacitance wiring and a lower wiring formed on an insulating surface, and a planarization formed on the insulating surface to cover the shielding film, the lower capacitance wiring and the lower wiring, A semiconductor device having an insulating film, a thin film transistor including an active layer formed in contact with the planarizing insulating film, and a capacitor wiring formed in contact with the planarizing insulating film, wherein the active layer forms a channel. A region, wherein the shielding film overlaps with the entire channel forming region with the planarizing insulating film interposed therebetween, and the lower layer capacitor wiring is connected to the capacitor wiring with the planarizing insulating film interposed therebetween. Overlapping, the gate electrode of the thin film transistor is electrically connected to the lower wiring, and the planarization insulating film is polished by a CMP method before the active layer is formed. The semiconductor device is provided to symptoms.

According to the present invention, a step of forming a shielding film in contact with an insulating surface, a step of covering the shielding film and forming an insulating film on the insulating surface, and polishing the insulating film by a CMP method to planarize the insulating film A method of manufacturing a semiconductor device, comprising: forming a film; and forming a semiconductor layer in contact with the planarizing insulating film, wherein the shielding film includes the semiconductor layer with the planarizing insulating film interposed therebetween. A method for manufacturing a semiconductor device, which overlaps with a layer, is provided.

According to the present invention, a step of forming a shielding film in contact with an insulating surface, a step of forming an insulating film on the insulating surface so as to cover the shielding film, and a step of polishing the insulating film by a CMP method to planarize the insulating film A method for manufacturing a semiconductor device, comprising: forming a film; and forming a plurality of thin film transistors including an active layer in contact with the planarizing insulating film, wherein the active layer has a channel formation region. In addition, a method for manufacturing a semiconductor device is provided in which the shielding film overlaps the entire channel formation region with the planarization insulating film interposed therebetween.

According to the present invention, a step of forming a lower capacitor wiring in contact with an insulating surface, a step of forming an insulating film on the insulating surface covering the lower capacitor wiring, and polishing and flattening the insulating film by a CMP method Forming a nitrided insulating film;
Forming a capacitor wiring in contact with the planarizing insulating film;
A method of manufacturing a semiconductor device, wherein the lower capacitor wiring overlaps the capacitor wiring with the planarization insulating film interposed therebetween.

According to the present invention, a step of forming a shielding film, a lower layer capacitor wiring and a lower layer wiring in contact with an insulating surface, and forming an insulating film on the insulating surface so as to cover the shielding film, the lower layer capacitor wiring and the lower layer wiring And polishing the insulating film by a CMP method to form a planarized insulating film;
A method for manufacturing a semiconductor device having a plurality of steps of forming a capacitor wiring and a thin film transistor including an active layer over the planarization insulating film, wherein the active layer has a channel formation region; The shielding film overlaps with the entire channel formation region with the flattening insulating film interposed therebetween, and the lower capacitor wiring overlaps with the capacitor wiring with the flattening insulating film interposed therebetween, and the thin film transistor has A method for manufacturing a semiconductor device is provided, wherein a gate electrode is electrically connected to the lower wiring.

In the present invention, the thickness of the shielding film, the lower capacitor wiring and the lower wiring is 0.1 μm to 0.5 μm.
m.

In the present invention, the shielding film, the lower-layer capacitor wiring or the lower-layer wiring may be characterized in that an edge portion is formed in a tapered shape.

In the present invention, the thickness of the planarizing insulating film may be 0.5 μm to 1.5 μm.

The present invention may be a digital camera, a video camera, a goggle type display device, a sound reproducing device, a notebook personal computer, a portable information terminal, or a DVD device having the semiconductor device.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the present invention will be described with reference to FIG. First, a shielding film 102a, a lower capacitor wiring 102b, and a lower wiring 102c made of the same material are formed on a substrate 101.
To form For the substrate 101, quartz, glass, or the like is used.

The shielding film 102a, the lower-layer capacitor wiring 102b, and the lower-layer wiring 102c need to have a light-shielding property, and W, WSix, Cu, Al, or the like can be used. In addition to the above-described materials, any material can be used as long as it has light-blocking properties and conductivity and can withstand the temperature of heat treatment in a later process.

FIG. 1 shows a structure in which the shielding film 102a, the lower-layer capacitor wiring 102b, and the lower-layer wiring 102c are formed, but the present invention is not limited to this structure. Shielding film 1
02a, lower layer capacitor wiring 102b and lower layer wiring 102c may be formed. In particular, in the case where only the shielding film 102a is formed, any material which does not have conductivity but has light-shielding properties and can withstand the temperature of heat treatment in a later process is used.
It can be used as a material for a shielding film. For example, a material in which a black pigment is mixed with silicon, silicon oxide, silicon oxynitride, or the like can be used as a material of the shielding film.

The shielding film 102a, the lower capacitor wiring 102b, and the lower wiring 102c may be formed by patterning a single-layer film, or may be formed without patterning using a metal mask.

Next, the shielding film 102a, the lower layer capacitor wiring 10
An insulating film 103a is formed on the substrate 101 so as to cover 2b and the lower wiring 102c. As the insulating film 103a, an insulating film which can withstand the temperature of heat treatment in a later process can be used. (Figure 1
(A))

The shielding film 102a and the lower layer capacitor wiring 10
2b and the edge portion of the lower wiring 102c may be formed in a tapered shape. By forming the insulating film into a tapered shape, unevenness of an insulating film to be formed later can be reduced and the time of a polishing step by a CMP method can be shortened.

Next, the insulating film 103a is polished by the CMP method. Slurry, pad and CMP used for CMP method
A known apparatus and the like can be used, and a polishing method can be performed using a known method.

By polishing by the CMP method, unevenness on the surface of the insulating film 103a (portion surrounded by a dotted line in FIG. 1A) is flattened. The planarized insulating film 103a is referred to as a planarized insulating film 103b. (FIG. 1 (B))

Next, after cleaning the surface of the planarizing insulating film 103b, the planarizing insulating film 1b is formed on the lower layer capacitor wiring 102b.
03b, the capacitance wiring 1 formed of silicon
04 is formed. The capacitor 105 is formed by the lower layer capacitor wiring 102b, the planarization insulating film 103b, and the capacitor wiring 104.

The active layer 10 of the TFT 106 is disposed on the shielding film 102a so as to be in contact with the planarizing insulating film 103b.
7 is formed. The active layer 107 is a channel forming region 108
And the entire channel formation region 108 overlaps with the shielding film 102a via the planarizing insulating film 103b.

A gate insulating film 109 is formed on the planarizing insulating film 103b so as to cover the capacitance wiring 104 and the active layer 107.

In the process after the formation of the planarizing insulating film 103b, the TFT 106 may be formed by any process. In this embodiment mode, a top gate type TFT is described; however, a bottom gate type TFT may be used.

In this embodiment, the semiconductor layer formed on the flattening insulating film 103b is used as the active layer 107 of the TFT 106, but the present invention is not limited to this. The semiconductor layer may be used for another semiconductor element. For example, a diode may be formed on a planarizing insulating film, and a shielding film and a semiconductor layer may be overlapped with a planarizing insulating film interposed therebetween such that only light incident from the side opposite to the substrate is incident on the diode. good.

According to the present invention, the TFT 106
Light can be prevented from entering the channel formation region 108 from the substrate 101 side. In addition, the flattening insulating film 10
Since the surface of 3b is flattened, the TF formed thereon is increased without increasing the thickness of the insulating film covering the shielding film 102a, the lower capacitor wiring 102b, and the lower wiring 102c.
The disconnection of the active layer 107 and the capacitor wiring 104 of T106 can be prevented, and the mobility of the TFT 106 can be prevented from increasing.

[0052]

Embodiments of the present invention will be described below.

Example 1 FIG. 2 is a top view showing an example of a pixel of a liquid crystal display having a shielding film according to the present invention.

Reference numeral 201 denotes a source signal line, and reference numeral 202 denotes a gate signal line. Reference numeral 203 denotes a lower-layer capacitance line, which is provided in parallel with the gate signal line 202.

Reference numeral 205 denotes a pixel TFT, which controls input of a video signal input to the source signal line 201 to the pixel electrode 208. The pixel TFT 205 has an active layer 206 and a gate electrode 207, and a channel formation region is provided in a region where the gate electrode 207 and the active layer 206 overlap. Under the active layer 206, the shielding film 204
Are formed and overlap the entire channel formation region.

In this embodiment, the gate signal line 202 corresponds to the lower wiring 102c in FIG. A planarization insulating film (not shown) is formed on and in contact with the gate signal line 202, the lower layer capacitor wiring 203, and the shielding film 204.

The gate electrode 207 is electrically connected to the gate signal line 202. One of a source region and a drain region of the active layer 206 is connected to the source signal line 201 through the connection wiring 209, and the other is connected to the pixel electrode 20.
8 is connected.

Numeral 210 denotes a capacitance line formed simultaneously with the active layer 206, and the capacitance line 210 and the lower layer capacitance line 203 are formed.
A capacitor is formed in the region where. Also, 21
Reference numeral 1 denotes an upper-layer capacitance line, which overlaps with the capacitance line 210 via a gate insulating film (not shown), and is electrically connected to the lower-layer capacitance line 203 via a contact hole. A capacitor is also formed in a region where the capacitance wiring 210 and the upper-layer capacitance wiring 211 overlap.

In this embodiment, since the two capacitors overlap, the capacitance value of the capacitors can be increased while suppressing a decrease in the aperture ratio. The pixel TFT 20
It is possible to prevent light from entering the channel formation region of No. 5 from the active matrix substrate side. In addition, since the surface of the planarization insulating film (not shown) is planarized, the thickness of the insulating film covering the shielding film 204, the gate signal line 202, and the lower capacitor wiring 203 is increased without increasing the thickness of the insulating film. The active layer 206 of the pixel TFT 205 and the capacitor wiring 210 can be prevented from being disconnected.
The mobility of 205 can be prevented from increasing.

The present invention is not limited to the above pixel structure.

(Embodiment 2) In this embodiment, a method for simultaneously manufacturing a pixel portion and a TFT (an n-channel TFT and a p-channel TFT) of a driving circuit provided around the pixel portion on the same substrate will be described in detail. I do.

First, as shown in FIG. 3A, an active matrix made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass, or quartz. Shielding film 30 on substrate (hereinafter, substrate) 300
1a, a gate signal line 301b, and a lower layer capacitor wiring 301c are formed.

The shielding film 301a, the gate signal line 301b,
The lower layer capacitor wiring 301c is formed simultaneously. Specifically, W is set to a thickness of 0.1 μm to 0.5 μm (in this embodiment, 0.1 μm to 0.5 μm.
3 μm) and then ICP (Inductively Coupled)
Plasma: Inductively coupled plasma) Using an etching method, CF ₄ and Cl ₂ are mixed as an etching gas, and 500 W of RF (13.56 MHz) power is applied to a coil-type electrode at a pressure of 1 Pa to generate plasma. Do it. 100 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied.

In this embodiment, the shielding film 301a, the gate signal line 301b, and the lower capacitor wiring 301c are formed using W, but the present invention is not limited to this structure. In addition to W, WSix, Cu, Al, or the like can be used. In addition to the above-described materials, any material can be used as long as it has a light-shielding property and conductivity and can withstand a processing temperature in a later process.

Next, the shielding film 301a and the gate signal line 301
b and the lower layer wiring 301c.
An insulating film made of silicon oxide is formed thereon. As the insulating film, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be used. For example, SiH ₄ , N
H _3, N ₂ O silicon oxynitride film made from 250-8
00 nm (preferably 300-500 nm), as well as SiH
_{4. A} silicon oxynitride hydride film made of N ₂ O
It may be formed by laminating to a thickness of 800 to 800 nm (preferably 300 to 500 nm). Here, the insulating film made of silicon oxide has a single-layer structure of 1.0 μm, preferably 0.5 to
1.5 μm). Note that the material of the insulating film is not limited to silicon oxide.

Next, the planarizing insulating film 302 is formed by polishing the insulating film by the CMP method. The CMP method can be performed by a known method. In the polishing of an oxide film, a slurry of a solid-liquid dispersion system in which an abrasive having a diameter of 100 to 1000 nm is dispersed in an aqueous solution containing a reagent such as a pH adjuster is generally used. In this embodiment, a silica slurry (pH = 10 to 11) in which 20 wt% of fumed silica particles obtained by thermally decomposing silicon chloride gas are dispersed in an aqueous solution to which potassium hydroxide is added.

After the formation of the planarizing insulating film 302, semiconductor layers 303 to 307 to be active layers of TFTs or capacitor wirings are formed. The semiconductor layers 303 to 307 are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed by a laser crystallization method or a known thermal crystallization method. This semiconductor layer 3
03-307 has a thickness of 25-80 nm (preferably 30-80 nm).
６０60 nm). The material of the crystalline semiconductor film is not limited, but is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to form a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser is used.
In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions can be appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 300 Hz, and the laser energy density is set to 100 to 400 mJ / cm ² (typically, 200
３００300 mJ / cm ² ). When a YAG laser is used, its second harmonic is used, the pulse oscillation frequency is set to 30 to 300 kHz, and the laser energy density is set to 300 to 600 mJ / cm ² (typically 350 to 500 mJ / cm ² ).
² ) Then, a laser beam condensed linearly with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is set to 50 to 98%.

Next, a gate insulating film 308 covering the semiconductor layers 303 to 307 is formed. The gate insulating film 308 is formed by a plasma CVD method or a sputtering method and has a thickness of 40 to
The insulating film containing silicon is formed to have a thickness of 150 nm. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 nm. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetr
aethyl Orthosilicate) and O ₂ and a reaction pressure of 4
0 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.
56 MHz) It can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain favorable characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Then, a first conductive film 309a and a second conductive film 309b for forming a gate electrode are formed over the gate insulating film 308. In this embodiment, the first conductive film 309a is formed of Ta to a thickness of 50 to 100 nm, and the second conductive film 309b is formed of W to a thickness of 100 to 300 nm. (FIG. 3 (B))

The Ta film is formed by a sputtering method, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for the gate electrode. α phase T
If a film of tantalum nitride having a crystal structure close to that of the α phase of Ta is formed on a base of Ta with a thickness of about 10 to 50 nm to form the a film, a Ta film of the α phase can be easily obtained. .

When a W film is formed, it is formed by a sputtering method using W as a target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
It is desirable to set the resistance to Ωcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, the crystallization is inhibited and the resistance is increased. From this, when using the sputtering method,
By using a W target with a purity of 99.9999% or 99.99% and forming a W film with sufficient care so as not to mix impurities from the gas phase during film formation, the resistivity is 9 to 20 μΩcm. Can be realized.

In this embodiment, the first conductive film 309 is used.
a is Ta and the second conductive film 309b is W, but there is no particular limitation, and Ta, W, Ti, Mo, Al, and Cu are all used.
Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. An example of another combination other than this embodiment is a combination in which the first conductive film 309a is formed of tantalum nitride (TaN), the second conductive film 309b is formed of W, and the first conductive film 309a is formed of tantalum nitride (TaN). T
aN), the second conductive film 309b is made of Al, and the first conductive film 309a is made of tantalum nitride (Ta).
N), and the second conductive film 309b is preferably formed using a combination of Cu.

Next, resist masks 310 to 31 are used.
5, and a first etching process for forming electrodes and wiring is performed. In this embodiment, the ICP (Inductively
Coupled Plasma: Inductively coupled plasma) etching method, CF ₄ and Cl ₂ are mixed in the etching gas and 1 Pa
500W RF (13.56MHz) to coil type electrode at pressure of
Power is supplied to generate plasma. 100 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF ₄
When Cl and Cl ₂ are mixed, both the W film and the Ta film are etched to the same extent.

Under the above-mentioned etching conditions, the shape of the resist mask is made appropriate, so that the ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. Become. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%. Selectivity ratio of silicon oxynitride film to W film is 2 to 4 (typically 3)
Therefore, the exposed surface of the silicon oxynitride film is etched by about 20 to 50 nm by the over-etching process. In this manner, the first shape conductive layers 316 to 321 (the first conductive layers 316a to 321a and the second conductive layers 316b to 321b) composed of the first conductive layer and the second conductive layer by the first etching process. To form 322
Denotes a gate insulating film, and the first shape conductive layers 316 to 3
The area not covered by 21 is etched by about 20 to 50 nm to form a thinned area.

Then, a first doping process is performed to add an impurity element imparting n-type. (FIG. 3C) The doping method may be an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 1.
0 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60 to ¹
The operation is performed at 00 keV. An element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used as the n-type impurity element. Here, phosphorus (P) is used.
In this case, the conductive layers 316 to 320 serve as a mask for the impurity element imparting n-type, and the first impurity regions 323 to 327 are formed in a self-aligned manner. The first impurity regions 323 to 327 have 1 × 10 ²⁰ to 1 × 10 ²¹ atomic / cm ^3.
Is added in the concentration range of n.

Next, a second etching process is performed as shown in FIG. Similarly, using the ICP etching method,
Mix CF ₄ , Cl ₂ and O ₂ in the etching gas
RF power (13.56 MH)
z) is supplied to generate plasma. Apply 50W RF (13.56MHz) power to the substrate side (sample stage)
A self-bias voltage lower than that in the first etching process is applied. Under such conditions, the W film is anisotropically etched, and Ta, which is the first conductive layer, is anisotropically etched at a lower etching rate to form the second shape conductive layers 333 to 338 (first conductive layer). Of the conductive layers 333a to 338a and the second conductive layers 333b to 338b). 332 is a gate insulating film, and the second shape conductive layers 333 to 33
The area not covered by 8 is further etched by about 20 to 50 nm to form a thinned area.

The etching reaction of the W film or the Ta film by the mixed gas of CF ₄ and Cl ₂ can be inferred from the generated radical or ion species and the vapor pressure of the reaction product.
Comparing the vapor pressures of fluorides and chlorides of W and Ta, W
WF ₆ is extremely high and other WC
l ₅ , TaF ₅ and TaCl ₅ are comparable. Therefore, C
With the mixed gas of F ₄ and Cl ₂ , both the W film and the Ta film are etched. However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in Ta, the increase in the etching rate is relatively small even if F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ .
Since the oxide of Ta does not react with fluorine or chlorine,
The etching rate of the a film decreases. Therefore, the W film and Ta
It is possible to make a difference in the etching rate with the film, and it is possible to make the etching rate of the W film larger than that of the Ta film.

Then, a second doping process is performed as shown in FIG. In this case, doping with an impurity element imparting n-type is performed under a condition of a higher acceleration voltage with a lower dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 keV and the dose is set to 1 × 10 ¹³ / cm ² , and a new impurity region is formed inside the first impurity region formed in the semiconductor layer in FIG. . The doping is performed using the second shape conductive layers 333 to 337 as masks for impurity elements,
Doping is performed so that an impurity element is also added to a region below the 337a. Thus, the second conductive layers 333a to 333a to
Third impurity regions 341 to 345 overlapping with 337a,
Second impurity regions 346 to 350 are formed between the first impurity region and the third impurity region. The impurity element imparting n-type is 1 × 10 ¹⁷ to 1 × 1 in the second impurity region.
The concentration is set to 0 ¹⁹ atoms / cm ³ , and the concentration is set to 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ in the third impurity region.

Then, as shown in FIG. 4C, fourth impurity regions 354 to 356 having a conductivity type opposite to one conductivity type are formed in the semiconductor layer 304 forming the p-channel TFT. Using the second conductive layer 334 as a mask for an impurity element, an impurity region is formed in a self-aligned manner. At this time, the semiconductor layers 303 and 3 forming an n-channel TFT are formed.
05, 306 and 307 are resist masks 351 to 353
To cover the entire surface. Each of the impurity regions 354 to 356 is doped with phosphorus at a different concentration, but is formed by an ion doping method using diborane (B ₂ H ₆ ), and the impurity concentration in each of the regions is 2 × 10 ²⁰ to 2x1
0 ²¹ atoms / cm ³ .

Through the above steps, an impurity region is formed in each semiconductor layer. The second conductive layers 333 to 336 overlapping with the semiconductor layer function as gate electrodes. Also, 3
37 functions as an upper layer capacitor wiring, and 338 functions as a source signal line.

In order to control the conductivity type in this way, FIG.
As shown in FIG. 3A, the impurity element added to each semiconductor layer is activated. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, laser annealing or rapid thermal annealing (RT
Method A) can be applied. In the thermal annealing method, the oxygen concentration is 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to 6
In this embodiment, the heat treatment is performed at 500 ° C. for 4 hours. However, when the wiring material used for 333 to 338 is weak to heat, activation is preferably performed after forming an interlayer insulating film (mainly containing silicon) to protect the wiring and the like.

Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
May be performed.

Next, the first interlayer insulating film 357 is formed with a thickness of 100 to 200 nm from a silicon oxynitride film. A second interlayer insulating film 358 made of an organic insulating material is formed thereon.
To form Next, etching for forming a contact hole is performed.

Then, a source wiring 359 for forming a contact with the source region of the semiconductor layer in the driver circuit 406 is formed.
To 361, drain wirings 362 and 363 for forming contacts with the drain region are formed. In addition, the pixel portion 407
, The pixel electrodes 366, 367, the connection wiring 365
Is formed (FIG. 5B). The source wiring 338 is electrically connected to the adjacent pixel TFT 404 by the connection wiring 365. The pixel electrode 366 is connected to the pixel TFT 40
The active layer formed from the fourth semiconductor layer 306 and the capacitor wiring formed from the semiconductor layer 307 are electrically connected to each other. Note that the pixel electrode 367 belongs to an adjacent pixel.

Although not shown, the upper capacitor wiring 3
37 is electrically connected to the lower layer capacitor wiring 301c. A capacitor is formed by the lower-layer capacitance wiring 301c, the planarization insulating film 302, and the capacitance wiring formed from the semiconductor layer 307. A capacitor is formed by the capacitor wiring formed from the semiconductor layer 307, the gate insulating film 332, and the upper layer capacitor wiring 337. The storage capacitor 405 is formed by combining these two capacitors.

As described above, the n-channel TFT 40
1, p-channel TFT 402, n-channel TFT 4
03 and a pixel portion 407 including a pixel TFT 404 and a storage capacitor 405 can be formed over the same substrate.

The n-channel TFT 40 of the driving circuit 406
Reference numeral 1 denotes a third impurity region 346 (G which overlaps with the channel formation region 368 and the second conductive layer 333 forming the gate electrode.
OLD region), a second impurity region 341 (LDD region) formed outside the gate electrode, and a first impurity region 327 functioning as a source region or a drain region. The p-channel TFT 402 includes a channel formation region 369, a fourth impurity region 356 overlapping with the second conductive layer 334 forming a gate electrode, a fourth impurity region 355 formed outside the gate electrode, a source region or a drain. There is a fourth impurity region 354 functioning as a region. A channel formation region 370 and a second conductive layer 335 forming a gate electrode are formed in the n-channel TFT 403.
A third impurity region 348 (GOLD region) overlapping with the second impurity region 343 formed outside the gate electrode
(LDD region) and a first impurity region 329 functioning as a source region or a drain region.

In the pixel TFT 404 of the pixel portion 407, a channel forming region 371, a third impurity region 349 (GOLD region) overlapping with the second conductive layer 336 forming the gate electrode, and a second region formed outside the gate electrode are formed. Impurity region 344 (LDD region) and a first impurity region 330 functioning as a source region or a drain region.
In the storage capacitor 405, in the capacitor wiring formed from the semiconductor layer 307, the region indicated by 331 has the same concentration as the first impurity region, and the region indicated by 345 has the same concentration as the third impurity region. In the region indicated by 350, an impurity element imparting n-type is added at the same concentration as the second impurity region.

The shielding film 301a overlaps the entire channel forming region 371 of the pixel TFT 404 via the planarizing insulating film 302.

AA ′ of the top view of the pixel shown in the first embodiment
Corresponds to AA ′ in FIG. 5B. That is, the source signal line 338, the connection wiring 365, the gate electrode 336, the shielding film 301a, the pixel electrode 366, the gate signal line 301b, and the lower capacitance wiring 30 shown in FIG.
1c, 201, 209, 207, 204, 208 and 20 in FIG.
2, 203, 210 and 211 respectively.

The pixel structure of the present invention is arranged so that the edge of the pixel electrode overlaps with the gate signal line so that the gap between the pixel electrodes can be shielded from light.

Next, a process for manufacturing an active matrix type liquid crystal display from the above-described active matrix substrate will be described. FIG. 6 is used for the description.

First, an alignment film 467 is formed on the active matrix substrate shown in FIG.

On the other hand, a counter substrate 469 is prepared. A color filter layer 470 and an overcoat layer 473 are formed over the counter substrate 469.

Further, a color filter layer 470 is formed in accordance with the connection wiring 365. The color filter of each color is a mixture of an acrylic resin and a pigment, and is formed with a thickness of 1 to 3 μm. This can be formed in a predetermined pattern using a photosensitive material and a mask. The overcoat layer is formed of a light-curing or thermosetting organic resin material, for example, using polyimide or acrylic resin.

The arrangement of the spacers may be determined arbitrarily. For example, it is preferable that the spacers are arranged on the opposing substrate so as to be positioned on the connection wiring. Further, the spacer may be arranged on the counter substrate with its position aligned with the TFT of the driver circuit 406. The spacer may be disposed over the entire surface of the drive circuit portion, or may be disposed so as to cover the source wiring and the drain wiring.

After forming the overcoat layer 473, the counter electrode 476 is formed by patterning, and after forming the alignment film 474, a rubbing process is performed.

Then, the active matrix substrate on which the pixel portion 407 and the drive circuit 406 are formed and the counter substrate are bonded with a sealant 468. A filler is mixed in the sealant 468, and the two substrates are bonded at a uniform interval by the filler and the spacer. Thereafter, a liquid crystal material is injected between the two substrates, and completely sealed with a sealing agent (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display shown in FIG. 6 is completed.

Note that the present invention is not limited to the above-described manufacturing method. This embodiment can be implemented in combination with the first embodiment.

(Embodiment 3) In this embodiment, the structure of a CMP apparatus used for polishing by the CMP method will be described.

FIG. 7 is a side view of the CMP apparatus of this embodiment.
FIG. 7A is a perspective view of FIG. Reference numeral 701 denotes a surface plate, which is rotated by a drive shaft (a) 702 in the direction of the arrow or in the opposite direction. The position of the drive shaft (a) 702 is fixed by an arm (a) 703.

A known polishing cloth or polishing pad can be used as the pad 704 in which the pad 704 is provided on the surface plate 701. A slurry supply nozzle 705 for supplying the slurry to the pad 704 is provided. In this embodiment, the slurry is supplied from the slurry supply nozzle 705 to a slurry supply position 710 substantially at the center of the pad 704. Known materials can be used for the slurry.

Reference numeral 706 denotes a carrier, which has a function of fixing the active matrix substrate 707 and rotating it on the pad 704. The carrier 706 is rotated by the drive shaft (b) 708 in the direction of the arrow or in the opposite direction. The position of the drive shaft (b) 708 is fixed by an arm (a) 709.

The surface of the active matrix substrate 707 on which an insulating film to be a flattening film is formed is a pad 704.
Held to the side.

Although not provided in this embodiment, when a polishing cloth is used for the pad 704, the deformation of the polishing cloth at the edge of the active matrix substrate can be suppressed by providing a pad pressure ring. When a pressure of 1.2 to 1.6 times the polishing pressure of the active matrix substrate 707 is applied to the pad pressure ring, the surface profile of the polishing cloth changes and uniform polishing cloth deformation is obtained.

FIG. 8 is a detailed view of the carrier 706 shown in FIG. The carrier 706 includes a polishing housing 711
, A wafer chuck 713 and a retainer ring 712. The wafer chuck 713 holds the active matrix substrate 707, and the retainer ring 712 prevents the active matrix substrate 707 from coming off during polishing. The polishing housing 711 has a function of holding the wafer chuck 713 and the retainer ring 712 and applying a polishing pressure.

Since the carrier 707 needs functions of pressurization and rotation, it is common to use a system having a rotation axis at the center and applying a load along this axis. In the case of the central axis load, the distribution of the load in the plane of the active matrix substrate is highest below the central axis, and it is inevitable that the load decreases toward the periphery. For this purpose, a known auxiliary load mechanism may be incorporated in the polishing housing to uniformly polish the active matrix substrate in the plane.

This embodiment can be implemented in combination with the first embodiment or the second embodiment.

(Embodiment 4) An example of a method of manufacturing a liquid crystal display, which is one of the semiconductor devices of the present invention, which is different from that of Embodiment 2, will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel TFT and a storage capacitor in a pixel portion and a TFT of a source signal line driver circuit and a gate signal line driver circuit provided in the periphery of the pixel portion will be described in detail according to steps.

In FIG. 9A, a glass substrate such as barium borosilicate glass or alumino borosilicate glass represented by Corning # 7059 glass or # 1737 glass, a quartz substrate, or the like is used as the substrate 501.
In the case of using a glass substrate, the glass strain point should be 10
The heat treatment may be performed in advance at a temperature lower by about 20 ° C. Then, a shielding film 502 is formed on the substrate 501 at a position where the TFT is to be formed.

The shielding film 502 sets W to 0.1 μm to 0.5 μm.
After forming to a thickness of 0.3 μm (0.3 μm in this embodiment),
Using an ICP (Inductively Coupled Plasma) etching method, CF ₄ is used as an etching gas.
And Cl ₂ are mixed, and a pressure of 1 Pa is applied to the coil-type electrode.
The plasma is generated by supplying 0 W RF (13.56 MHz) power. 100W RF on substrate side (sample stage)
(13.56 MHz) Power is applied and a substantially negative self-bias voltage is applied.

In this embodiment, the shielding film 502 is formed using W, but the present invention is not limited to this configuration. In addition to W, it is possible to use a metal such as WSix, Cu, or Al, or a material in which a black pigment is mixed in silicon, silicon oxide, silicon oxynitride, or the like. In addition to the above materials,
Any material can be used as long as it has a light-shielding property and can withstand a processing temperature in a later process.

Next, the substrate 50 is covered so as to cover the shielding film 502.
An insulating film made of silicon oxide is formed on 1. The insulating film is
A silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be used. For example, SiH ₄ ,
A silicon oxynitride film made of NH ₃ and N ₂ O
800 nm (preferably 300-500 nm), as well as Si
A silicon oxynitride hydride film formed from H ₄ and N ₂ O
It may be formed by laminating to a thickness of 0 to 800 nm (preferably 300 to 500 nm). Here, the insulating film made of silicon oxide has a single-layer structure and a thickness of 0.5 to 1.5 μm. Note that the material of the insulating film is not limited to silicon oxide.

Next, the planarizing insulating film 503 is formed by polishing the insulating film by the CMP method. The CMP method can be performed by a known method. In the polishing of the oxide film, a slurry of a solid-liquid dispersion system in which an abrasive having a diameter of 100 to 1000 nm is generally dispersed in an aqueous solution containing a reagent such as a pH adjuster is used. In this embodiment, a silica slurry (pH = 10 to 11) in which 20 wt% of fumed silica particles obtained by thermally decomposing silicon chloride gas are dispersed in an aqueous solution to which potassium hydroxide is added.

After forming the planarizing insulating film 502, 25 to 80 nm
An amorphous semiconductor layer having a thickness of (preferably 30 to 60 nm) having an amorphous structure is formed by a method such as a plasma CVD method or a sputtering method. The semiconductor film having an amorphous structure includes an amorphous semiconductor layer and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. As a result, the planarizing insulating film 5
03 can be prevented from being contaminated, and the T
Variations in FT characteristics and variations in threshold voltage can be reduced.

Then, a crystallization step is performed to form a crystalline semiconductor layer 504 from the amorphous semiconductor layer. Laser annealing method, thermal annealing method (solid phase growth method),
Alternatively, a rapid thermal annealing method (RTA method) can be applied. When a glass substrate or a plastic substrate having low heat resistance as described above is used, it is particularly preferable to apply a laser annealing method. In the RTA method,
An infrared lamp, a halogen lamp, a metal halide lamp, a xenon lamp, or the like is used as a light source. Alternatively, the crystalline semiconductor layer 504 can be formed by a crystallization method using a catalytic element according to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652. In the crystallization step, first, it is preferable to release hydrogen contained in the amorphous semiconductor layer,
Heat treatment at 400 to 500 [deg.] C. for about 1 hour to reduce the amount of hydrogen contained to 5 atom% or less and then to crystallize is preferable because roughness of the film surface can be prevented.

In the step of forming an amorphous silicon film by the plasma CVD method, SiH ₄ and argon (A
When the substrate temperature at the time of film formation is 400 to 450 ° C. using r), the hydrogen concentration in the amorphous silicon film is 5 atomic
It can be less than%. In such a case, heat treatment for releasing hydrogen is unnecessary.

When the crystallization is performed by laser annealing, a pulse oscillation type or continuous oscillation type excimer laser or argon laser is used as the light source. When a pulse oscillation type excimer laser is used, laser annealing is performed by processing a laser beam into a linear shape. Laser annealing conditions are appropriately selected by the practitioner, for example,
The laser pulse oscillation frequency is 300 Hz, and the laser energy density is 100 to 500 mJ / cm ² (typically 30 to
0 to 400 mJ / cm ² ). Then, a linear beam is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear beam at this time is set to 50 to 98%. In this manner, as shown in FIG.
4 can be obtained.

Then, using a first photomask (PM1), a resist pattern is formed on the crystalline semiconductor layer 504 by photolithography, and the crystalline semiconductor layer is divided into islands by dry etching. FIG.
Semiconductor layers 505 to 508 are formed as shown in FIG. For dry etching of the crystalline silicon film, a mixed gas of CF ₄ and O ₂ is used.

For such a semiconductor layer, an impurity element imparting a p-type is added at a concentration of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ for the purpose of controlling the threshold voltage (Vth) of the TFT. It may be added to the entire surface of the semiconductor layer. P for semiconductor
Elements belonging to Group 13 of the periodic table, such as boron (B), aluminum (Al), and gallium (Ga), are known as impurity elements imparting a mold. As the method, an ion implantation method or an ion doping method (or an ion shower doping method) can be used, but the ion doping method is suitable for treating a large-area substrate. In the ion doping method, diborane (B ₂ H ₆ ) is used as a source gas and boron (B) is used.
Is added. The implantation of such an impurity element is not always necessary and may be omitted. However, it is a method preferably used for keeping the threshold voltage of the n-channel TFT within a predetermined range.

The gate insulating film 509 is formed of a silicon-containing insulating film with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 nm. A silicon oxynitride film formed by adding O ₂ to SiH ₄ and N ₂ O is
The reduced fixed charge density in the film makes it a preferred material for this application. Also, SiH ₄ , N ₂ O and H ₂
Is preferably used because the interface defect density of the gate insulating film can be reduced. Of course, the gate insulating film is not limited to such a silicon oxynitride film,
Another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, a TEOS (Tetraethyl Orthosilicat
e) and O ₂ were mixed, the reaction pressure was 40 Pa, and the substrate temperature was 300.
It can be formed by discharging at a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² . The silicon oxide film thus manufactured is
Good characteristics as a gate insulating film can be obtained by thermal annealing at 00 to 500 ° C. (FIG. 9 (B))

Then, as shown in FIG. 9C, a heat-resistant conductive layer 511 for forming a gate electrode on the first shape gate insulating film 509 is formed to a thickness of 200 to 400 nm (preferably 250 to 350 nm). It is formed with a thickness. The heat-resistant conductive layer 511 may be formed as a single layer, or may have a stacked structure including a plurality of layers such as two layers or three layers as necessary. The heat-resistant conductive layer includes an element selected from Ta, Ti, and W, an alloy containing the above element, or an alloy film combining the above elements. These heat-resistant conductive layers are formed by a sputtering method or a CVD method, and it is preferable to reduce the concentration of impurities contained therein in order to reduce the resistance. In particular, the oxygen concentration is preferably 30 ppm or less. In this embodiment, a W film is formed to a thickness of 300 nm. The W film may be formed by sputtering using W as a target, or may be formed by thermal CVD using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to reduce the resistance in order to use it as a gate electrode, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, the crystallization is inhibited and the resistance is increased. From this, in the case of using the sputtering method, W of 99.9999% purity can be obtained.
By using a target and forming the W film with sufficient care so as not to mix impurities from the gas phase during film formation, a resistivity of 9 to 20 μΩcm can be realized.

On the other hand, when a Ta film is used for the heat-resistant conductive layer 511, it can be similarly formed by a sputtering method. The Ta film uses Ar as a sputtering gas. Also, if an appropriate amount of Xe or Kr is added to the gas during sputtering,
The internal stress of the film to be formed can be relaxed to prevent the film from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for the gate electrode.
The resistivity of the film was about 180 μΩcm, and was not suitable for use as a gate electrode. Since the TaN film has a crystal structure close to the α-phase, if a TaN film is formed under the Ta film, an α-phase Ta film can be easily obtained. Although not shown, phosphorus (P) having a thickness of about 2 to 20 nm is formed under the heat-resistant conductive layer 511.
It is effective to form a silicon film doped with GaAs.
Accordingly, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, a small amount of the alkali metal element contained in the heat-resistant conductive layer 511 diffuses into the first shape gate insulating film 509. Can be prevented. In any case, the heat-resistant conductive layer 511 preferably has a resistivity in the range of 10 to 50 μΩcm.

Next, using the second photomask (PM2), resist masks 512 to 517 are formed by photolithography. Then, a first etching process is performed. In this embodiment, an ICP etching apparatus is used, and Cl ₂ and CF ₄ are used as etching gases.
A plasma is formed by applying an RF (13.56 MHz) power of 3.2 W / cm ² at a pressure of 1 Pa. RF (13.56 MHz) power of 224 mW / cm ² is also applied to the substrate side (sample stage), whereby a substantially negative self-bias voltage is applied. Under these conditions, the etching rate of the W film is about 100 nm / m
in. The first etching process estimates the time when the W film is just etched based on the etching rate,
The time obtained by increasing the etching time by 20% was defined as the etching time.

By the first etching process, conductive layers 518 to 523 having a first tapered shape are formed. The angle of the tapered portion of the conductive layers 518 to 523 is 15 to 30 °
It is formed so that In order to perform etching without leaving a residue, over-etching is performed to increase the etching time at a rate of about 10 to 20%. Since the selectivity of the silicon oxynitride film (the first shape gate insulating film 509) to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film Etch about 20-50nm first
A gate insulating film 580 having a second shape in which a tapered shape is formed is formed near the end portions of the conductive layers 518 to 523 having the tapered shape.

Then, a first doping process is performed to
An electric impurity element is added to the semiconductor layer. Here, n
A step of adding an impurity element for giving a mold is performed. First shape
The masks 512 to 517 on which the conductive layers are formed are left as they are.
And conductive layers 518 to 523 having a first tapered shape.
Element that imparts n-type in a self-aligned manner with a mask as a mask
Is added by an ion doping method. Impurity element giving n-type
The tapered portion at the end of the gate electrode and the second shape
Through the gate insulating film 580, and the half located thereunder.
The dose is 1 × 1 to be added to reach the conductor layer.
0¹³~ 5 × 10 ¹⁴atoms / cm^TwoAnd the acceleration voltage is 80 to 1
Performed at 60 keV. as an impurity element that imparts n-type
Group 15 elements, typically phosphorus (P) or arsenic
Element (As) is used, but phosphorus (P) is used here.
The first impurity region 52 is formed by such an ion doping method.
1 × 10 for 4-527²⁰~ 1 × 10^{twenty one}atomic / cm^ThreeNo
Impurity element that imparts n-type is added in the
Second impurity region (A) 529 formed below portion
1 to 1 are not necessarily uniform in the same area.
0¹⁷~ 1 × 10²⁰atomic / cm^ThreeN-type within the concentration range of
Impurity element is added. (FIG. 10A)

In this step, in the second impurity regions (A) 529 to 532, the change in the concentration of the impurity element imparting n-type contained at least in the portion overlapping the first shape conductive layers 518 to 523 is as follows: This reflects the change in the thickness of the tapered portion. That is, the second impurity region (A) 529
The concentration of phosphorus (P) added to the conductive layers 532 to 532 gradually decreases in the region overlapping the first shape conductive layers 518 to 523 from the end of the conductive layer toward the inside. This is because the concentration of phosphorus (P) reaching the semiconductor layer changes depending on the difference in the thickness of the tapered portion.

Next, a second etching process is performed as shown in FIG. The etching process is also performed using an ICP etching apparatus, and CF ₄ and C are used as etching gases.
RF power 3.2 W / cm ² (13.56 MHz) using l ₂ mixed gas
z), bias power 45mW / cm ² (13.56MHz), pressure 1.0P
Etching is performed with a. Conductive layers 540 to 545 having the second shape formed under these conditions are formed. A tapered portion is formed at the end, and the tapered shape gradually increases inward from the end. As compared with the first etching process, the ratio of the isotropic etching is increased by the lower bias power applied to the substrate side, and the angle of the tapered portion is 30 to 60 °. Mask 512-5
17 is etched and the end is scraped, and the masks 534 to 5
39. The surface of the second shape gate insulating film 580 is etched by about 40 nm, and a third shape gate insulating film 570 is newly formed.

Then, an impurity element imparting n-type is doped under a condition of a high acceleration voltage with a lower dose than in the first doping process. For example, when the accelerating voltage is 70 to 120
KeV and a dose of 1 × 10 ¹³ / cm ^{2 so} that the impurity concentration in a region overlapping with the second shape conductive layers 540 to 545 is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ^3. I do. Thus, the second impurity region (B) 546-
550 are formed.

Then, impurity regions 556 and 557 of a conductivity type opposite to one conductivity type are formed in the semiconductor layers 505 and 507 forming the p-channel TFT. Also in this case, an impurity element imparting p-type is added using the second shape conductive layers 540 and 542 as a mask to form an impurity region in a self-aligned manner. At this time, resist masks 551 to 553 are formed using the third photomask (PM3) to cover the entire surfaces of the semiconductor layers 506 and 508 forming the n-channel TFT. The impurity regions 556, 5 formed here
57 is formed by an ion doping method using diborane (B ₂ H ₆ ). The concentration of the impurity element imparting p-type in impurity regions 556 and 557 is 2 × 10 ²⁰ to 2 × 10 ²¹ atoms / cm ^3.
So that

However, the impurity regions 556,
Numeral 57 designates 3 containing an impurity element imparting n-type.
It can be divided into two areas. The third impurity regions 556a and 557a are 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm.
An impurity element imparting n-type at a concentration of ³ is contained, and the fourth impurity regions (A) 556b and 557b are 1 × 10 ¹⁷ to 1 ×
An impurity element imparting n-type at a concentration of 10 ²⁰ atoms / cm ³⁶ is included, and the fourth impurity regions (B) 556c and 557c have an n-type concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^3. Contains an impurity element to be provided. However, the concentration of the impurity element imparting p-type in these impurity regions 556b, 556c, 557b, and 557c is set to 1 × 10 ¹⁹ atoms / cm ³ or more, and the third impurity regions 556a and 557a are formed.
In this case, the concentration of the impurity element imparting p-type is set to be 1.5 to 3 times the concentration of the impurity element imparting n-type, so that the p-channel type T
There is no problem because it functions as the source and drain regions of the FT. In addition, the fourth impurity regions (B) 556c and 557c are formed so as to partially overlap with the conductive layer 540 or 542 having the second tapered shape.

Thereafter, as shown in FIG.
The first interlayer insulating film 558 is formed on the conductive layers 540 to 545 having the shapes described above and the gate insulating film 570. First
The interlayer insulating film 558 may be formed of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film combining these. In any case, the first interlayer insulating film 558 is formed from an inorganic insulating material. The thickness of the first interlayer insulating film 558 is 100 to 200 nm. First interlayer insulating film 55
When a silicon oxide film is used as 8, plasma CVD
TEOS and O ₂ are mixed by the method, the reaction pressure is 40 Pa, the substrate temperature is 300-400 ° C., and the high frequency (13.56 MHz)
It can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . In the case where a silicon oxynitride film is used as the first interlayer insulating film 558, Si
A silicon oxynitride film formed from H ₄ , N ₂ O, and NH ₃ or a silicon oxynitride film formed from SiH ₄ , N ₂ O may be used. The production conditions in this case are as follows:
00Pa, substrate temperature 300-400 ° C, high frequency (60
MHz) It can be formed at a power density of 0.1 to 1.0 W / cm ² . Further, as the first interlayer insulating film 558, SiH ₄ ,
A silicon oxynitride hydride film formed from N ₂ O and H ₂ may be used. Similarly, a silicon nitride film is formed by plasma CVD.
It can be made from iH ₄ and NH ₃ .

Then, a step of activating the impurity elements imparting n-type or p-type added at the respective concentrations is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less,
Preferably in a nitrogen atmosphere of 0.1 ppm or less 400 ~
The heat treatment is performed at 700 ° C., typically 500 to 600 ° C. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours.
When a plastic substrate having a low heat-resistant temperature is used as the substrate 501, a laser annealing method is preferably used.

Subsequent to the activation step, the atmosphere gas is changed, and the atmosphere gas is changed to 300 to 100% in an atmosphere containing 3 to 100% hydrogen.
A heat treatment is performed at 450 ° C. for 1 to 12 hours to hydrogenate the semiconductor layer. This step is to terminate dangling bonds of 10 ¹⁶ to 10 ¹⁸ / cm ^{3 in} the semiconductor layer by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed. In any case, the semiconductor layer 5
It is desirable that the defect density in the range of 0.05 to 508 be 10 ¹⁶ / cm ³ or less.
% May be provided.

Then, a second interlayer insulating film 559 made of an organic insulating material is formed with an average thickness of 1.0 to 2.0 μm. As organic resin materials, polyimide, acrylic,
Polyamide, polyimide amide, BCB (benzocyclobutene) and the like can be used. For example, in the case of using a polyimide of a type that is thermally polymerized after being applied to a substrate, it is formed by firing at 300 ° C. in a clean oven.
In the case of using acrylic, a two-component type is used, and after mixing the main material and the curing agent, the whole surface is applied using a spinner and then pre-heated at 80 ° C. for 60 seconds on a hot plate. Then, it can be formed by firing in a clean oven at 250 ° C. for 60 minutes.

As described above, by forming the second interlayer insulating film 559 with an organic insulating material, the surface can be satisfactorily flattened. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. However, since it is hygroscopic and is not suitable as a protective film, it is preferable to use it in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the first interlayer insulating film 558 as in this embodiment. .

Thereafter, using a fourth photomask (PM4), a resist mask having a predetermined pattern is formed, and contact holes are formed in the respective semiconductor layers and reach the impurity regions serving as source regions or drain regions. The contact hole is formed by a dry etching method. In this case, a second interlayer insulating film 5 made of an organic resin material is used by using a mixed gas of CF ₄ , O ₂ and He as an etching gas.
First, the first interlayer insulating film 558 is etched using CF ₄ and O ₂ as etching gases. Further, in order to increase the selectivity with respect to the semiconductor layer, a contact hole can be formed by switching the etching gas to CHF ₃ and etching the third shape gate insulating film 570.

Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, a resist mask pattern is formed by a fifth photomask (PM5), and the source wirings 560 to 564 and the drain wirings 565 to 565 are formed by etching.
68 are formed. The pixel electrode 569 is formed simultaneously with the drain wiring. The pixel electrode 571 represents a pixel electrode belonging to an adjacent pixel. Although not shown, in this embodiment, this wiring is formed by forming a Ti film with a thickness of 50 to 150 nm,
Forming a contact with an impurity region forming a source or drain region of the semiconductor layer, forming aluminum (Al) to a thickness of 300 to 400 nm on the Ti film,
Further, a transparent conductive film was formed thereon with a thickness of 80 to 120 nm. Indium oxide zinc oxide alloy (In ₂ O ₃ —ZnO) and zinc oxide (ZnO) are also suitable materials for the transparent conductive film, and gallium (Ga) is added to increase the transmittance and conductivity of visible light. Zinc oxide (ZnO: G
a) can be preferably used.

Thus, a substrate having TFTs of drive circuits (source signal line drive circuit and gate signal line drive circuit) and pixel TFTs of a pixel portion is completed on the same substrate by using five photomasks. Can be. The driving circuit includes a first p-channel TFT 600, a first n-channel TFT 601, a second p-channel TFT 602, and a second p-channel TFT 602.
N-channel type TFT 603, and the pixel portion has a pixel TFT 6
04, a storage capacitor 605 is formed.

In the first p-channel TFT 600, a conductive layer having a second tapered shape has a function as a gate electrode 620, and the semiconductor layer 505 functions as a channel formation region 606 and a source or drain region. Third impurity region 607a, fourth impurity region (A) 60 forming an LDD region that does not overlap with gate electrode 620
7b, a structure having a fourth impurity region (B) 607c forming an LDD region partly overlapping the gate electrode 620.

In the first n-channel TFT 601, a conductive layer having a second tapered shape has a function as a gate electrode 621, and a semiconductor layer 506 functions as a channel formation region 608 and a source or drain region. First impurity region 609a, second impurity region (A) 60 forming an LDD region that does not overlap with gate electrode 621
9b, a structure having a second impurity region (B) 609c forming an LDD region partly overlapping with the gate electrode 621. For the channel length of 2 to 7 μm, the length of the portion where the second impurity region (B) 609c overlaps with the gate electrode 621 is 0.1 to 0.3 μm. The length of Lov is controlled from the thickness of the gate electrode 621 and the angle of the tapered portion. By forming such an LDD region in an n-channel TFT, a high electric field generated in the vicinity of the drain region is relieved, and the generation of hot carriers is prevented.
Deterioration of T can be prevented.

Second p-channel TFT 60 of drive circuit
2, a conductive layer having a second tapered shape has a function as a gate electrode 622, and a third impurity region 611 a which functions as a channel formation region 610, a source region or a drain region in the semiconductor layer 507, and a gate electrode 622.
A fourth impurity region (A) 611b forming an LDD region which does not overlap with the LDD, and an LD partially overlapping with the gate electrode 622;
The structure has a fourth impurity region (B) 611c that forms the D region.

The driving circuit has a logic circuit such as a shift register and a buffer, and a sampling circuit formed by an analog switch. In FIG. 11B, the TFTs forming them have a single-gate structure in which one gate electrode is provided between a pair of sources and drains. A gate structure may be used.

In the pixel TFT 604, a conductive layer having a second tapered shape has a function as a gate electrode 624, and the semiconductor layer 508 has channel forming regions 614a, 614a.
4b, first impurity regions 615a and 617 functioning as a source region or a drain region, a second impurity region (A) 615b forming an LDD region not overlapping with the gate electrode 624, and an LD partially overlapping with the gate electrode 624.
The structure has a second impurity region (B) 615c that forms the D region. Second impurity region (B) 615
The length of the portion where c overlaps with the gate electrode 624 is 0.1 to
0.3 μm. In addition, a semiconductor extending from the first impurity region 617 and including a second impurity region (A) 619b, a second impurity region (B) 619c, and a region 618 to which an impurity element which determines a conductivity type is not added. Layer and third
A storage capacitor 605 is formed from an insulating layer formed of the same layer as the gate insulating film having the shape of FIG. 3A and an upper layer capacitor wiring 625 formed of the second tapered conductive layer.

Also, the conductive layer 5 having the second tapered shape
37 functions as a source signal line, and is connected to a source region 615 c of the pixel TFT 604 by a source wiring 564.

Note that the entire channel forming regions 614a and 614b of the pixel TFT 604 overlap the shielding film 502.

The gate electrode 624 of the pixel TFT 604 intersects the semiconductor layer 508 thereunder via the gate insulating film 570, and extends over a plurality of semiconductor layers to serve also as a gate signal line. The storage capacitor 605 is a pixel TFT 60
4 is formed in a region where the upper layer capacitor wiring 625 overlaps with the semiconductor layer extending from the drain region 617 and the gate insulating film 570 therebetween. In this structure, an impurity element for controlling valence electrons is not added to the semiconductor layer 618 as a capacitor wiring.

With the above-described configuration, it is possible to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel TFT and the driving circuit, and to improve the operation performance and reliability of the semiconductor device. . Further, the gate electrode is formed of a conductive material having heat resistance, thereby facilitating activation of the LDD region, the source region, and the drain region. Further, when forming the LDD region overlapping with the gate electrode via the gate insulating film, the LDD region is formed by giving a concentration gradient to the impurity element added for the purpose of controlling the conductivity type, particularly in the vicinity of the drain region. Can be expected to increase the electric field relaxation effect.

Whether the TFT gate electrode has a single-gate structure or a multi-gate structure in which a plurality of gate electrodes are provided between a pair of source and drain is determined by the practitioner according to the characteristics of the circuit. Just choose.

Next, as shown in FIG.
A spacer made of a columnar spacer is formed on the active matrix substrate in the state shown in FIG. The spacer may be provided by scattering particles of several μm, but here, a method of forming a resin film on the entire surface of the substrate and then patterning the resin film is adopted. Although there is no limitation on the material of such a spacer, for example, NN700 manufactured by JSR Co., Ltd. is applied by a spinner, and then formed into a predetermined pattern by exposure and development processing. Using a clean oven, etc.
Heat and cure at 150-200 ° C. The spacer manufactured in this way can have different shapes depending on the conditions of the exposure and development processing.However, preferably, the shape of the spacer is columnar and the top is flat, so that the opposing substrate is When combined, the mechanical strength of the liquid crystal panel can be secured. The shape is conical,
Although there is no particular limitation such as a pyramid shape, for example, when the shape is a cone, specifically, the height is 1.2 to 5 μm, the average radius is 5 to 7 μm, and the ratio of the average radius to the bottom radius is 1 Vs. 1.
5 is assumed. At this time, the taper angle of the side surface is set to ± 15 ° or less.

The arrangement of the spacers may be arbitrarily determined, but preferably, as shown in FIG. 12A, in the pixel portion, the columnar spacer is overlapped with the contact portion 631 of the pixel electrode 569 so as to cover that portion. 656 may be formed. Since the flatness of the contact portion 631 is impaired and the alignment of the liquid crystal is disturbed in this portion, the disclination is prevented by forming the columnar spacer 656 in such a manner that the contact portion 631 is filled with the resin for the spacer. can do. Further, spacers 655a to 655d are also formed on the TFT of the driving circuit. This spacer may be formed over the entire surface of the drive circuit section,
As illustrated in FIG. 12A, a source wiring and a drain wiring may be provided so as to cover them.

After that, an alignment film 657 is formed. Usually, a polyimide resin is used for the alignment film of the liquid crystal display element. After forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. The area not rubbed in the rubbing direction from the end of the columnar spacer 656 provided in the pixel portion was set to 2 μm or less. In the rubbing process, generation of static electricity often poses a problem, but the effect of protecting the TFT from static electricity can be obtained by the spacers 655a to 655d formed on the TFT of the driving circuit. Although not shown in the drawing, after forming the alignment film 657 first, the spacers 656 and 65 are formed.
5a to 655d may be formed.

On the opposing substrate 651 on the opposing side, a transparent conductive film 653 and an alignment film 654 are formed. Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached with a sealant 658. Sealant 6
Filler 58 is mixed with a filler (not shown), and the two substrates are bonded together at a uniform interval by the filler and spacers 656 and 655a to 655d.
After that, a liquid crystal material 659 is injected between the two substrates. A known liquid crystal material may be used as the liquid crystal material. For example, TN
In addition to the liquid crystal, a thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response in which the transmittance changes continuously with an electric field can be used. Some of the thresholdless antiferroelectric mixed liquid crystals exhibit a V-shaped electro-optical response characteristic.
Thus, the active matrix type liquid crystal display shown in FIG. 12B is completed.

The present invention is not limited to the manufacturing method described in this embodiment. The active matrix type liquid crystal display of the present invention can be manufactured by using a known method.

This embodiment can be implemented by freely combining with Embodiment 3.

(Example 5)

[0158] In this embodiment, an example of a method for manufacturing a liquid crystal display of the present invention will be described with reference to FIGS.

First, referring to FIG. 16A, in this embodiment, a substrate 80 made of glass such as barium borosilicate glass or alumino borosilicate glass typified by Corning # 7059 glass or # 1737 glass.
0 is used. Note that the substrate 800 is not limited as long as it has a light-transmitting property, and a quartz substrate may be used.
Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

A shielding film 801 is formed on the surface of the substrate 800 where the TFT is to be formed. The shielding film 801 sets W to 0.1 μm
After forming to a thickness of 0.5 μm (0.2 μm in this embodiment), CF ₄ and Cl ₂ are mixed into an etching gas by using an ICP (Inductively Coupled Plasma) etching method, Plasma is generated by applying 500 W RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa. 100W on substrate side (sample stage)
(13.56 MHz), and a substantially negative self-bias voltage is applied.

In this embodiment, the shielding film 801 is formed using W, but the present invention is not limited to this configuration. In addition to W, it is possible to use a metal such as WSix, Cu, or Al, or a material in which a black pigment is mixed in silicon, silicon oxide, silicon oxynitride, or the like. In addition to the above materials,
Any material can be used as long as it has a light-shielding property and can withstand a processing temperature in a later process.

Next, the substrate 80 is covered so as to cover the shielding film 801.
An insulating film made of silicon oxide is formed on the substrate. The insulating film is
A silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be used. For example, SiH ₄ ,
A silicon oxynitride film made of NH ₃ and N ₂ O
800 nm (preferably 300-500 nm), as well as Si
A silicon oxynitride hydride film formed from H ₄ and N ₂ O
It may be formed by laminating to a thickness of 0 to 800 nm (preferably 300 to 500 nm). Here, the insulating film made of silicon oxide has a single-layer structure and a thickness of 0.5 to 1.5 μm. Note that the material of the insulating film is not limited to silicon oxide.

Next, the planarizing insulating film 802 is formed by polishing the insulating film by the CMP method. The CMP method can be performed by a known method. In the polishing of an oxide film, a slurry of a solid-liquid dispersion system in which an abrasive having a diameter of 100 to 1000 nm is dispersed in an aqueous solution containing a reagent such as a pH adjuster is generally used. In this embodiment, a silica slurry (pH = 10 to 11) in which 20 wt% of fumed silica particles obtained by thermally decomposing silicon chloride gas are dispersed in an aqueous solution to which potassium hydroxide is added.

After the formation of the planarizing insulating film 802, semiconductor layers 803 to 806 are formed on the planarizing insulating film 802. The semiconductor layers 803 to 806 are formed by forming a semiconductor film having an amorphous structure by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like), and then performing a known crystallization treatment (a laser crystallization method, a thermal crystallization method, or the like). A crystalline semiconductor film obtained by performing a crystallization method or a thermal crystallization method using a catalyst such as nickel) is patterned and formed into a desired shape. The semiconductor layers 803 to 806 have a thickness of 25 to 80 nm (preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably silicon or silicon germanium (Si _x Ge _1-x (X = 0.0001-
0.02)) It is good to form with an alloy etc. In this embodiment, after a 55 nm amorphous silicon film is formed by using the plasma CVD method, a solution containing nickel is held on the amorphous silicon film. Dehydrogenation (500 ° C.,
1 hour), thermal crystallization (550 ° C., 4 hours) was performed, and further, a laser annealing process for improving crystallization was performed to form a crystalline silicon film. Then, semiconductor layers 803 to 806 were formed by patterning the crystalline silicon film using a photolithography method.

After the formation of the semiconductor layers 803 to 806, a slight amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.

In the case where a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 300 Hz, and the laser energy density is set to 100 to 4.
(Typically ^{200~300mJ / cm 2) 00mJ / cm} 2 to.
When a YAG laser is used, it is preferable that the second harmonic is used, the pulse oscillation frequency is 30 to 300 kHz, and the laser energy density is 300 to 600 mJ / cm ² (typically 350 to 500 mJ / cm ² ). And width 10
A laser beam condensed linearly at 0 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is 50 to
What is necessary is just 98%.

Next, a gate insulating film 807 covering the semiconductor layers 803 to 806 is formed. The gate insulating film 807 is formed by a plasma CVD method or a sputtering method and has a thickness of 40 to
The insulating film containing silicon is formed to have a thickness of 150 nm. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N =
7%, H = 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) is formed by a plasma CVD method.
And O ₂ , a reaction pressure of 40 Pa and a substrate temperature of 300 to
400 ° C., high frequency (13.56 MHz) power density 0.
It can be formed by discharging at 5 to 0.8 W / cm ² .
The silicon oxide film thus manufactured is thereafter
Good characteristics as a gate insulating film can be obtained by thermal annealing at up to 500 ° C.

Then, as shown in FIG. 16A, a first conductive film 808a having a thickness of 20 to 100 nm and a second conductive film 808b having a thickness of 100 to 400 nm are stacked over the gate insulating film 807. Formed. In this embodiment, the film thickness 3
A first conductive film 808a made of a TaN film with a thickness of 0 nm and a second conductive film 808b made of a W film with a thickness of 370 nm were stacked. The TaN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen.
The W film was formed by a sputtering method using a W target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to reduce the resistance in order to use it as a gate electrode, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Therefore, in this embodiment, high-purity W (purity 99.99999) is used.
%), A resistivity of 9 to 20 μΩcm can be achieved by forming a W film with sufficient care so that no impurities are mixed in the gas phase during film formation by a sputtering method using a target of (%). Was.

In this embodiment, the first conductive film 808 is used.
a is TaN, and the second conductive film 808b is W. However, there is no particular limitation, and any of Ta, W, Ti, Mo, Al, C
It may be formed of an element selected from u, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Also, A
A gPdCu alloy may be used. The first conductive film is formed of a tantalum (Ta) film, the second conductive film is formed of a W film, and the first conductive film is formed of a titanium nitride (TiN) film. As a W film, the first
The first conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is formed of a tantalum nitride (TaN) film. May be combined.

Next, a mask 809 made of resist is formed by photolithography, and a first etching process for forming electrodes and wirings is performed (FIG. 16).
(B)). The first etching process is performed under the first and second etching conditions. In this embodiment, as the first etching condition, an ICP (Inductively Coupled Plasma) etching method is used, CF ₄ , Cl _2, and O ₂ are used as etching gases, and the respective gas flow ratios are 25. / 25/10 (sccm), 500 W of RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used.
150W RF (13.56MH) also on the substrate side (sample stage)
z) Turn on the power and apply a substantially negative self-bias voltage. The W film is etched under the first etching conditions to make the end of the first conductive layer tapered. The etching rate for W under the first etching condition is 2
The etching rate with respect to TaN is 80.32 nm / min.
Is about 2.5. Further, the taper angle of W is about 26 ° under the first etching condition.

Thereafter, the second etching condition was changed without removing the resist mask 809, CF ₄ and Cl ₂ were used as etching gases, and the respective gas flow ratios were set to 30/30 (sccm). A 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma, and etching was performed for about 30 seconds. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Second
The etching rate for W under the etching conditions of
The etching rate for 8.97 nm / min and TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, 10
It is preferable to increase the etching time by about 20%.

In the first etching process, the shape of the resist mask 809 is made appropriate, and the first etching process is performed by the effect of the bias voltage applied to the substrate side.
End portions of the conductive layer and the second conductive layer are tapered. The angle of the tapered portion may be 15 to 45 degrees. Thus, the first shape conductive layer 810 including the first conductive layer and the second conductive layer by the first etching process.
813 (first conductive layers 810a to 813a and second conductive layers 810b to 813b) are formed. Reference numeral 814 denotes a gate insulating film, and a region which is not covered with the first shape conductive layers 810 to 813 is etched by about 20 to 50 nm to form a thinned region.

Next, a second etching process is performed without removing the resist mask (FIG. 16C). Here, CF ₄ , Cl _2, and O ₂ are used as etching gases, and the respective gas flow ratios are 25/25/10 (scc
m) and 500 W of R on the coil-type electrode at a pressure of 1 Pa
F (13.56 MHz) power was applied to generate plasma to perform etching. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. The etching rate for W in the second etching process is 124.62 nm / min, and Ta is
The etching rate for N is 20.67 nm / min, and the selectivity ratio of W to TaN is 6.05. Therefore, the W film is selectively etched. The taper angle of W became 70 ° by the second etching. The second conductive layers 816b to 816b to 816b
19b is formed. On the other hand, the first conductive layers 810a to 810a
3a is hardly etched and the first conductive layer 81
6a to 819a are formed. Reference numeral 820 denotes a gate insulating film, and a region which is not covered with the first shape conductive layers 816 to 819 is etched by about 20 to 50 nm to form a thinned region.

First conductive layer 816a and second conductive layer 81
6b serves as a gate electrode of an n-channel TFT of a driver circuit formed in a later step, and an electrode formed of the first conductive layer 817a and the second conductive layer 817b is It becomes the gate electrode of the p-channel TFT of the drive circuit formed in the step. Similarly, the first conductive layer 81
The electrode formed by the second conductive layer 818a and the second conductive layer 818b serves as a gate electrode of an n-channel TFT of a pixel portion formed in a later step.
The electrode formed with the electrode 19b serves as one electrode (capacitance wiring) of the storage capacitor of the pixel portion formed in a later step.

Next, a first doping process is performed to obtain a state shown in FIG. Doping is performed on the second conductive layer 8
Using the masks 16b to 819b as masks for the impurity elements, the semiconductor layers below the tapered portions of the first conductive layers 816a to 819a are doped so that the impurity elements are added. In this example, P (phosphorus) was used as an impurity element, and plasma doping was performed at a dose of 3.5 × 10 ¹² and an acceleration voltage of 90 keV. Thus, low-concentration impurity regions 822a to 825a which do not overlap with the first conductive layer and low-concentration impurity regions 822b to 825 which overlap with the first conductive layer
b is formed in a self-aligned manner. Low concentration impurity region 822b
The concentration of phosphorus (P) added to ８825b was 1 × 10
^{It is 17} to 1 × 10 ¹⁸ atoms / cm ³ , and has a gradual concentration gradient according to the thickness of the tapered portions of the first conductive layers 816a to 819a. Note that the first conductive layer 816a
Although the impurity concentration in the semiconductor layer overlapping with the tapered portion of the first conductive layers 816a to 819a is slightly reduced inward from the end of the tapered portion of the first conductive layers 816a to 819a, they are substantially the same.

Then, a resist mask 826 is formed, a second doping process is performed, and an impurity element imparting n-type is added to the semiconductor layer (FIG. 17B). The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 ×
10 ^{13 to} 5 × 10 ¹⁵ atoms / cm ² and acceleration voltage of 60 to
It is performed at 100 keV. In this embodiment, the dose is set to 1.
The test was performed at 5 × 10 ¹⁵ atoms / cm ² and an acceleration voltage of 80 keV. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the conductive layers 816 to 819 serve as a mask for the impurity element imparting n-type, and the self-aligned high-concentration impurity regions 827
a to 830a, low-concentration impurity regions 827b to 830b that do not overlap with the first conductive layer, and low-concentration impurity regions 827c to 830c that overlap with the first conductive layer are formed. The high-concentration impurity regions 827a to 830a have 1 × 10 ²⁰ to 1 × 10
^An n-type impurity element is added in a concentration range of ²¹ atoms / cm ³ .

It is not necessary to dope the semiconductor film on which the p-channel TFT is formed with the n-type impurity by the second doping treatment shown in FIG. , 806 may be formed so as to cover the entirety, so that n-type impurities are not doped. Conversely, a mask 826 is formed on the semiconductor layers 804 and 8
Alternatively, the polarity of the semiconductor layer may be inverted to p-type in the third doping process without being provided over the semiconductor layer 06.

Next, after removing the resist mask 826, a new resist mask 831 is formed and a third doping process is performed. By the third doping process, the semiconductor layer serving as the active layer of the p-channel TFT has a conductivity type (p-type) opposite to the one conductivity type (n-type).
Region 732 to which an impurity element imparting
833 are formed (FIG. 17C). First conductive layer 81
7, 819 are used as masks for impurity elements, and p
An impurity element for imparting a mold is added to form an impurity region in a self-aligned manner. In this embodiment, the impurity regions 832 and 8
33 is formed by ion doping using diborane (B ₂ H ₆ ). In the third doping process, n
The semiconductor layer forming the channel type TFT is covered with a mask 831 made of resist. By the first doping process and the second doping process, the impurity region 832
Phosphorus is added to each of b and 832c at a different concentration, and the concentration of the impurity element imparting p-type is 2 × 10 ²⁰ to 2 × 10 ²¹ atoms / cm ^{3 in} any of the regions.
By performing the doping process so as to function as described above, no problem occurs because the p-channel TFT functions as a source region and a drain region.

Through the above steps, impurity regions are formed in the respective semiconductor layers.

Next, the mask 831 made of a resist is removed to form a first interlayer insulating film 835. This first
The interlayer insulating film 835 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by a plasma CVD method or a sputtering method. In this embodiment, the plasma C
A 150 nm-thick silicon oxynitride film was formed by a VD method. Needless to say, the first interlayer insulating film 835 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 18A, the impurity element added to each semiconductor layer is activated. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, 400 to 700 ° C, typically 500 to 550 ° C.
In this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In this embodiment, at the same time as the above activation treatment, nickel used as a catalyst during crystallization is doped with impurity regions (827a, 829a, 83a) containing a high concentration of phosphorus.
2a, 833a), the nickel concentration in the semiconductor layer mainly serving as a channel formation region is reduced.
TF having channel forming region manufactured in this manner
T has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and good characteristics can be achieved.

Further, an activation process may be performed before forming the first interlayer insulating film 835. However, when the wiring material used is weak to heat, an active layer is formed after an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring and the like as in this embodiment. It is preferable to carry out a chemical treatment.

Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the semiconductor layer. In this embodiment, heat treatment was performed at 410 ° C. for one hour in a nitrogen atmosphere containing about 3% of hydrogen. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

In the case where a laser annealing method is used as the activation treatment, it is preferable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the above hydrogenation.

Next, a second interlayer insulating film 836 made of an organic insulating material is formed on the first interlayer insulating film 835. In this embodiment, an acrylic resin film having a thickness of 1.6 μm was formed. Next, each impurity region 827a, 829a, 8
Patterning is performed to form contact holes reaching 32a and 833a.

Then, in the driver circuit 905, electrodes 840 to 843 electrically connected to the impurity regions 827a and 832a are formed. These electrodes are composed of a 50 nm thick Ti film and a 500 nm thick film.
A multilayer film of an m alloy film (an alloy film of Al and Ti) is formed by patterning.

[0189] In the pixel portion 906, a connection wiring 845 or a source signal line 844 in contact with the impurity region 829a is formed, and a connection wiring 846 in contact with the impurity region 833a is formed.

Next, a transparent conductive film is further formed on the transparent conductive film.
A pixel electrode 847 is formed by forming a pattern with a thickness of 0 nm and patterning. (FIG. 18B) The transparent conductive film is made of an indium oxide-zinc oxide alloy (In ₂ O ₃ —Zn).
O) and zinc oxide (ZnO) are also suitable materials, and gallium (G) is used to further increase the transmittance and conductivity of visible light.
Zinc oxide (ZnO: Ga) to which a) is added can be suitably used.

The pixel electrode 847 is connected to the connection wiring 845.
And an electrical connection is formed with the drain region of the pixel TFT, and further an electrical connection is formed with the semiconductor layer (impurity region 833a) functioning as one electrode forming a storage capacitor. You.

Here, the pixel electrode 845 is
Although an example using a transparent conductive film is described, a reflective liquid crystal display can be manufactured by forming a pixel electrode using a conductive material having reflectivity. In that case, a pixel electrode can be formed at the same time as the step of manufacturing the electrode, and the material of the pixel electrode is a film containing Al or Ag as a main component,
Alternatively, it is desirable to use a material having excellent reflectivity such as a laminated film thereof.

As described above, the n-channel TFT 90
Drive circuit 90 having one and p-channel TFT 902
5 and a pixel portion 906 having a pixel TFT 903 and a storage capacitor 904 can be formed over the same substrate.

N-channel TFT 90 of drive circuit 905
Reference numeral 1 denotes a low-concentration impurity region 8 overlapping with a channel formation region 850 and a first conductive layer 816a forming a part of a gate electrode.
27C (GOLD region), a low concentration impurity region 827b (LDD region) formed outside the gate electrode, and a high concentration impurity region 827a functioning as a source region or a drain region. The p-channel TFT 902 functions as a channel formation region 851, an impurity region 832c overlapping with the first conductive layer 817a forming part of the gate electrode, an impurity region 832b formed outside the gate electrode, and a source region or a drain region. Impurity region 8
32a.

In the pixel TFT 903 of the pixel portion 906, a channel forming region 852 and a low-concentration impurity region 829c (GOL) overlapping the first conductive layer 818a forming a gate electrode are provided.
D region), a low concentration impurity region 829b (LDD region) formed outside the gate electrode, and a high concentration impurity region 829a functioning as a source region or a drain region. Further, the semiconductor layers 833a to 833c which are part of the capacitor wiring which is one electrode of the storage capacitor 904 are each doped with an impurity element imparting p-type. The storage capacitor 904 is formed by using the gate insulating film 820 as a dielectric.
The electrode 819 and the semiconductor layers 833a to 833c and 853 are formed.

The shielding film 801 overlaps the entire channel forming region 852 of the pixel TFT 903.

Next, an alignment film 855 is formed and a rubbing process is performed. In this embodiment, before forming the alignment film 855, a columnar spacer for maintaining a substrate interval was formed at a desired position by patterning an organic resin film such as an acrylic resin film. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 856 is prepared. The opposite substrate is provided with a color filter in which a coloring layer 858 is arranged corresponding to each pixel. Next, a flattening film 859 covering this color filter was provided. Next, a counter electrode 857 made of a transparent conductive film was formed in the pixel portion 906 over the planarization film 859, an alignment film 860 was formed over the entire surface of the counter substrate, and rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion 906 and the driver circuit 905 are formed and the counter substrate are bonded with a sealant 861. A filler is mixed in the sealing material 861, and the two substrates are bonded to each other at a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 862 is injected between the two substrates, and completely sealed with a sealant (not shown). Liquid crystal material 8
A well-known liquid crystal material may be used for 62. Thus, the active matrix type liquid crystal display shown in FIG. 19 is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a desired shape. Further, a polarizing plate and the like were appropriately provided using a known technique. Then, an FPC was attached using a known technique.

This embodiment can be implemented in combination with the third embodiment.

(Embodiment 6) In this embodiment, an example of a sectional view of a liquid crystal display having the structure of the present invention will be described.

FIG. 20 is a sectional view of a liquid crystal display having the structure of the present invention. Active matrix substrate 60
01, a shielding film 148 having silicon oxide and a black pigment is formed. And the active matrix substrate 60
A planarizing insulating film 6002 is formed on the first insulating film 01 so as to cover the shielding film 148.

[0203] On the planarization insulating film 6002, the driver circuit 6201 includes a p-channel TFT 6101 and a first n-type TFT 6101.
Channel type TFT 6102, second n-channel type TFT
6103, a pixel TFT 6104 and a storage capacitor 6 in the pixel portion.
105 is formed.

In the p-channel TFT 6101 of the driver circuit, the channel formation region 126, the source regions 127a and 127b, and the drain regions 128a and 1281 are formed in the semiconductor layer 6004.
28b. First n-channel TFT 610
2 includes a channel formation region 129 in the semiconductor layer 6005;
An LDD region 130 overlapping with the gate electrode 6071 (such an LDD region is referred to as Lov), a source region 131, and a drain region 132 are provided. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.
0 to 1.5 μm. Second n-channel TFT 61
03, the channel formation region 13 is formed in the semiconductor layer 6006.
3. It has LDD regions 134 and 135, a source region 136, and a drain region 137. This LDD region is Lov
An LDD region that does not overlap with the gate electrode 6072 (such an LDD region is referred to as Loff) is formed, and the length of the Loff region in the channel length direction is 0.3 to 2.0.
μm, preferably 0.5 to 1.5 μm. Pixel TF
In T6104, the semiconductor layer 6007 includes channel formation regions 138 and 139, Loff regions 140 to 143, and source or drain regions 144 to 146. Loff
The length of the region in the channel length direction is 0.5 to 3.0 μm, preferably 1.5 to 2.5 μm. Also, pixel TFT
6104, the channel forming regions 138 and 139 and the pixel TF
An offset region (not shown) is formed between the T LDD regions and the Loff regions 140 to 143.
Further, the upper capacitor wiring 6074 and the gate insulating film 602
0 and a semiconductor layer 147 (capacitance wiring) connected to the drain region 146 of the pixel TFT 6104 and to which an impurity element imparting n-type is added.
5 are formed. In FIG. 20, the pixel TFT 6104 has a double gate structure, but may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

The shielding film 148 overlaps the entire channel forming regions 138 and 139 of the pixel TFT 6104.

With the above configuration, the TFTs constituting each circuit according to the specifications required by the pixel TFT and the driver
Can be optimized to improve the operation performance and reliability of the liquid crystal display.

Reference numeral 6060 denotes a pixel electrode.
The drain region 146 is electrically connected to the drain region 146. Reference numeral 6061 denotes an alignment film. 6062 is a counter substrate, 6063 is a counter electrode, 6064 is an alignment film, 6065
Is a liquid crystal. The liquid crystal display shown in FIG. 20 is a reflection type liquid crystal display.

In this embodiment, the reflection type liquid crystal display performs display in the TN (twist) mode. Therefore, a polarizing plate (not shown) is disposed above the reflective liquid crystal display.

[0209] This embodiment can be implemented in combination with the third embodiment.

(Embodiment 7) A liquid crystal display formed by carrying out the present invention can be used for display portions of various electronic devices. Such electronic devices include video cameras, digital cameras, projectors (rear or front type), head mounted displays (goggle type displays), game consoles, car navigation systems, personal computers, and personal digital assistants (mobile computers, mobile phones). Or an electronic book).
Examples of these are shown in FIG. 13, FIG. 14 and FIG.

FIG. 13A shows a personal computer, which includes a main body 7001, a video input section 7002, and a display section 70.
03, a keyboard 7004. The present invention can be applied to the video input unit 7002 and the display unit 7003.

FIG. 13B shows a video camera, which includes a main body 7101, a display portion 7102, an audio input portion 7103, operation switches 7104, a battery 7105, and an image receiving portion 710.
6. The invention can be applied to the display portion 7102.

FIG. 13C shows a mobile computer (mobile computer), which comprises a main body 7201, a camera section 7202, an image receiving section 7203, operation switches 7204, and a display section 7205. The invention can be applied to the display portion 7205.

FIG. 13D shows a goggle type display having a main body 7301, a display portion 7302, and an arm portion 730.
3 The present invention can be applied to the display portion 7302.

FIG. 13E shows a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium), and includes a main body 7401, a display portion 7402, and a speaker portion 740.
3, a recording medium 7404, and operation switches 7405. This apparatus uses a DVD (Dig) as a recording medium.
It is possible to enjoy listening to music, watching movies, playing games, and using the Internet using an IT (Versatile Disc), CD, or the like. The invention can be applied to the display portion 7402.

FIG. 13F shows a digital camera, which includes a main body 7501, a display portion (A) 7502, an eyepiece portion 7503,
An operation switch 7504, a display portion (B) 7505, and a battery 7506 are included. The electronic device of the present invention can be used for the display portion (A) 7502 and the display portion (B) 7505. In the case where the display portion (B) 7505 is mainly used as an operation panel, power consumption can be suppressed by displaying white characters on a black background.

FIG. 14A shows a front type projector, which includes a light source optical system, a display portion 7601 and a screen 7.
602. The present invention can be applied to the display portion 7601.

FIG. 14B shows a rear projector, which comprises a main body 7701, a light source optical system and a display portion 7702, a mirror 7703, a mirror 7704, and a screen 7705. The present invention can be applied to the display portion 7702.

Note that FIG. 14C shows the light source optical system and the display portion 760 in FIGS. 14A and 14B.
1 is a diagram showing an example of the structure of 7702. FIG. The light source optical system and the display units 7601 and 7702 are provided with a light source optical system 780.
1, mirrors 7802, 7804 to 7806, dichroic mirror 7803, optical system 7807, display unit 780
8, a phase difference plate 7809, and a projection optical system 7810. The projection optical system 7810 includes a plurality of optical lenses provided with a projection lens. This configuration corresponds to the display unit 7808
It is called a three-plate system because three are used. Also,
In the optical path indicated by the arrow in FIG. 14C, the practitioner may appropriately provide an optical lens, a film having a polarizing function, a film for adjusting a phase difference, an IR film, or the like.

FIG. 14D is a diagram showing an example of the structure of the light source optical system 7801 in FIG. 14C. In the present embodiment, the light source optical system 7801 includes a reflector 7811, a light source 7812, and lens arrays 7813 and 7813.
814, a polarization conversion element 7815, and a condenser lens 7816. Note that the light source optical system shown in FIG. 14D is an example, and is not limited to this structure. For example, a practitioner may appropriately provide an optical lens, a film having a polarizing function, a film for adjusting a phase difference, an IR film, or the like to the light source optical system.

FIG. 14 (C) shows an example of a three-plate type, while FIG. 15 (A) shows an example of a single-plate type. FIG.
The light source optical system and the display unit shown in FIG.
901, a display unit 7902, a projection optical system 7903, and a phase difference plate 7904. The projection optical system 7903 includes a plurality of optical lenses provided with a projection lens. FIG.
The light source optical system and the display unit shown in FIG. 14A are the light source optical system and the display unit 760 in FIGS. 14A and 14B.
1, 7702. Also, a light source optical system 7901
May use the light source optical system shown in FIG. Note that the display portion 7902 is provided with a color filter (not shown) to colorize a display image.

The light source optical system and the display section shown in FIG. 15B are an application example of FIG. 15A. Instead of providing a color filter, an RGB rotating color filter disk 7905 is used. The display image is colorized.
The light source optical system and the display unit shown in FIG.
14A and 14B can be applied to the light source optical system and the display portions 7601 and 7702.

The light source optical system and the display section shown in FIG. 15C are called a color filterless single plate type. In this method, a microlens array 7915 is provided in a display portion 7916, and a dichroic mirror (green) 791 is provided.
2. Display images are colored using a dichroic mirror (red) 7913 and a dichroic mirror (blue) 7914. The projection optical system 7917 includes a plurality of optical lenses provided with a projection lens. The light source optical system and the display portion shown in FIG. 15C are shown in FIGS. 14A and 14B.
It can be applied to the light source optical system and the display units 7601 and 7702 in the inside. Further, as the light source optical system 7911, an optical system using a coupling lens and a collimator lens in addition to the light source may be used.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 6.

[0225]

According to the structure of the present invention, the surface of the insulating film can be flattened, and deterioration of the characteristics of the TFT formed on the insulating film can be suppressed. In addition, warping of the substrate due to the stress of the insulating film can be eliminated to some extent by polishing by the CMP method.

Further, TF from the active matrix substrate side
Since the light irradiated to T can be blocked by the blocking film, it is possible to prevent the off-current of the TFT from increasing due to the light. Further, since the shielding film is formed on the active matrix substrate side, it is possible to suppress the alignment margin when forming the shielding film, and it is possible to improve the aperture ratio.

Note that, in addition to the structure of the present invention in which a shielding film is provided between the active layer of the TFT and the substrate, a shielding film is formed above the TFT and the wiring via an interlayer insulating film, so that the active layer is formed. In particular, it becomes more reliable to prevent light from entering the channel formation region.

When forming a shielding film between the active matrix substrate and the active layer of the TFT, wiring may be formed simultaneously with the shielding film. When the wiring and the shielding film are formed of the same material, and the wiring is a gate signal line or a source signal line, disturbance (disclination) of an image due to a disorder in orientation of a liquid crystal material between pixels is observed. Can be prevented.

In addition to the structure of the present invention, a structure having a shielding film on the counter substrate side may be added.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an active matrix substrate of the present invention.

FIG. 2 is a top view of a pixel of the present invention.

FIG. 3 illustrates a method for manufacturing a liquid crystal display of the present invention.

FIG. 4 illustrates a method for manufacturing a liquid crystal display of the present invention.

FIG. 5 illustrates a method for manufacturing a liquid crystal display of the present invention.

FIG. 6 illustrates a method for manufacturing a liquid crystal display of the present invention.

FIG. 7 is a diagram of a CMP apparatus.

FIG. 8 is an enlarged view of a carrier.

FIG. 9 illustrates a method for manufacturing a liquid crystal display of the present invention.

FIG. 10 illustrates a method for manufacturing a liquid crystal display of the present invention.

FIG. 11 illustrates a method for manufacturing a liquid crystal display of the present invention.

FIG. 12 illustrates a method for manufacturing a liquid crystal display of the present invention.

FIG. 13 is a diagram of an electronic device using the liquid crystal display of the present invention.

FIG. 14 is a view of a projector using the liquid crystal display of the present invention.

FIG. 15 is a view of a projector using the liquid crystal display of the present invention.

FIG. 16 illustrates a method for manufacturing a liquid crystal display of the present invention.

FIG. 17 illustrates a method for manufacturing a liquid crystal display of the present invention.

FIG. 18 illustrates a method for manufacturing a liquid crystal display of the present invention.

FIG. 19 illustrates a method for manufacturing a liquid crystal display of the present invention.

FIG. 20 is a cross-sectional view of the liquid crystal display of the present invention.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/78 626C 627A F-term (Reference) 2H092 JA24 JA46 JB56 JB58 JB64 KB25 MA08 MA14 MA19 MA22 MA27 MA30 NA04 NA24 PA08 RA10 5C094 AA10 AA13 AA25 AA32 AA42 AA43 AA48 BA03 BA43 CA19 DA09 DA13 DB01 DB04 EA04 EA05 EA10 EB02 ED15 FA01 FA02 FB12 FB14 FB15 GB10 HA06 HA08 HA10 JA08 5F110 AA06 AA14 AA18 DD13 DD02 DD02 EE02 EE03 EE04 EE06 EE08 EE09 EE14 EE15 EE23 EE28 EE44 EE45 FF02 FF04 FF09 FF28 FF30 FF36 GG01 GG02 GG13 GG25 GG28 GG32 GG34 GG43 GG45 GG47 GG51 GG52 HJ01 HJ04 HJ07 HJ12 HJ13 HJ18 HJ23 HL03 HL04 HL07 HL12 HL22 HL23 HM15 NN03 NN04 NN22 NN23 NN24 NN27 NN34 NN35 NN36 NN45 NN46 NN48 NN58 NN73 PP01 PP02 PP03 PP06 PP34 PP35 QQ04 QQ11 QQ19 QQ24 QQ2 5 QQ28

Claims (29)

[Claims] A shielding film formed on the insulating surface, a planarizing insulating film formed on the insulating surface to cover the shielding film, and a semiconductor layer formed in contact with the planarizing insulating film. ,
Wherein the shielding film overlaps the semiconductor layer with the planarizing insulating film interposed therebetween, and the planarizing insulating film has a CM before the semiconductor layer is formed.
A semiconductor device characterized by being polished by a P method. 2. A semiconductor device comprising: a shielding film formed on an insulating surface; a planarizing insulating film formed on the insulating surface to cover the shielding film; and an active layer formed in contact with the planarizing insulating film. Wherein the active layer has a channel forming region, and the shielding film overlaps the entire channel forming region with the planarizing insulating film interposed therebetween. Before the active layer is formed, the planarizing insulating film is subjected to CMP.
A semiconductor device characterized by being polished by a method. 3. The semiconductor device according to claim 1, wherein said shielding film has a thickness of 0.1 μm to 0.5 μm. 4. The semiconductor device according to claim 1, wherein the shielding film has a tapered edge portion. 5. A lower capacitance wiring formed on an insulating surface;
A semiconductor device comprising: a planarization insulating film formed on the insulating surface to cover the lower capacitance wiring; and a capacitance wiring formed in contact with the planarization insulation film, wherein the lower capacitance wiring is The planarization insulating film overlaps with the capacitor wiring with a flattening insulating film interposed therebetween.
A semiconductor device characterized by being polished by a P method. 6. The semiconductor device according to claim 5, wherein said lower-layer capacitor wiring has a thickness of 0.1 μm to 0.5 μm. 7. The semiconductor device according to claim 5, wherein an edge portion of said lower layer capacitor wiring is formed in a tapered shape. 8. A shielding film formed on an insulating surface, a lower-layer capacitor wiring and a lower-layer wiring, and a planarizing insulating film formed on the insulating surface to cover the shielding film, the lower-layer capacitor wiring and the lower-layer wiring. And a thin film transistor including an active layer formed in contact with the planarizing insulating film, and a capacitor wiring formed in contact with the planarizing insulating film, wherein the active layer forms a channel forming region. The shielding film overlaps with the entire channel formation region with the planarization insulating film interposed therebetween, and the lower layer capacitor wiring overlaps with the capacitance wiring with the planarization insulating film interposed therebetween. A gate electrode of the thin film transistor is electrically connected to the lower wiring; and the planarization insulating film is formed by CMP before the active layer is formed.
A semiconductor device characterized by being polished by a method. 9. The semiconductor device according to claim 8, wherein the thickness of the shielding film, the lower capacitor wiring, and the lower wiring is 0.1 μm to 0.5 μm.
μm. 10. The semiconductor device according to claim 8, wherein the shielding film, the lower layer capacitor wiring, or the lower layer wiring has a tapered edge portion. 11. The flattening insulating film according to claim 1, wherein the thickness of the flattening insulating film is 0.5 μm to 1.0 μm.
A semiconductor device having a thickness of 5 μm. 12. A digital camera comprising the semiconductor device according to claim 1. 13. A video camera comprising the semiconductor device according to claim 1. 14. A goggle type display device comprising the semiconductor device according to claim 1. 15. An audio reproducing apparatus comprising the semiconductor device according to claim 1. 16. A notebook personal computer having the semiconductor device according to claim 1. 17. A portable information terminal comprising the semiconductor device according to claim 1. 18. A DVD device comprising the semiconductor device according to claim 1. 19. A step of forming a shielding film in contact with an insulating surface, a step of forming an insulating film on the insulating surface covering the shielding film, and polishing the insulating film by a CMP method to form a planarized insulating film. Forming a semiconductor layer in contact with the planarization insulating film;
A method of manufacturing a semiconductor device, comprising: the shielding film overlaps with the semiconductor layer with the planarizing insulating film interposed therebetween. 20. A step of forming a shielding film in contact with an insulating surface, a step of forming an insulating film on the insulating surface covering the shielding film, and polishing the insulating film by a CMP method to form a planarized insulating film. Forming a thin film transistor including an active layer in contact with the planarization insulating film, a method for manufacturing a semiconductor device, wherein the active layer has a channel formation region, The method for manufacturing a semiconductor device, wherein the shielding film overlaps with the entire channel formation region with the planarization insulating film interposed therebetween. 21. The method according to claim 19, wherein
The method of manufacturing a semiconductor device, wherein the thickness of the shielding film is 0.1 μm to 0.5 μm. 22. One of claims 19 to 21.
3. The method for manufacturing a semiconductor device according to item 1, wherein the shielding film has an edge portion formed in a tapered shape. 23. A step of forming a lower-layer capacitor wiring in contact with an insulating surface; a step of forming an insulating film on the insulating surface so as to cover the lower-layer capacitor wiring; Forming a film; forming a capacitor wiring in contact with the planarization insulating film;
A method for manufacturing a semiconductor device, comprising: the lower capacitance wiring overlaps the capacitance wiring with the planarization insulating film interposed therebetween. 24. The method of manufacturing a semiconductor device according to claim 23, wherein the thickness of the lower capacitor wiring is 0.1 μm to 0.5 μm. 25. The method according to claim 23, wherein
A method for manufacturing a semiconductor device, wherein an edge portion of the lower layer capacitor wiring is formed in a tapered shape. 26. A step of forming a shielding film, a lower layer capacitor wiring and a lower layer wiring in contact with an insulating surface, and a step of forming an insulating film on the insulating surface to cover the shielding film, the lower layer capacitor wiring and the lower layer wiring A semiconductor device comprising: a step of polishing the insulating film by a CMP method to form a planarized insulating film; and a plurality of steps of forming a capacitor wiring and a thin film transistor including an active layer on the planarized insulating film. Wherein the active layer has a channel forming region, the shielding film overlaps the entire channel forming region with the planarizing insulating film interposed therebetween, and the lower layer capacitor wiring is A manufacturing method of a semiconductor device, wherein the capacitor wiring overlaps with the capacitor wiring with a planarization insulating film interposed therebetween, and a gate electrode included in the thin film transistor is electrically connected to the lower wiring. Method. 27. The semiconductor device according to claim 26, wherein the thickness of the shielding film, the lower capacitor wiring, and the lower wiring is 0.1 μm to
A method for manufacturing a semiconductor device, which is 0.5 μm. 28. The method according to claim 26, wherein
A method for manufacturing a semiconductor device, wherein an edge portion of the shielding film, the lower-layer capacitor wiring, or the lower-layer wiring is formed in a tapered shape. 29. The flattening insulating film according to claim 1, wherein the thickness of the flattening insulating film is 0.5 μm to 1.0 μm.
A method for manufacturing a semiconductor device, which is 5 μm.