WO2012096155A1 - Thin-film transistor substrate and method for manufacturing same - Google Patents

Thin-film transistor substrate and method for manufacturing same Download PDF

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Publication number
WO2012096155A1
WO2012096155A1 PCT/JP2012/000094 JP2012000094W WO2012096155A1 WO 2012096155 A1 WO2012096155 A1 WO 2012096155A1 JP 2012000094 W JP2012000094 W JP 2012000094W WO 2012096155 A1 WO2012096155 A1 WO 2012096155A1
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conductive layer
conductive
film
layer
provided
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PCT/JP2012/000094
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French (fr)
Japanese (ja)
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西村 直樹
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シャープ株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon
    • H01L29/458Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT

Abstract

A TFT substrate (30a) is provided with a plurality of TFTs (5a) which are provided with: a semiconductor layer (15) having a channel region (C); a gate electrode (13a) disposed so as to be superimposed on the channel region (C) and provided such that a gate insulating film (14) intervenes between the gate electrode (13a) and the semiconductor layer (15); and a source electrode (18a) and a drain electrode (18b) each provided discretely from the other and each connected to a respective outside side of the channel region (C) of the semiconductor layer (15). At least one of the gate electrode (13a), source electrode (18a), or drain electrode (18b) has a first conductor layer (11a) and a copper second conductor layer (12a) provided on the first conductor layer (11a). The film thickness of the first conductor layer (11a) is provided such that the surface of the second conductor layer (12a) is flat.

Description

Thin film transistor substrate and manufacturing method thereof

The present invention relates to a thin film transistor substrate and a manufacturing method thereof, and more particularly to a thin film transistor substrate using copper wiring and a manufacturing method thereof.

A thin film transistor (hereinafter also referred to as “TFT”) substrate that constitutes a display panel such as a liquid crystal display panel includes a plurality of gate lines provided to extend in parallel to each other and in a direction perpendicular to each gate line. Display wirings such as a plurality of source lines provided so as to extend in parallel are provided. In recent years, a wiring structure using a copper wiring having a lower electrical resistance than a conventional aluminum wiring has been proposed for the TFT substrate as in the case of semiconductor devices.

For example, Patent Document 1 includes a second metal of an easily oxidizable metal mainly composed of at least one kind of Ag, Au, Cu, Al, and Pt and typified by Ti, Zr, Hf, and Al. A liquid crystal display device having a wiring layer formed by coating the surface of an added conductive layer with an oxide layer of a second metal is disclosed.

Japanese Patent Laid-Open No. 10-153788

By the way, for example, in a TFT substrate using a display wiring having a laminated structure in which a lower layer is a titanium layer and an upper layer is a copper layer, an end portion of the copper layer is easily formed so that the protruding portion is Due to the origin of ESD (electrostatic discharge) that may occur during the manufacturing process, there is a risk that elements such as TFTs may be destroyed or the display wiring may be short-circuited with other display wiring. .

The present invention has been made in view of such points, and an object thereof is to suppress the formation of protrusions in a copper conductive layer.

In order to achieve the above object, according to the present invention, the surface of the second conductive layer made of copper is made flat according to the film thickness of the first conductive layer.

Specifically, a thin film transistor substrate according to the present invention is separated from a semiconductor layer having a channel region, and a gate electrode provided in the semiconductor layer with a gate insulating film interposed therebetween so as to overlap the channel region. A thin film transistor substrate provided with a plurality of thin film transistors each including a source electrode and a drain electrode connected to both outer sides of the channel region of the semiconductor layer, wherein at least one of the gate electrode, the source electrode, and the drain electrode One has a first conductive layer and a second conductive layer made of copper provided on the first conductive layer, and the film thickness of the first conductive layer is flat on the surface of the second conductive layer. It is set to become.

According to the above configuration, at least one of the gate electrode, the source electrode, and the drain electrode has a stacked structure of the first conductive layer and the second conductive layer made of copper, and the surface of the second conductive layer is flattened. Since the film thickness of the first conductive layer is set, when the first conductive layer and the second conductive layer are formed, the second conductive film serving as the second conductive layer and the resist pattern formed thereon are adhered to each other. Will be improved. For this reason, the etchant is unlikely to enter between the second conductive film and the resist pattern, so that the oxidation of the end portion of the second conductive layer due to the etchant remaining below the resist pattern is suppressed. Thereby, since formation of the protrusion resulting from oxidation is suppressed in the edge part of a 2nd conductive layer, formation of the protrusion part in a copper-made conductive layer is suppressed.

On the other hand, as shown in FIG. 6A, when the film thickness of the first conductive film 111 to be the first conductive layer 111a is, for example, 350 mm, the second conductive layer to be the second conductive layer 112a. Since the surface of the conductive film 112 is easily formed in an uneven shape, the etching solution E remains between the resist pattern R and the second conductive layer 112a after the wet etching, as shown in FIG. 6B. . Then, as shown in FIG. 6C, the end surface of the second conductive layer 112a is oxidized to form an oxide film X, and as shown in FIG. The oxide film X grows, and the protrusion P is formed. After that, the pressure resistance of the insulating film 114 formed so as to cover the first conductive layer 111a and the second conductive layer 112a is lowered. Here, when the film thickness of the first conductive film 111 is relatively large, distortion occurs at the interface between the first conductive film 111 and the second conductive film 112 having different crystal structures (crystal lattices), and the distortion occurs. When the surface of the second conductive film 112 is easily formed in an uneven shape due to the above, and the film thickness of the first conductive film 111 is relatively small, the first conductive film 111 and the second conductive film 112 described above. It is presumed that the strain at the interface becomes small and the surface of the second conductive layer 112 is easily formed flat.

The film thickness of the first conductive layer may be 50 mm or more and 150 mm or less.

According to the above configuration, since the thickness of the first conductive layer is not less than 50 mm and not more than 150 mm, the surface of the second conductive layer is specifically flattened. Here, when the film thickness of the first conductive layer is smaller than 50 mm, the adhesion between the second conductive layer and the underlayer is excessively lowered, and the film thickness of the first conductive layer is larger than 150 mm. In this case, the surface of the second conductive layer is formed in an uneven shape.

The first conductive layer may be configured to improve adhesion between the second conductive layer and the base layer.

According to said structure, since the 1st conductive layer is comprised so that the adhesiveness of a 2nd conductive layer and a base layer may be improved, it is made from copper which comprises at least 1 of a gate electrode, a source electrode, and a drain electrode The second conductive layer is prevented from peeling off.

The first conductive layer may be made of titanium.

According to the above configuration, since the first conductive layer is made of titanium, the adhesion between the second conductive layer made of copper and the underlying layer (for example, a silicon-based material such as a glass substrate, a semiconductor layer, or a gate insulating film) is improved. Specifically improve.

The method for manufacturing a thin film transistor substrate according to the present invention includes a semiconductor layer having a channel region, and a gate electrode provided on the semiconductor layer with a gate insulating film interposed therebetween so as to overlap the channel region. A thin film transistor substrate provided with a plurality of thin film transistors each including a source electrode and a drain electrode connected to both outer sides of the channel region of the semiconductor layer, wherein the substrate includes a first conductive layer. A conductive film forming step of forming a second conductive film made of copper on the first conductive film so that the surface is flattened by the film thickness of the first conductive film after forming the film with a predetermined film thickness And after forming a resist pattern on the second conductive film, a second conductive film exposed from the resist pattern, and a first conductive film disposed below the second conductive film. At least one of the gate electrode, the source electrode, and the drain electrode is formed by removing by etching to form a first conductive layer from the first conductive film and forming a second conductive layer from the second conductive film. And an etching process for forming the two.

According to the above method, at least one of the gate electrode, the source electrode, and the drain electrode has a laminated structure of the first conductive layer and the second conductive layer made of copper. Since the surface of the second transparent conductive film to be the second conductive layer is flattened by the film thickness of the first conductive film, the first conductive layer and the second conductive layer are formed in the etching process. The adhesion between the second conductive film and the resist pattern formed thereon is improved. Therefore, in the etching process, the etchant is difficult to enter between the second conductive film and the resist pattern, so that oxidation of the end portion of the second conductive layer due to the etchant remaining below the resist pattern is suppressed. . Thereby, since formation of the protrusion resulting from oxidation is suppressed in the edge part of a 2nd conductive layer, formation of the protrusion part in a copper-made conductive layer is suppressed.

On the other hand, as shown in FIG. 6A, when the film thickness of the first conductive film 111 to be the first conductive layer 111a is, for example, 350 mm, the second conductive layer to be the second conductive layer 112a. Since the surface of the conductive film 112 is easily formed in an uneven shape, the etching solution E remains between the resist pattern R and the second conductive layer 112a after the wet etching, as shown in FIG. 6B. . Then, as shown in FIG. 6C, the end surface of the second conductive layer 112a is oxidized to form an oxide film X, and as shown in FIG. The oxide film X grows, and the protrusion P is formed. After that, the pressure resistance of the insulating film 114 formed so as to cover the first conductive layer 111a and the second conductive layer 112a is lowered. Here, when the film thickness of the first conductive film 111 is relatively large, distortion occurs at the interface between the first conductive film 111 and the second conductive film 112 having different crystal structures (crystal lattices), and the distortion occurs. When the surface of the second conductive film 112 is easily formed in an uneven shape due to the above, and the film thickness of the first conductive film 111 is relatively small, the first conductive film 111 and the second conductive film 112 described above. It is presumed that the strain at the interface becomes small and the surface of the second conductive layer 112 is easily formed flat.

According to the present invention, since the surface of the second conductive layer made of copper is made flat by the film thickness of the first conductive layer, the formation of protrusions in the conductive layer made of copper can be suppressed.

FIG. 1 is a cross-sectional view of a TFT substrate according to the first embodiment. FIG. 2 is a cross-sectional view illustrating a part of the manufacturing process of the TFT substrate according to the first embodiment. FIG. 3 is a cross-sectional view of the TFT substrate according to the second embodiment. FIG. 4 is an explanatory view showing a part of the manufacturing process of the TFT substrate according to the second embodiment in cross section. FIG. 5 is a cross-sectional view of a TFT substrate according to the third embodiment. FIG. 6 is an explanatory view showing, in section, a part of the manufacturing process of the TFT substrate according to the comparative example.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.

Embodiment 1 of the Invention
1 and 2 show Embodiment 1 of a TFT substrate and a manufacturing method thereof according to the present invention. Specifically, FIG. 1 is a cross-sectional view of the TFT substrate 30a of this embodiment. FIG. 2 is an explanatory view showing a part of the manufacturing process of the TFT substrate 30a in cross section.

As shown in FIG. 1, the TFT substrate 30a includes an insulating substrate 10, a plurality of gate lines (not shown) provided on the insulating substrate 10 so as to extend in parallel to each other, and a direction orthogonal to each gate line. A plurality of TFTs 5a provided for each of a plurality of source lines (not shown) provided so as to extend in parallel and for each intersection of each gate line and each source line, that is, for each sub-pixel which is the minimum unit of an image. An interlayer insulating film 19 provided so as to cover each TFT 5a, a plurality of pixel electrodes 20a provided in a matrix on the interlayer insulating film 19 and connected to each TFT 5a, and so as to cover each pixel electrode 20a And an alignment film (not shown).

As shown in FIG. 1, the TFT 5 a includes a gate electrode 13 a provided on the insulating substrate 10, a gate insulating film 14 provided so as to cover the gate electrode 13 a, and a gate electrode 13 a on the gate insulating film 14. Thus, the semiconductor layer 15 provided with the channel region C, and the source electrode 18a and the drain electrode 18b provided on the semiconductor layer 15 so as to overlap the gate electrode 13a and to be separated from and opposed to each other are provided.

The gate electrode 13a is, for example, a protruding portion to the side of each gate line. As shown in FIG. 1, the gate electrode 13a includes a first conductive layer 11a provided on the insulating substrate 10, and a copper second conductive layer 12a stacked on the first conductive layer 11a. . Here, the thickness of the first conductive layer 11a is 50 to 150 mm so that the surface of the second conductive layer 12a is formed flat. And when the film thickness of the 1st conductive layer 11a is smaller than 50 mm, the adhesiveness of the 2nd conductive layer 12a and the insulated substrate 10 (underlayer) will fall too much, and the film | membrane of the 1st conductive layer 11a When the thickness is larger than 150 mm, the surface of the second conductive layer 12a is formed in an uneven shape. The first conductive layer 11a is made of titanium so as to improve the adhesion between the second conductive layer 12a made of copper and the insulating substrate 10.

The semiconductor layer 15 is, for example, laminated with an intrinsic amorphous silicon layer (not shown) having a channel region C so that the channel region C is exposed to the intrinsic amorphous silicon layer, and connected to the source electrode 18a and the drain electrode 18b. n + amorphous silicon layer (not shown).

The source electrode 18a is, for example, a portion protruding to the side of each source line.

As shown in FIG. 1, the drain electrode 18b is connected to the pixel electrode 20a through a contact hole 19a formed in the interlayer insulating film 19.

The TFT substrate 30a having the above configuration constitutes an active matrix driving type liquid crystal display panel together with a counter substrate disposed opposite to the TFT substrate 30a and a liquid crystal layer sealed between the two substrates.

Next, a method for manufacturing the TFT substrate 30a of this embodiment will be described with reference to FIGS. Here, the manufacturing method of this embodiment includes a conductive film forming step and an etching step.

First, a second conductive material such as a first conductive film 11 such as a titanium film having a thickness of about 50 nm and a copper film having a thickness of about 300 nm to 400 nm is formed on the entire substrate of the insulating substrate 10 such as a glass substrate by sputtering. The film 12 is sequentially formed (see FIG. 2A, conductive film formation step). Here, in the present embodiment, a titanium film is exemplified as the first conductive film 12, but the first conductive film 12 may be a molybdenum film, a titanium nitride film, or the like. In the present embodiment, a copper film is exemplified as the second conductive film 13, but the second conductive film 13 may be a copper alloy film.

Subsequently, as shown in FIG. 2A, after the resist pattern Ra is formed on the second conductive film 12 using photolithography, the second conductive film 12 exposed from the resist pattern Ra and the lower conductive film 12 are arranged below the second conductive film 12. The first conductive film 11 to be removed is removed by wet etching using an etchant containing hydrogen peroxide and water, thereby forming a gate composed of the first conductive layer 11a and the second conductive layer 12a as shown in FIG. The electrode 13a and the gate line are formed (etching process).

Then, after the resist pattern Ra is peeled off, as shown in FIG. 2C, the entire substrate on which the gate electrode 13a and the gate line are formed is formed, for example, by a plasma CVD (Chemical Vapor Deposition) method. The gate insulating film 14 is formed by forming a film having a thickness of about 400 nm.

Further, for example, an intrinsic amorphous silicon film (thickness of about 100 nm) and an n + amorphous silicon film doped with phosphorus (thickness of about 50 nm) are formed on the entire substrate on which the gate insulating film 14 is formed by plasma CVD. After sequentially forming the film, a stacked layer of an intrinsic amorphous silicon film and an n + amorphous silicon film is patterned into an island shape on the gate electrode 13a using photolithography, thereby forming a semiconductor layer forming layer.

Subsequently, for example, an aluminum film (thickness of about 200 nm), a titanium film (thickness of about 100 nm), and the like are sequentially formed on the entire substrate on which the semiconductor layer forming layer has been formed by a sputtering method. Then, the metal laminated film is patterned using photolithography to form the source electrode 18a, the drain electrode 18b (see FIG. 1), and the source line.

Then, by using the source electrode 18a and the drain electrode 18b as a mask, the n + amorphous silicon layer of the semiconductor layer forming layer is removed by etching, thereby forming a channel region C (see FIG. 1). A TFT 5a (see FIG. 1) provided with is formed.

Further, for example, a silicon nitride film (thickness of about 200 nm) or the like is formed on the entire substrate on which the TFT 5a is formed to form an inorganic insulating film.

Subsequently, for example, an acrylic photosensitive resin is applied to a thickness of about 2 μm by spin coating on the entire substrate on which the inorganic insulating film is formed, and the applied photosensitive resin is passed through a photomask. After the exposure, development is performed to form an organic insulating film having an opening that becomes a part of the contact hole 19a on the drain electrode 18b (see FIG. 1).

Further, the inorganic insulating film exposed from the opening of the organic insulating film is removed by etching to form a contact hole 19a, whereby an interlayer insulating film 19 composed of the inorganic insulating film and the organic insulating film (see FIG. 1). Form.

Finally, after forming a transparent conductive film such as an ITO (Indium Tin Oxide) film (thickness of about 100 nm) on the entire substrate on which the interlayer insulating film 19 has been formed by sputtering, the transparent conductive film is The pixel electrode 20a is formed by patterning using photolithography.

The TFT substrate 30a can be manufactured as described above.

As described above, according to the TFT substrate 30a and the manufacturing method thereof of the present embodiment, the gate electrode 13a has a laminated structure of the first conductive layer 11a and the second conductive layer 12a made of copper, and the conductive film is formed. In the process, the surface of the second transparent conductive film 12 to be the second conductive layer 12a is made flat by the film thickness of the first conductive film 11 to be the first conductive layer 11a. When the conductive layer 11a and the second conductive layer 12a are formed, the adhesion between the second conductive film 12 and the resist pattern Ra formed thereon is improved. For this reason, in the etching process, it becomes difficult for the etching solution to enter between the second conductive film 12 and the resist pattern Ra, and therefore, the oxidation of the end portion of the second conductive layer 12a caused by the etching solution remaining below the resist pattern Ra. Can be suppressed. Thereby, since formation of the protrusion resulting from oxidation is suppressed in the edge part of the 2nd conductive layer 12a, formation of the protrusion in the copper 2nd conductive layer 12a can be suppressed. Furthermore, since the generation of ESD is suppressed by suppressing the formation of protrusions at the end of the second conductive layer 12a, the destruction of elements such as the TFT 5a and the gate electrode 13a (including the gate line), A short circuit between the source electrode 18a (including the source line) and the drain electrode 18b can be suppressed.

In addition, according to the TFT substrate 30a and the manufacturing method thereof of the present embodiment, the first conductive layer 11a is configured to improve the adhesion between the second conductive layer 12a and the insulating substrate 10, and thus the gate electrode 13a. Can be prevented from peeling off the second conductive layer 12a made of copper.

<< Embodiment 2 of the Invention >>
3 and 4 show Embodiment 2 of the TFT substrate and the manufacturing method thereof according to the present invention. Specifically, FIG. 3 is a cross-sectional view of the TFT substrate 30b of this embodiment. FIG. 4 is an explanatory view showing a part of the manufacturing process of the TFT substrate 30b in cross section. In the following embodiments, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

In the first embodiment, the TFT substrate 30a using the copper wiring as the gate electrode 13a (including the gate line) is illustrated. However, in the present embodiment, not only the gate electrode 13a (including the gate line) but also the source electrode 18c. The TFT substrate 30b using the copper wiring is also exemplified for the drain electrode 18d (including the source line).

As shown in FIG. 3, the TFT substrate 30b includes an insulating substrate 10, a plurality of gate lines (not shown) provided on the insulating substrate 10 so as to extend in parallel to each other, and a direction perpendicular to each gate line. A plurality of source lines (not shown) provided so as to extend in parallel, and a plurality of TFTs 5b provided for each intersection of each gate line and each source line, that is, for each sub-pixel which is the minimum unit of an image An interlayer insulating film 19 provided so as to cover each TFT 5b, a plurality of pixel electrodes 20a provided in a matrix on the interlayer insulating film 19 and connected to each TFT 5b, and so as to cover each pixel electrode 20a And an alignment film (not shown).

As shown in FIG. 3, the TFT 5 b includes a gate electrode 13 a provided on the insulating substrate 10, a gate insulating film 14 provided so as to cover the gate electrode 13 a, and a gate electrode 13 a on the gate insulating film 14. Thus, the semiconductor layer 15 provided with the channel region C and the source electrode 18c and the drain electrode 18d provided on the semiconductor layer 15 so as to overlap the gate electrode 13a and to be separated from and opposed to each other are provided.

The source electrode 18c is, for example, a portion protruding to the side of each of the source lines. As shown in FIG. 3, the source electrode 18c includes a first conductive layer 16c provided on the gate insulating film 14 and the semiconductor layer 15, and a copper second conductive layer 17a stacked on the first conductive layer 16c. And.

As shown in FIG. 3, the drain electrode 18d is connected to the pixel electrode 20a through a contact hole 19a formed in the interlayer insulating film 19. As shown in FIG. 3, the drain electrode 18d includes a first conductive layer 16d provided on the gate insulating film 14 and the semiconductor layer 15, and a copper second conductive layer 17b stacked on the first conductive layer 16d. And.

Here, the first conductive layers 16c and 16d have a thickness of 50 to 150 mm so that the surfaces of the second conductive layers 17a and 17b are formed flat. When the thickness of the first conductive layers 16c and 16d is smaller than 50 mm, the adhesion between the second conductive layers 17a and 17b and the gate insulating film 14 and the semiconductor layer 15 (underlayer) is too low. Thus, when the thickness of the first conductive layers 16c and 16d is larger than 150 mm, the surfaces of the second conductive layers 17a and 17b are formed in an uneven shape. The first conductive layers 16c and 16d are made of titanium so as to improve the adhesion between the copper second conductive layers 17a and 17b and the gate insulating film 14 and the semiconductor layer 15.

The TFT substrate 30b having the above configuration constitutes an active matrix driving type liquid crystal display panel together with a counter substrate disposed opposite to the TFT substrate 30b and a liquid crystal layer sealed between the two substrates.

Next, a method for manufacturing the TFT substrate 30b of this embodiment will be described with reference to FIGS. Here, the manufacturing method of the present embodiment includes a conductive film forming step and an etching step, but the steps up to the step of forming the semiconductor layer forming layer are substantially the same as those of the first embodiment, and thereafter A manufacturing method will be described.

First, the layers up to the semiconductor layer formation layer are formed by the same method as in the first embodiment, and the entire thickness of the substrate on which the semiconductor layer formation layer is formed is, for example, as shown in FIG. A first conductive film 16 such as a titanium film having a thickness of about 50 nm and a second conductive film 17 such as a copper film having a thickness of about 300 nm to 400 nm are sequentially formed (conductive film formation step). Here, in the present embodiment, a titanium film is exemplified as the first conductive film 16, but the first conductive film 16 may be a molybdenum film, a titanium nitride film, or the like. In the present embodiment, a copper film is exemplified as the second conductive film 17, but the second conductive film 17 may be a copper alloy film.

Subsequently, as shown in FIG. 4B, after the resist pattern Rb is formed on the second conductive film 17 using photolithography, the second conductive film 17 exposed from the resist pattern Rb and the lower conductive film 17 are arranged below the second conductive film 17. The first conductive film 16 to be removed is removed by wet etching using an etchant containing hydrogen peroxide and water, thereby forming a source comprising the first conductive layer 16c and the second conductive layer 17a as shown in FIG. An electrode 18c, a drain electrode 18d composed of the first conductive layer 16d and the second conductive layer 17b, and a source line are formed (etching step).

Then, using the source electrode 18c and the drain electrode 18d as a mask, the n + amorphous silicon layer of the semiconductor layer forming layer is removed by etching, thereby forming a channel region C (see FIG. 3). A TFT 5b (see FIG. 3) including the above is formed.

Further, for example, a silicon nitride film (thickness of about 200 nm) or the like is formed on the entire substrate on which the TFT 5b is formed to form an inorganic insulating film.

Subsequently, for example, an acrylic photosensitive resin is applied to a thickness of about 2 μm by spin coating on the entire substrate on which the inorganic insulating film is formed, and the applied photosensitive resin is passed through a photomask. After the exposure, development is performed to form an organic insulating film having an opening that becomes a part of the contact hole 19a on the drain electrode 18d (see FIG. 3).

Further, the inorganic insulating film exposed from the opening of the organic insulating film is removed by etching to form a contact hole 19a, whereby an interlayer insulating film 19 composed of the inorganic insulating film and the organic insulating film (see FIG. 3). Form.

Finally, after forming a transparent conductive film such as an ITO film (thickness of about 100 nm) on the entire substrate on which the interlayer insulating film 19 has been formed by sputtering, the transparent conductive film is formed using photolithography. The pixel electrode 20a is formed by patterning.

The TFT substrate 30b can be manufactured as described above.

As described above, according to the TFT substrate 30b and the manufacturing method thereof according to the present embodiment, in addition to the effects of the first embodiment, the source electrode 18c is formed of the first conductive layer 16c and the second conductive layer 17a made of copper. The drain electrode 18d has a laminated structure of a first conductive layer 16d and a copper second conductive layer 17b, and the first conductive layer 16c and 16d is formed in the conductive film forming step. Since the surface of the second transparent conductive film 17 to be the second conductive layers 17a and 17b is flattened by the film thickness of the film 16, the first conductive layers 16c and 16d and the second conductive layer 17a are etched in the etching process. And 17b, the adhesion between the second conductive film 17 and the resist pattern Rb formed thereon is improved. For this reason, in the etching process, it becomes difficult for the etchant to enter between the second conductive film 17 and the resist pattern Rb. Therefore, the end portions of the second conductive layers 17a and 17b caused by the etchant remaining below the resist pattern Rb. Can be suppressed. Thereby, since formation of the protrusion resulting from oxidation is suppressed in the edge part of the 2nd conductive layers 17a and 17b, formation of the protrusion in copper-made 2nd conductive layers 17a and 17b can be suppressed. Further, since the formation of protrusions at the end portions of the second conductive layers 17a and 17b is suppressed, the generation of ESD is suppressed, so that the elements such as the TFT 5b are destroyed and the gate electrode 13a (including the gate line). And a short circuit between the source electrode 18c (including the source line) and the drain electrode 18d can be suppressed.

Further, according to the TFT substrate 30b and the manufacturing method thereof of the present embodiment, the first conductive layers 16c and 16d improve the adhesion between the second conductive layers 17a and 17b and the gate insulating film 14 and the semiconductor layer 15. Since it is comprised, peeling of the copper 2nd conductive layer 17a which comprises the source electrode 18c, and the copper 2nd conductive layer 17b which comprises the drain electrode 18d can be suppressed.

<< Embodiment 3 of the Invention >>
FIG. 5 is a cross-sectional view of the terminal region of the TFT substrate 30 of this embodiment.

In each of the above embodiments, the structure of the display region of the TFT substrates 30a and 30b has been illustrated, but in this embodiment, the structure of the terminal region of the TFT substrate 30 is illustrated. Here, the display area is an area in which a plurality of sub-pixels are arranged in a matrix, and the terminal area is an area at the end of the substrate outside the display area.

The configuration of the display area of the TFT substrate 30 is substantially the same as the TFT substrate 30a of the first embodiment or the TFT substrate 30b of the second embodiment.

In the terminal region of the TFT substrate 30, a plurality of gate lines extending in parallel with each other in the display region described in the first embodiment are drawn out to form gate lines 13b as shown in FIG.

As shown in FIG. 5, the gate line 13b includes a first conductive layer 11b provided on the insulating substrate 10, and a copper second conductive layer 12b stacked on the first conductive layer 11b. Here, the thickness of the first conductive layer 11b is 50 to 150 mm so that the surface of the second conductive layer 12b is formed flat. When the thickness of the first conductive layer 11b is smaller than 50 mm, the adhesion between the second conductive layer 12b and the insulating substrate 10 (underlying layer) is excessively lowered, and the film of the first conductive layer 11b When the thickness is larger than 150 mm, the surface of the second conductive layer 12b is formed in an uneven shape. The first conductive layer 11b is made of titanium so as to improve the adhesion between the second conductive layer 12b made of copper and the insulating substrate 10.

As shown in FIG. 5, the end of the gate line 13b is covered with a transparent conductive layer 20b to form a gate terminal T.

The TFT substrate 30 of this embodiment can be manufactured by forming the transparent conductive layer 20b simultaneously with the pixel electrode 20a in the manufacturing method described in the first and second embodiments.

As described above, according to the TFT substrate 30 and the manufacturing method thereof according to the present embodiment, the surface of the second conductive layer 12b made of copper is changed depending on the film thickness of the first conductive layer 11b as in the first and second embodiments. Since it is made flat, formation of the projection part in the 2nd copper conductive layer 12b can be suppressed, and generation | occurrence | production of ESD in the gate terminal T can be suppressed.

In the present embodiment, the structure of the gate terminal at the end of the gate line is illustrated, but the present invention can also be applied to the structure of other terminals such as the source terminal at the end of the source line.

In each of the above embodiments, a TFT substrate using copper wiring for at least the gate electrode has been exemplified. However, the present invention can also be applied to a TFT substrate using copper wiring for at least one of the source electrode and the drain electrode. Can do.

In each of the above embodiments, a TFT substrate having a bottom gate type TFT has been exemplified. However, the present invention can also be applied to a TFT substrate having a top gate type TFT.

In each of the above embodiments, the TFT substrate using the TFT electrode connected to the pixel electrode as the drain electrode has been exemplified. However, the present invention is applied to the TFT substrate called the source electrode. Can also be applied.

In each of the above embodiments, the TFT substrate constituting the liquid crystal display panel is exemplified, but the present invention can also be applied to other display panels such as an organic EL (Electro Luminescence) panel.

Further, in each of the above embodiments, the TFT substrate in which the capacitor line that configures the auxiliary capacitor is not disposed in each subpixel is illustrated. However, in the present invention, the capacitor line that configures the auxiliary capacitor is disposed in each subpixel. It can also be applied to a TFT substrate.

As described above, the present invention can suppress the formation of the protrusions in the copper conductive layer, and thus is useful for TFT substrates that require low wiring resistance.

C channel region Ra, Rb resist pattern 5a, 5b TFT
10 Insulating substrate (underlayer)
11a, 11b, 16c, 16d First conductive layer 12a, 12b, 17a, 17b Second conductive layer 13a Gate electrode 14 Gate insulating film (underlayer)
15 Semiconductor layer (underlayer)
18a, 18c Source electrode 18b, 18d Drain electrode 30, 30a, 30b TFT substrate

Claims (5)

  1. A semiconductor layer having a channel region;
    A gate electrode provided on the semiconductor layer via a gate insulating film and disposed so as to overlap the channel region;
    A thin film transistor substrate provided with a plurality of thin film transistors each provided with a source electrode and a drain electrode provided so as to be separated from each other and connected to both outer sides of the channel region of the semiconductor layer,
    At least one of the gate electrode, the source electrode, and the drain electrode has a first conductive layer and a copper second conductive layer provided on the first conductive layer,
    The thin film transistor substrate, wherein the film thickness of the first conductive layer is set so that the surface of the second conductive layer is flat.
  2. The thin film transistor substrate according to claim 1,
    The thin film transistor substrate according to claim 1, wherein the first conductive layer has a thickness of 50 to 150 mm.
  3. In the thin film transistor substrate according to claim 1 or 2,
    The thin film transistor substrate, wherein the first conductive layer is configured to improve adhesion between the second conductive layer and the base layer.
  4. The thin film transistor substrate according to any one of claims 1 to 3,
    The thin film transistor substrate, wherein the first conductive layer is made of titanium.
  5. A semiconductor layer having a channel region;
    A gate electrode provided on the semiconductor layer via a gate insulating film and disposed so as to overlap the channel region;
    A method of manufacturing a thin film transistor substrate provided with a plurality of thin film transistors each provided with a source electrode and a drain electrode provided so as to be separated from each other and connected to both outer sides of the channel region of the semiconductor layer,
    After the first conductive film is formed on the substrate with a predetermined film thickness, a copper second conductive film is formed on the first conductive film so that the surface is flattened by the film thickness of the first conductive film. A conductive film forming step;
    After forming a resist pattern on the second conductive film, the second conductive film exposed from the resist pattern and the first conductive film disposed below the second conductive film are removed by wet etching, and the first conductive film is removed. An etching process for forming at least one of the gate electrode, the source electrode, and the drain electrode by forming a first conductive layer from one conductive film and forming a second conductive layer from the second conductive film. A method for manufacturing a thin film transistor substrate, comprising:
PCT/JP2012/000094 2011-01-13 2012-01-10 Thin-film transistor substrate and method for manufacturing same WO2012096155A1 (en)

Priority Applications (2)

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JP2011-004614 2011-01-13
JP2011004614 2011-01-13

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000347221A (en) * 1999-05-27 2000-12-15 Sharp Corp Method of forming polycrystal silicon tft using copper wiring for pixel array in liquid crystal display
JP2002094078A (en) * 2000-06-28 2002-03-29 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2010272663A (en) * 2009-05-21 2010-12-02 Sony Corp Thin film transistor, display device, and electronic apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000347221A (en) * 1999-05-27 2000-12-15 Sharp Corp Method of forming polycrystal silicon tft using copper wiring for pixel array in liquid crystal display
JP2002094078A (en) * 2000-06-28 2002-03-29 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2010272663A (en) * 2009-05-21 2010-12-02 Sony Corp Thin film transistor, display device, and electronic apparatus

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