JP2002094071A - Semiconductor device and inter-layer insulation layer forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and an inter-layer insulation layer forming method for maintaining the transfer ability and reliability of a thin-film field effect transistor, which simultaneously reduces the short-circuit between the upper and lower parts of a wiring crossing part, and moreover improving sensitivity in a photoelectric converter. SOLUTION: On an insulation substrate 201, a first conductive layer 202 for constituting the gate electrode and gate wiring of a TFT, an inter-layer insulation layer 203, a semiconductor layer 204, an ohmic contact layer 205, and a second conductive layer 206 for constituting the source/drain electrode and signal line of the TFT, are formed. Also, the inter-layer insulation layer 203 of the upper and lower wiring crossing parts is formed with a film thickness which is larger than the peripheral inter-layer insulation layer 203.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and an interlayer insulating layer forming method, and more particularly, to a photoelectric conversion device mounted on an image reading device / image pickup device represented by a scanner / X-ray image pickup device, and the like. Used for active matrix type liquid crystal display devices, TFT (ThinFilm Transis
The present invention relates to a semiconductor device having a structure in which a plurality of pixels formed by a tor (a thin film field effect transistor) and a capacitor are arranged, and an interlayer insulating layer forming method.

[0002]

2. Description of the Related Art In recent years, hydrogenated amorphous silicon (a
Scanner, using a semiconductor material represented by -Si).
2. Description of the Related Art Semiconductor devices having a structure in which an image reading element and a switch TFT mounted on a digital copying machine, an X-ray imaging device, and the like are formed one-dimensionally or two-dimensionally on a large-area substrate have been put to practical use.

In particular, since a-Si can be formed uniformly on a large-area substrate at a low temperature, there is an advantage that an inexpensive glass substrate can be used. In addition, since it can be used not only as a semiconductor material of a thin film field effect transistor (TFT) but also as a photoelectric conversion material, there is an advantage that a photoelectric conversion semiconductor layer and a TFT can be simultaneously formed.

Conventionally, a photoelectric conversion device represented by this type of semiconductor device generally includes a PIN photodiode as a photoelectric conversion element and a TFT as a switch element, but uses a-Si. Since the photoelectric conversion semiconductor layer and the TFT can be formed at the same time,
MIS (Metal Insulator Semicond.)
uctor (metal insulated semiconductor) type photodiodes are also in practical use.

FIG. 5 is a basic equivalent circuit diagram of a semiconductor device having a plurality of TFTs t11 to t5n and a plurality of capacitors c11 to c5n. In FIG. 5, each TFT t11
To t5n are common gate wirings Vg
Vg line 501 is connected to each TFT
It is connected to a gate driver 502 that controls ON / OFF of t11 to t5n. In addition, each TFT t11 to t
The 5n source or drain electrode is connected to a Sig line 503 which is a common signal line.
Are connected to a source driver (amplifier IC) 504. In the figure, 506 is a common electrode driver, and 507 is a TFT.
This is a TFT matrix panel in which t11 to t5n and capacitors c11 to c5n are arranged in a matrix.

[0006] The Sig line 503 is connected to the TFTs t11 to t5n.
A signal line capacitance C2 is formed by a cross portion of the signal line capacitance V2 and the Vg line 501. In the photoelectric conversion device, the output of the Sig line 503 is determined by the capacitance C1 of the photodiode and the signal line capacitance C2. That is, it is generated in the photoelectric conversion element from the incident light,
The accumulated electric charge is distributed to the capacitance C1 of the photodiode and the capacitance C2 of the signal line by the TFTs t11 to t5n, and the Sig line potential is read out by the amplifier IC 504 to obtain image information.

FIG. 6 is a schematic sectional view of the TFT portion of the semiconductor device shown in FIG. In FIG. 6, reference numeral 601 denotes an insulating substrate;
Reference numeral 602 denotes a first conductive layer forming a gate electrode and a gate wiring. Reference numerals 603, 604, and 605 denote an interlayer insulating layer, a semiconductor layer, and an ohmic contact layer, respectively. Reference numeral 606 denotes a second conductive layer forming the source / drain electrodes of the switch TFT and the signal line.

[0008]

However, the above-described prior art has the following problems.

In the above conventional example, in recent years, the area of the substrate has been increased, and the number of pixels has been increased accordingly. As a result, defects due to high-density wiring routing have increased.
Specifically, there is a relatively large problem of short-circuit between the upper and lower portions at the wiring intersection. This problem is caused by increasing the thickness of the interlayer insulating layer.
The problem can be solved by covering a foreign substance that causes a short circuit. Further, in the photoelectric conversion device, since the output sensitivity is improved due to a decrease in C2 which is a cross portion capacitance between the Sig line and the Vg line, a thicker interlayer insulating layer is required.

However, in the TFT portion, since the interlayer insulating layer has an appropriate thickness in terms of the transfer capability and reliability of the TFT, the conventional interlayer insulating of the TFT and the signal line (Sig line) is required. In a layer configuration in which the layers are formed in the same layer, there is a problem that the interlayer insulating layer cannot be made thicker than the appropriate thickness of the TFT.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device which can maintain the transfer performance and reliability of a thin film field effect transistor, reduce the short-circuit between upper and lower portions of a wiring intersection, and can improve the sensitivity in a photoelectric conversion device. And a method for forming an interlayer insulating layer.

[0012]

According to the present invention, an interlayer insulating layer of the thin film field effect transistor is provided on an interlayer insulating layer at an intersection of a vertical wiring and a horizontal wiring on the insulating substrate on which the thin film field effect transistor is formed. Wherein the interlayer insulating layer at at least one or more of the upper and lower wiring intersections has a structure formed to be thicker than surrounding interlayer insulating layers.

The semiconductor device according to the present invention will be described with reference to FIG. 2. Referring to FIG. 2, the interlayer insulating layer 203 at the intersection of the vertical wiring and the horizontal wiring on the insulating substrate 201 on which the thin film field effect transistor is formed. A semiconductor device using an interlayer insulating layer of the thin film field effect transistor, wherein at least one or more of the upper and lower wiring intersecting portions is formed to have a thickness larger than that of a surrounding interlayer insulating layer. It has.

[Operation] The semiconductor device of the present invention is a semiconductor device having a layer structure in which a source or drain electrode of a thin film field effect transistor and a signal line are formed in the same layer.
While maintaining the transfer performance and reliability of the thin film field effect transistor, while reducing the short circuit between the top and bottom of the wiring intersection,
In a photoelectric conversion device using the semiconductor device of the present invention, improvement in sensitivity can be realized.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

(1) Description of Configuration As a first embodiment of the present invention, a MI
A method for forming an interlayer insulating layer twice in a photoelectric conversion device using an S-type photodiode and a TFT as a switch element will be described with reference to FIGS.

Step 1: Switch TF on insulating substrate 201
A Cr film is formed as a T gate electrode by sputtering.

Step 2: A gate electrode 202 of the switch TFT is formed using the photomask shown in FIG. FIG. 2A is a schematic cross-sectional view.

Step 3: CVD (Chemical Vapor Deposition) of a SiN film as a first interlayer insulating layer
To form a film. This film thickness is determined by the size of the target foreign matter and the coverage ability of the film constituting the upper layer.

Step 4: Using the photomask shown in FIG. 1B, the first interlayer insulating layer 203 'at the intersection of the upper and lower wirings
To form FIG. 2B is a schematic cross-sectional view.

Step 5: As the second interlayer insulating layer 203 ″, the semiconductor layer 204, and the ohmic contact layer 205,
An iN layer, an i layer, and an n ⁺ layer are formed by CVD.

Step 6: Using the photomask shown in FIG. 1C, a contact hole 210 is formed by CDE (Chemical Dry Etching). FIG. 2C is a schematic sectional view.

Step 7: A source / drain (SD) electrode of the switch TFT and an Al film are formed by sputtering as a Sig line and a Vs line.

Step 8: The source / drain electrodes of the switch TFT and the wiring 206 are formed using the photomask shown in FIG. 1D, and subsequently, using the photomask shown in FIG. RIE (Reactive Ion Etching:
N ⁺ in the TFT gap is removed by reactive ion etching). FIG. 2D is a schematic sectional view.

Step 9: The n ⁺ layer, the i layer, and the interlayer insulating layer are separated from each other by using the photomask shown in FIG. FIG. 2E is a schematic sectional view. In FIG. 2E, 201 is an insulating substrate, 202 is a first conductive layer forming a gate electrode and a gate wiring, and 203 is a first interlayer insulating layer 203 ′ and a second interlayer insulating layer 203 ″. An interlayer insulating layer, 204 is a semiconductor layer, 205 is an ohmic contact layer, and 206 is a second conductive layer constituting source / drain electrodes and signal lines of the switch TFT.

After the above step 9, a protective film (not shown) is laminated on the ohmic contact layer 205 and the second conductive layer 206. It is necessary to laminate a protective layer also on a portion other than "on the ohmic contact layer 205 and the second conductive layer 206" (for example, a TFT gap portion). Further, a protective layer is also laminated on a device portion formed on a glass substrate.

(2) Description of Operation Next, the operation of the first embodiment of the present invention will be described in detail with reference to FIG.

TF is formed on the interlayer insulating layer at the intersection of the upper and lower wirings of the vertical wiring and the horizontal wiring on the insulating substrate 201 on which the TFT is formed.
In a photoelectric conversion device using an interlayer insulating layer of T, as shown in FIG. 2, a structure in which at least one or more interlayer insulating layers 203 at the intersections of upper and lower wirings are formed with a thickness larger than the surrounding interlayer insulating layers. Therefore, it was possible to confirm a sufficiently satisfactory reduction in the short-circuit rate between the upper and lower portions at the intersection of the wirings.
Further, it was confirmed that the sensitivity was improved due to a decrease in the signal line capacity.

According to the first embodiment of the present invention, in a photoelectric conversion device having a layer structure in which a source or drain electrode of a TFT and a Sig line are formed in the same layer, while maintaining transfer performance and reliability of the TFT, wiring The short circuit between the upper and lower portions of the intersection can be reduced, and the sensitivity can be improved.

[Second Embodiment] Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

(1) Description of Configuration As a second embodiment of the present invention, the MI
With reference to FIGS. 3 and 4, a method for forming an interlayer insulating layer by using half-etching of the surroundings in a photoelectric conversion device using an S-type photodiode and a TFT as a switch element will be described.

Step 1: Switch TF on insulating substrate 401
A Cr film is formed as a T gate electrode by sputtering.

Step 2: The gate electrode 402 of the switch TFT is formed using the photomask shown in FIG. FIG. 4A is a schematic sectional view.

Step 3: A SiN film is formed as an interlayer insulating layer 403 by CVD. This film thickness is determined by the size of the target foreign matter and the coverage ability of the film constituting the upper layer.

Step 4: Using the photomask shown in FIG. 3B, half-etching is performed by RIE, and the portion other than the intersection between the upper and lower wirings is set to an appropriate film thickness of the TFT. FIG. 4B is a schematic sectional view.

Step 5: An i layer and an n ⁺ layer are formed by CVD as the semiconductor layer 404 and the ohmic contact layer 405.

Step 6: A contact hole 410 is formed by CDE using the photomask shown in FIG. FIG. 4C is a schematic sectional view.

Step 7: An Al film is formed as a source / drain (SD) electrode of the switch TFT, a Sig wiring, and a Vs wiring by sputtering.

Step 8: The source / drain electrodes of the switch TFT and the wiring 406 are formed using the photomask shown in FIG. 3D, and subsequently, using the photomask shown in FIG. In RIE, n ⁺
Is removed. FIG. 4D is a schematic sectional view.

Step 9: The n ⁺ layer, the i layer, and the interlayer insulating layer are separated from each other by using the photomask shown in FIG. FIG. 4E is a schematic sectional view. 4E, reference numeral 401 denotes an insulating substrate; 402, a first conductive layer forming a gate electrode and a gate wiring; 403, an interlayer insulating layer;
404 is a semiconductor layer, 405 is an ohmic contact layer,
Reference numeral 406 denotes a second conductive layer forming the source / drain electrodes of the switch TFT and the signal line.

After the completion of the above step 9, a protective film (not shown) is laminated on the ohmic contact layer 405 and the second conductive layer 406. It is necessary to laminate a protective layer also on a portion other than "on the ohmic contact layer 205 and the second conductive layer 206" (for example, a TFT gap portion). Further, a protective layer is also laminated on a device portion formed on a glass substrate.

(2) Description of Operation Next, the operation of the second embodiment of the present invention will be described in detail with reference to FIG.

TF is formed on the interlayer insulating layer at the intersection of the upper and lower wirings of the vertical wiring and the horizontal wiring on the insulating substrate 401 on which the TFT is formed.
In the photoelectric conversion device using the T interlayer insulating layer, as shown in FIG. 4, a structure in which at least one or more interlayer insulating layers 403 at the intersections of the upper and lower wirings are formed with a thickness larger than the surrounding interlayer insulating layers. Therefore, it was possible to confirm a sufficiently satisfactory reduction in the short-circuit rate between the upper and lower portions at the intersection of the wirings.
Further, it was confirmed that the sensitivity was improved due to a decrease in the signal line capacity.

According to the second embodiment of the present invention, in a photoelectric conversion device having a layer structure in which a source or drain electrode of a TFT and a Sig line are formed in the same layer, the transfer capability and reliability of the TFT are maintained while the wiring is formed. The short circuit between the upper and lower portions of the intersection can be reduced, and the sensitivity can be improved.

[0045]

As described above, according to the present invention, the thin film field effect transistor is formed on the interlayer insulating layer at the intersection of the vertical wiring and the horizontal wiring on the insulating substrate on which the thin film field effect transistor is formed. In a semiconductor device using an interlayer insulating layer, the source or drain of the thin-film field-effect transistor is formed because at least one of the interlayer insulating layers at the intersection of the upper and lower wirings is formed to be thicker than a surrounding interlayer insulating layer. In a semiconductor device having a layer structure in which an electrode and a signal line are formed in the same layer, while maintaining transfer performance and reliability of a thin film field effect transistor, a short circuit between upper and lower portions of a wiring intersection is reduced, and a semiconductor device of the present invention is provided. In a photoelectric conversion device using, there is an effect that sensitivity can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view of a photomask used in a manufacturing process of a photoelectric conversion device according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view of the photoelectric conversion device according to the first embodiment of the present invention.

FIG. 3 is a plan view of a photomask used in a manufacturing process of a photoelectric conversion device according to a second embodiment of the present invention.

FIG. 4 is a schematic sectional view of a photoelectric conversion device according to a second embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of the semiconductor device.

FIG. 6 is a schematic cross-sectional view of a TFT section of a semiconductor device.

[Explanation of symbols]

201, 401 insulating substrate 202, 402 gate electrode and gate wiring of switch TFT 203, 403 interlayer insulating layer 204, 404 semiconductor layer 205, 405 ohmic contact layer 206, 406 source or drain electrode of switch TFT and signal line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 619A F-term (Reference) 4M118 AA10 AB01 BA05 BA14 CA07 CA11 FB03 FB09 FB13 FB26 5C024 AX11 CX41 CY47 EX01 GX03 GX07 HX40 5F033 HH08 JJ01 JJ08 KK17 PP15 QQ09 QQ10 QQ11 QQ37 RR06 UU04 VV15 XX31 5F110 AA26 BB10 CC07 EE04 EE44 FF03 FF29 GG35 GG44 HK08 HK34 HL03 HL23 NN23 NN02

Claims (6)

[Claims] 1. A semiconductor device using an interlayer insulating layer of a thin-film field-effect transistor as an interlayer insulating layer at an intersection of an upper wiring and a lower wiring on an insulating substrate on which a thin-film field-effect transistor is formed, A semiconductor device having a structure in which the interlayer insulating layer at one of the upper and lower wiring intersections is formed to be thicker than a surrounding interlayer insulating layer. 2. The semiconductor device according to claim 1, wherein the interlayer insulating layer at the intersection of the upper and lower wirings has a structure formed by a plurality of film forming steps. 3. The structure according to claim 1, wherein the interlayer insulating layer in a portion other than the upper and lower wiring intersections is formed by a film forming step and an etching process in a portion other than the upper and lower wiring intersections. 3. The semiconductor device according to claim 1. 4. An interlayer insulation of a semiconductor device using an interlayer insulation layer of a thin film field effect transistor as an interlayer insulation layer at an intersection of an upper wiring and a lower wiring on an insulating substrate on which a thin film field effect transistor is formed. A method of forming an interlayer insulating layer, comprising a step of forming at least one or more of the interlayer insulating layers at intersections of the upper and lower wirings with a thickness larger than that of surrounding interlayer insulating layers. 5. The method according to claim 4, wherein the step includes a step of forming the interlayer insulating layer at the intersection of the upper and lower wirings by a plurality of film forming steps. 6. The method according to claim 1, wherein the step includes a step of forming the interlayer insulating layer at a portion other than the intersection of the upper and lower wirings and a step of etching the portion other than the intersection of the upper and lower wirings. The method for forming an interlayer insulating layer according to claim 4.