JP2002077209A - In-ring clock control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an in-ring clock control system which automatically sets a clock, having the highest quality for avoiding a timing loop. SOLUTION: A minimum NDID value detecting section 4 refers to the PL information on EXTCLK from a PL/QL table 3, and when the PL information is NSEL, stops the succeeding processings. When the information is not NSEL, however, the section 4 discriminates whether the NDID of its own station has the minimum value among all nodes by referring to an NDID/NDSEQ table 2. The node, which is discriminated as having the minimum value decides its own station as the master station of nodes having external input clocks, and a PL/QL processing section 5 discriminates as to whether the QL and PL of the relevant EXTCLK are at the highest levels. When the section 5 discriminates that the PL and QL are at the highest levels, an S1 byte generating and transmitting section 6 generates the S1 byte, corresponding to the highest quality level and transmits the byte to lines LINE1 and LINE2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control system in a ring, and more particularly to a timing loop (Tim).
The present invention relates to an in-ring clock control system that sets the highest quality clock while avoiding a ring loop.

[0002]

2. Description of the Related Art A conventional reception synchronization message (SSM (s
ynchronization status mes
As an example of the clock control method in the RING using the “sage”), four ADMs (Add-Drop Multi) are used.
A RING system having a (plexer) node will be described.

Here, the ADM is compatible with SONET (sync).
A node on a ring such as a conventional optical network, for example, 155 Mbits /
On a high-speed transmission line such as seconds or 622 Mbit / s, a low-speed line of less than or equal to that is put in and out of the high-speed transmission line (add /
drop).

In FIG. 5, four ADM devices NODE1 to NODE4 are connected, and NODE1 and NODE3 have:
A RING system for providing two external input clocks EXTCLK1 and EXTCLK2 respectively is shown.

A solid line with an arrow connecting between the NODEs represents a main signal line using an optical fiber, and a dotted line with an arrow shows a clock flow. The dotted line with the arrow pointing inside the ring in each NODE indicates which Timing Re
Indicates whether the internal clock is generated in synchronization with the reference. In FIG. 5, NODE4, NODE
3 and NODE2 are both synchronized with EXTCLK1.

Table 1 shows the timing of each ADM device.
A setting example of Reference is shown.

[0007]

[Table 1]

[0008] For simplicity, the QL settings are equal at all nodes. In all the nodes, the PL set value of the holdover is set to 14, and the PL set value of the internal clock (free-run) is set to 15.

QL (quality level), P
For L (priority level), ITU
-T regulation G. 781. QL is Timing Re
quality Level of the reference
el), and 1-5, 7 and SSM can be set.

[0010] PL indicates the priority in the same QL value. In Table 1, 1 to 15 and NSEL are set. NSEL is the applicable Timing Ref
This is a setting that makes it impossible to select “erence”.

[0011] Further, the smaller the numerical value of both QL and PL, the higher the priority.

Also, the reception synchronization message (SSM (Syn)
chronization Status Messa
ge)), the QL value indicated by the received S1 byte becomes the set value.

In each NODE, QL with the highest priority,
The internal clock synchronized with the clock having the PL setting is generated, and the QL of the Timing Reference is transmitted in both LINE directions.

However, when the internal clock is synchronized with the LINE clock, QL is added to the extracted LINE.
7 is transmitted. This is to avoid a timing loop.

FIG. 6 is a timing chart showing clock control of the entire system. As shown in this timing chart, the internal clock of NODE1 is QL2
EXTCLK1 and EXTCLK2 are more P
NODE in synchronization with EXTCLK1 where the L value is high priority
QL2 is sent to both LINEs.

Then, the internal clock of the NODE 4 is
Of LINE1 and LINE2 set in the SSM, QL7 is transmitted to LINE1 in synchronization with LINE1 clock for receiving QL2 transmitted by NODE1, and
Send QL2 to NE3.

Further, the internal clock of the NODE 3 is Q
LINE1 that receives L2 and is set in SSM
EXTCLK1 and EXTCLK2, which are QL2 and QL2, transmit QL7 to LINE1 and QL2 to LINE2 in synchronization with LINE1 having a higher PL value.

Further, the internal clock of the NODE 2 is S
LINE1 and LINE2 set in SM are both Q
LINE1 which receives L2 but has higher PL value
QL7 is sent to LINE1 in synchronization with
To the QL2.

[0019]

Referring to FIG. 7, consider a case where multiple failures occur in the above-described ring transmission line. In FIG. 7, it is assumed that signal loss 1 occurs first between NODE1 and NODE4, signal loss 2 occurs next between NODE2 and NODE3, and then signal loss 2 is restored.

According to the timing chart shown in FIG. 6, when a signal interruption 1 occurs between NODE1 and NODE4, since QL7 is received by LINE2 in NODE4, Timide having the second highest priority next to the LINE1 clock.
ng Reference as QL5 and PL14
QL5 is sent to LINE2 by the internal clock synchronized with HOLDOVER having the above.

In NODE3, EXT5 is received to receive QL5 from LINE2 and QL7 from LINE1.
LK1 and EXTCLK2 have a higher QL value priority, and QL2 is transmitted in both directions of LINE1 and LINE2 by an internal clock synchronized with EXTCLK1 having a higher PL value priority.

At this time, in NODE4, LINE2 side is Q
When L2 is received, the internal clock synchronized with HOLDOVER is synchronized with LINE2, and QL7 is transmitted to LINE2.

In NODE2, the QL value input from LINE1 remains QL2, and there is no change in the synchronization of the internal clock.

In NODE1, similarly to NODE2, there is no change in the synchronization of the internal clock.

If only signal interruption 1 between NODE1 and NODE4 occurs, this state is stabilized.

From this state, NODE2 and NOD
When the signal loss 2 occurs during E3, LI in NODE2
Timing Re with the highest priority next to NE1 clock
As the reference, an internal clock synchronized with LINE2 is generated, and QL7 is sent to LINE2. There is no change in Timing Reference in other NODEs.

At the same time that only signal interruption 2 is restored from this state, NODE 3 sends QL 2 in the direction of LINE 2 by the internal clock synchronized with EXTCLK 1 and NO
DE2 sends out QL2 in the direction of LINE1 by the internal clock synchronized with LINE2.

NODE receiving QL2 from NODE2
3 is QL7 in the direction of LINE2 to synchronize with LINE2.
return it. Also, NODE2 receives QL2 from NODE3 and synchronizes with LINE1 so that QL moves in the LINE1 direction.
Returns 7

Then, NODE3 is driven to QL2 in the direction of LINE2 by the internal clock synchronized with EXTCLK1.
And NODE2 sends QL2 in the direction of LINE1 by the internal clock synchronized with LINE2.

As shown in FIG. 8, this repetition continues until the signal interruption 1 is restored. This is Timing Look
In NODE2 and NODE3, the selection of Timing Reference for synchronizing the internal clock of the device is in an oscillating state. Such a Timing Loop
Is not only a 4-NODE RING system, but also NO
It happens even if the DE number is higher.

Accordingly, the present invention provides a method for controlling a plurality of ADMs (Add
-Drop Multiplexer) node and AD
In a ring system including a clock supply device that supplies a clock to an M node, a reception synchronization message (SS
M (Synchronization Status)
It is an object of the present invention to set the highest quality clock so as to avoid Timing Loop using the Message)).

[0032]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a plurality of ADMs (Add-Drop Mu).
The ADM device includes a clock supply device that supplies a clock to the ADM device, and a reception synchronization message (SSM (Synchronization S)).
a RING clock control system using the ADM, and two or more ADMs supplied with a clock as an external input clock;
The external input clock received by one of the ADMs is set as the highest quality, and the setting of the highest quality clock is such that the node identifier (NDID) for the node sequence number (NDSEQ) = 0 is the minimum value among all the NDIDs. It is determined whether or not the clock control is performed.

More specifically, each of the ADM nodes used in the in-ring clock control system of the present invention includes an alarm detecting unit for detecting an input cutoff of an external clock, and an NDID / NDSEQ table for storing the plurality of node sequence information. And Timing Reference of the plurality of nodes
a PL / QL table for storing the QL and PL of the ce, and the P / L of the external clock with reference to the PL / QL table.
If L is NSEL, stop the process; otherwise, refer to the NDID / NDSEQ table to see NDSEQ
An NDID minimum value detection unit that determines whether the NDID for = 0 is the minimum value of all NODEs, a PL / QL processing unit that detects whether the QL and PL of the external clock are at the highest level, An ADM node that has an S1 byte generation / transmission unit that generates an S1 byte and sends the S1 byte to the ring system; And load the lower 4 bits with QL,
The ADM node that has transmitted to the ring system and received the S1 byte recognizes the QL loaded in the lower 4 bits as the upper QL.

Further, in the clock control method of the present invention, the ADM node which has detected the external clock input disconnection loads the external clock input disconnection information in the upper 4 bits of the S1 byte and sets QL in the lower 4 bits. The ADM node that has loaded the packet and transmitted it to the ring system and received the S1 byte is the QL loaded with the lower 4 bits.
Is a clock control method using an in-ring clock control system that recognizes
If LINE is selected as the synchronization source clock and the QL is not received from the LINE, if at least one LINE is not NSEL or if at least one LINE is not disconnected, the NDID for NDSEQ = 0 is Determine whether the value is the minimum value of all NDIDs,
If not, loading the upper 4 bits of the S1 byte with the first status of input disconnection, loading the lower 4 bits with QL smaller than 2, and sending out, NDSEQ = 0
Determining the own NODE as a master station from a plurality of NODEs having an external input timing source in the NODE for which the NDID with respect to the NDID is the minimum value among all the NDIDs; And the QL value for loading the lower 4 bits is transmitted as 2.

That is, in the present invention, each NODE
In order to send the node information including the node ID (NDID) and the node sequence number (NDSEQ) set in the S1 byte, the unused upper four bits b1, b2, b3, and b4 of the S1 byte are used. One NODE to be a master station is determined from a plurality of NODEs having an input timing source.

Specifically, in a plurality of NODEs having an external input timing source, a node ID (NDID)
With reference to the node sequence information including the node sequence number (NDSEQ) and the node sequence information (NDSEQ), the NODE having the minimum value of the NDID for NDSEQ = 0 among all the node sequence numbers is set as the master station, and the S1 byte [upper 4 bits = 0001] + [Lower 4 bits = 0000 (Q
L2)]. However, [upper 4 bits = 000
1] is a Timing Reference in which the internal clock of EXTCLK1 or EXTCLK2 is synchronized.
Is sent. [Upper 4 bits = 0001] +
The NODE that has received the S1 byte of [lower 4 bits = 0000 (QL2)] recognizes this as a higher QL value (denoted as QL2 *) instead of normal QL2.

If LINE1 receives QL2 and sends it to LINE2 when both EXTCLK1 and EXTCLK2 are disconnected, [upper 4 bits = 0000] + [lower 4 bits = 0000 (QL
2)].

[0038]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an intra-ring clock control system according to one embodiment of the present invention. The alarm detection unit 1 detects an EXTCLK1 disconnection / EXTCLK2 disconnection detection unit 11 that detects an EXTCLK1 input disconnection and an EXTCLK2 input disconnection, and a NO that detects a state in which each NODE in the RING system cannot operate as a normal ADM device.
A DE_FAIL detection unit 12.

The NDID / NDSEQ table 2 is as shown in Table 2
Has node sequence information such as

[0041]

[Table 2]

NDID of NDID / NDSEQ table
Is based on ITU-T regulations G. An ID number 841 is set individually for each ADM in the RING system, and 0 to 15 can be arbitrarily set. However, setting the same ID number for different ADMs within a RING is prohibited.

The NDSEQ indicates chain information of ADMs in a RING, and sets up to 16 units that can be connected as a RING system from 0 to 15. In each NODE, NDID is sequentially applied in the direction of LINE1 by setting the own NODE to NDSEQ = 0.

The PL / QL table 3 has Q as shown in Table 1.
Holds the set values of L and PL.

The NDID minimum value detecting section 4 refers to the PL information of EXTCLK from the PL / QL table 3 and
If EL, stop further processing; otherwise, ND
NDSEQ = 0 with reference to ID / NDSEQ table 2
Is determined to be the minimum value of all NODEs.

The PL / QL processing unit 5 outputs the corresponding EXTCLK
Is detected whether or not QL and PL are the highest levels.

The S1 byte generation / transmission unit 6 generates the S1 byte and transmits it to LINE1 and LINE2. FIG.
5 is a flowchart illustrating the operation of the in-ring clock control system of the present invention.

In each NODE of the RING system,
LINE is selected as the synchronization source clock, and the LINE is selected.
If QL2 * has been received, QL2 * is transmitted to the opposite LINE via PL / QL processing unit 5 as it is (step A0 → step A9).

The S1 byte generating / sending unit 6 performs PL / QL
From Table 3, EXTCLK1 = NSEL and EXTC
If the information LK2 = NSEL is obtained, the upper 4 bits of the S1 byte = "0000" is generated and transmitted (step A1 → step A7).

In the EXTCLK1 disconnection / EXTCLK2 disconnection detecting section 11, EXTCLK1 disconnection and EXTCLK2 disconnection are performed.
Even when disconnection is detected, the upper 4 bits of the S1 byte = "000"
0 ”is generated and transmitted (step A2 → step A
7).

In step A1, either one of NSEL
If not, and if the disconnection has not been detected in step A2, the operation proceeds to the operation of the NDID minimum value detector 4. Here, it is determined whether the NDID for NDSEQ = 0 is the minimum value among all the NDIDs, and if not, step A7 is executed.

Where NDID for NDSEQ = 0
When the NODE for which is determined to be the smallest is in the alarm generation state by the NODE_FAIL detection unit 12, that is, in a state where an appropriate QL value cannot be transmitted (step A3), the information obtained from the NDID / NDSEQ table 2 at the time of the determination. (Step A4).

In the NDID minimum value detector 4, the NDS
If the NDID for EQ = 0 is determined to be the minimum value among all the NDIDs, the own NODE is determined as the master station from a plurality of NODEs having an external input timing source (step A5 → step A6), and the S1 byte is generated. • Upper 4 bits of S1 byte at sending unit 6 = "000"
RING is generated and transmitted (step A8).
QL2 * is transmitted to another NODE in the system.

Referring to FIG. 3, NODE1 and NODE4
A more specific description will be given of the intra-ring clock control system of the present invention in the case where <Signal disconnection 1> occurs between. In FIG. 3, EXTCLK1, EXTCLK2, LINE
1, LINE2 is shown, but the same applies when three or more external clocks and three or more LINEs are used.

At the point in time when a failure such as <Signal interruption 1> has not occurred, the selected clock flows in the direction of the dotted line with an arrow.

However, as shown at the beginning of the timing chart of FIG.
Transmit in the E2 direction. [Upper 4 bits = 0001] +
The NODE that has received the S1 byte of [lower 4 bits = 0000 (QL2)] recognizes this as a higher QL value (denoted as QL2 *) instead of normal QL2.

Referring to the timing chart of FIG.
A signal break occurs between ODE1 and NODE4, and then NO
A signal interruption occurs between DE2 and NODE3, and then NO
A case will be described in which the signal disconnection generated between DE2 and NODE3 is restored.

Between NODE 1 and NODE 4 <Signal loss 1
When> occurs, NODE4 sends QL5 to LINE2 as a Timing Reference having the next highest priority after LINE1 clock because QL7 is received at LINE2 by the internal clock synchronized with HOLDOVER having QL5 and PL14.

In NODE3, EXTCL is received to receive QL5 from LINE1 and QL7 from LINE2.
K1 and EXTCLK2 have a higher QL value priority, and QL2 is transmitted in both directions of LINE1 and LINE2 by an internal clock synchronized with EXTCLK1 having a higher PL value priority.

At this time, LINE2 side is QL in NODE4.
2 is received, the internal clock synchronized with HOLDOVER is synchronized with LINE2, and QL7 is sent to LINE2. LIN in NODE2
Since the QL value input from the E1 side is QL2, LIN
QL2 * is transmitted in the LINE1 direction in synchronization with the LINE2 clock by QL2 * received from the E2 direction. Even in NODE3, the QL value input from the LINE2 side becomes QL2 *, so that L is synchronized with the LINE2 clock.
QL2 * is transmitted in the direction of INE1 and stabilized.

Further, from this state, NODE2 and NOD
When <Signal disconnection 2> occurs during E3, NODE3 generates an internal clock synchronized with EXTCLK1 and sends QL2 to LINE2 as the next highest priority Timing Reference. There is no change in Timing Reference in other NODEs.

From this state, only <signal loss 2> is <recovery>
Then, at the same time as signal disconnection 2 is restored, NODE3 is EXTCL
QL2 is transmitted in the direction of LINE2 by the internal clock synchronized with K1, and NODE2 transmits QL2 * in the direction of LINE1 by the internal clock synchronized with LINE2.

NOD receiving QL2 * from NODE2
E3 is QL in the direction of LINE2 to synchronize with LINE2.
7 is returned and QL2 * is transmitted in the LINE1 direction.

At this time, NODE2 is changed from LINE1 to QL.
2 is received, but QL2 * from LINE2 is given priority, so that the synchronization state of the clock in the device does not change and stabilizes,
Does not fall into vibration continuation.

[0065]

According to the present invention described above, a plurality of A
In a ring system that includes a DM (Add-Drop Multiplexer) node and a clock supply device that supplies a clock to the ADM node, a reception synchronization message (SSM (Synchronization)
Status Message))
The highest quality clock can be set to avoid g Loop.

[Brief description of the drawings]

FIG. 1 is a block diagram of a ring clock control system of the present invention.

FIG. 2 is a flowchart for explaining the operation of the ring clock control system of the present invention.

FIG. 3 is a diagram for explaining a state in which a signal interruption that has occurred later out of two signal interruptions has been restored in the ring clock control system of the present invention;

FIG. 4 is a timing chart for explaining a state in which a signal interruption that has occurred later out of two signal interruptions has been recovered in the ring clock control system of the present invention;

FIG. 5: 4NODE-RIN in a state without signal interruption
Conceptual diagram of G system

FIG. 6 is a timing chart for explaining a state in which the signal interruption that has occurred after two of the signal interruptions that have occurred in two places has been recovered in the 4NODE-RING system of FIG. 5;

FIG. 7 is a conceptual diagram for explaining a state in which a signal interruption that has occurred later from two signal interruptions has been recovered in the 4NODE-RING system of FIG. 5;

FIG. 8 is a conceptual diagram for explaining a timing loop that occurs after the signal interruption that has occurred after two of the signal interruptions that have occurred in two places in the 4NODE-RING system of FIG. 5;

[Description of Signs] 1 Alarm detection unit that collects and issues various alarms in NODE 11 EXTCLK1 disconnection / EXTCLK2 disconnection detection unit 12 NODE-FAIL detection unit 2 NDID / NDS that stores node sequence information
EQ table 3 PL / QL table for storing PL / QL values 4 NDID for NDSEQ = 0 out of all NDIDs
NDID minimum value detection unit that determines whether it is the minimum value 5 PL that sends out QL2 * obtained from LINE CLK
・ QL processing unit 6 S1 byte generation / transmission unit

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (6)

[Claims] 1. A clock for a ring system comprising a plurality of ADM nodes and a plurality of external clock supply devices, and supplying an external clock from the plurality of external clock supply devices to two or more ADM nodes of the plurality of ADM nodes. A control system, wherein an ADM node having a node identifier (NDID) having a minimum value among ADM nodes having a node sequence number (NDSEQ) of zero is a master node that supplies the clock to the ring system. And ring clock control system. 2. A clock control system for a ring system comprising a plurality of ADM nodes and a plurality of external clock supply devices, and supplying a clock from said plurality of external clock supply devices to at least two ADM nodes of said plurality of ADM nodes. In the system, each of the ADM nodes includes: an alarm detection unit that detects an input interruption of an external clock;
NDSEQ table, Timing Reference of the plurality of nodes
The PL / QL table storing the QL and PL of the external clock is referred to, and if the PL of the external clock is NSEL, the processing is stopped; otherwise, the NDID / NDSEQ table is referred to. NDSE
An NDID minimum value detection unit that determines whether the NDID for Q = 0 is the minimum value of all NODEs, and a PL / QL processing unit that detects whether QL and PL of the external clock are at the highest level. S1 which generates a byte and sends it to the ring system
An ADM node that includes a byte generation / transmission unit, and detects that the input of the external clock has been interrupted;
The ADM node loads the upper 4 bits of the S1 byte with external clock input disconnection information and loads the lower 4 bits with QL and sends it to the ring system. The ADM node receiving the S1 byte loads the lower 4 bits. A clock control system in a ring, which recognizes a given QL as a higher-level QL. 3. The clock control of a ring system comprising a plurality of ADM nodes and a plurality of external clock supply devices, and supplying a clock from the plurality of external clock supply devices to two or more ADM nodes among the plurality of ADM nodes. An ADM node that detects the external clock input disconnection, loads the external clock input disconnection information in the upper 4 bits of the S1 byte and loads the QL in the lower 4 bits, and sends it to the ring system. The ADM node receiving the S1 byte uses a clock control system in a ring that recognizes the QL loaded in the lower 4 bits as the upper QL. Select as clock,
If the QL has not been received from that LINE, if at least one LINE is not NSEL or if at least one LINE is not disconnected, ND
It is determined whether or not the NDID for SEQ = 0 is the minimum value among all the NDIDs. If not, the upper 4 bits of the S1 byte are loaded with a first status of input disconnection, and the lower 4 bits are loaded with a QL smaller than 2. Transmitting the NDID to NDSEQ = 0 and determining the own NODE as a master station from among a plurality of NODEs having an external input timing source, for the NODE for which NDID for NDSEQ = 0 is determined to be the minimum value among all NDIDs; A clock control method, characterized in that the station loads the second status of the input disconnection in the upper 4 bits of the S1 byte and transmits a QL value of 2 in the lower 4 bits as a QL value of 2. 4. The method according to claim 3, wherein one LINE is selected as a synchronization source clock, and when the QL is received from the LINE, the QL is transmitted to another LINE as it is. Clock control method. 5. The clock control method according to claim 3, wherein when an alarm is generated from a NODE for which NDID for NDSEQ = 0 is determined to be the minimum, information of the NODE is masked. 6. The ADM node that receives the QL value 2 loaded in the S1 byte from one LINE, and sends the QL value 2 loaded in the S1 byte to another LINE to the upstream node that transmitted the S1 byte. 4. The clock control method according to claim 3, wherein the data is returned using the one LINE while the QL value is set to 7.