JP2002076290A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which a large stress is less likely to be generated, in an interface between a metal of a storage capacity and a ferroelectric. SOLUTION: A switching transistor is formed in the semiconductor substrate. As the storage capacity connected to this transistor, a lower electrode, a dielectric film connected to the lower electrode, and an upper electrode contacted with the dielectric film, are formed. In this case, at least one of each of mean particle sizes of crystal grain boundaries of the lower electrode, the dielectric film and the upper electrode is made smaller than one-tenth of the largest width of the lower electrode. Thus, stresses generated in the interface are diffused in the bonding surfaces of the grain boundaries.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using a ferroelectric for a storage capacitor, and more particularly to a structure of the storage capacitor.

[0002]

2. Description of the Related Art Semiconductor memory devices such as nonvolatile memory devices utilizing the ferroelectricity of a dielectric thin film have been developed.
Semiconductor memory devices using this ferroelectric material include non-contact IC cards (RF-
ID, TAG), etc., and is expected. For example, in a nonvolatile memory device, a device having a structure in which a storage capacitor portion having a metal-ferroelectric-metal (MFM) structure is disposed above a switching transistor having a metal-oxide-semiconductor (MOS) structure has been put to practical use. I have. In this MFM structure, a conductive oxide may be used instead of the metal electrode (M). The non-volatile memory device having the MFM structure includes:
It is considered to be the most practical device structure to date because of the advantage of relatively easy device formation.

[0003] As with other semiconductor memory devices, high integration of non-volatile memory devices has been promoted. In high integration, the projected area (occupied area) of the storage capacitor portion on the semiconductor substrate is reduced. However, a signal margin must be secured, and the capacitance value of the storage capacitor section needs to be a certain value or more. Therefore, the shape of the interface between the metal and the ferroelectric is changed to 1
From a flat surface to a large number of flat surfaces or curved surfaces, the area of the interface is set to be the same even if the occupied area is reduced.

[0004]

In the manufacture of a nonvolatile memory device, a ferroelectric film suffers damages such as damage during etching, hydrogen damage in a reducing process, and stress damage from an upper laminated film, and thus has poor electrical characteristics. Heat treatment is performed to alleviate these stresses and restore the characteristics because of deterioration.

However, since the shape of the interface between the metal and the ferroelectric is changed to a large number of planes or curved surfaces, a large stress is generated on the entire surface and a local area of the interface. In some cases, crystal defects originating from the interface or interface occur, and the electrical characteristics of the non-volatile memory device deteriorate.

[0006] In order to solve the above problems, an object of the present invention is to provide a semiconductor memory device in which a large stress is hardly generated at an interface between a metal and a ferroelectric in a storage capacitor portion.

[0007]

That is, a first feature of the present invention for solving the above-mentioned problems is that a switching transistor provided on a semiconductor substrate, a first bottom portion having a back surface connected to the transistor, and a first transistor having a back surface connected to the switching transistor are provided. A lower electrode having a first side wall electrically connected to the first bottom, a second bottom having a back surface in contact with the surface of the first bottom, and a second electrode having an outer surface in contact with the inner surface of the first side wall; A semiconductor memory device comprising: a dielectric film having a side wall and made of a ferroelectric; and an upper electrode having a bottom surface in contact with a surface of the second bottom portion and a side surface in contact with an inner surface of the second side wall. , At least one of the average grain sizes of the lower electrode, the upper electrode, and the crystal grain boundary of the dielectric film is smaller than 1/10 of the maximum width of the lower electrode. As a result, the storage capacitor section is composed of the lower electrode, the dielectric film and the upper electrode. The capacity can be increased by the so-called bowl-shaped lower electrode having the bottom and side walls and the dielectric film, but the stress also increases. Therefore, by setting the average grain size of each of the crystal grain boundaries of the lower electrode, the dielectric film, and the upper electrode as described above, it is possible to disperse the stress generated at the interface at the bonding surface between the grain boundaries.

The first feature of the present invention is more effective when at least one of the maximum thickness of the lower electrode and the maximum thickness of the dielectric film is smaller than one third of the maximum width. Thereby, the accumulation in the thickness direction of the deformation of the grain boundary due to heat treatment or the like that causes stress can be suppressed.
Further, stress generated at the interface between the lower electrode and the ferroelectric can be reduced.

The first feature of the present invention is more effective when the non-oriented component of the crystal of the dielectric film is 50% or more. Here, the “non-oriented component” refers to the intensity I1 of the strongest line in the powder X-ray diffraction pattern and the most specific orientation component of the ferroelectric X-ray diffraction pattern in the ferroelectric crystal orientation. It is the ratio of the intensity I2 to the sum of the intensity I2 of the component exhibiting strong orientation. This allows
Since various crystal planes are exposed on the surface of the ferroelectric film, stress generated at the interface between the electrode and the ferroelectric can be dispersed.

A second feature of the present invention is that a switching transistor provided on a semiconductor substrate, a first bottom portion connected to the back surface of the switching transistor, and a first side wall electrically connected to the first bottom portion are provided. Having the lower electrode and the first
A dielectric film made of a ferroelectric material having a second bottom portion whose back surface is in contact with the front surface of the bottom portion and a second side wall whose outer surface is in contact with the inner surface of the first side wall, and is in contact with the surface of this second bottom portion A semiconductor memory device having an upper electrode having a bottom surface and a side surface in contact with an inner surface of a second side wall, wherein at least one of the volume densities of the lower electrode and the upper electrode is smaller than the volume density of the dielectric film. is there. The polarization of the ferroelectric is inverted in the operation of the ferroelectric memory, but the amount of polarization is limited by an external stress. In order to alleviate this stress, the stress is alleviated by reducing the volume density of at least one of the upper and lower electrodes to make the structure easily deformable.

A second feature of the present invention is more effective when at least one of the lower electrode and the upper electrode has a gap. Here, the “gap” is a void. The term "voids" does not mean only those that exist inside, but also those that appear on the surface, such as depressions and chips. By arranging voids where stress is likely to occur, generation can be suppressed. Further, even if stress occurs, the void can be deformed to disperse the stress.

The second feature of the present invention is more effective when the lower electrode has a gap near the first bottom and the first side wall. This place is a place where stress is likely to be generated, and by arranging a gap here, generation of stress can be suppressed.

The second feature of the present invention is more effective when the upper electrode has a void inside. Thus, even if stress is generated, the gap can be deformed to disperse the stress.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor device according to an embodiment of the present invention and a method for manufacturing the same will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. In addition, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from actual ones.

FIG. 1 is a sectional view of a semiconductor memory device according to a first embodiment of the present invention. The semiconductor memory device according to the first embodiment of the present invention includes a switching transistor formed on a p-type semiconductor substrate 1 and having a gate electrode 6 also functioning as a word line;
The transistor is composed of a storage capacitor section 14 connected to the source region 4 of the transistor and the lower electrode 11 and a bit line 9 connected to the drain region 3 of the transistor.

The switching transistor includes a gate insulating film 5 in surface contact with the upper surface of the substrate 1, a gate electrode 6 in surface contact with the upper surface of the insulating film 5, an upper surface of the gate electrode 6, and an interior including the upper surface of the substrate 1. position and in that the n ⁺ -type drain region 3 reaches up to the lower portion of the gate electrode 6 is a right end, n ⁺ type left end located therein has led to a lower portion of the gate electrode 6 including the upper surface of the substrate 1 A source region 4, an n ⁺ -type drain region 3 including the upper surface of the substrate, the left side surface of which is in surface contact with the regions 9 and 72 and located above the region 1; And a field oxide film 2 arranged to surround the periphery of the region 4. In the following embodiments, the switching transistor is described as an n-channel metal-insulator-semiconductor (MIS) field-effect transistor (FET) unless otherwise specified. Note that a p-channel MISFET may be used, in which case the conductivity type of each semiconductor region may be reversed. That is, an n-type semiconductor region in an n-channel MISFET may be treated as a p-type semiconductor region in a p-channel MISFET.
A p-type semiconductor region in an ISFET may be treated as an n-type semiconductor region in a p-channel MISFET.

The bit line 9 is arranged on the first interlayer insulating film 15 and is connected to the drain region 3 by a plug 7 penetrating the film 15. The second on the bit line 9 and the film 15
An interlayer insulating film 16 is provided.

The storage capacitor portion 14 has a bowl-shaped lower electrode 11 having a bottom portion and a side wall portion, a bottom portion having a back surface in contact with the bottom surface of the electrode 11, and a side wall portion having an outside contact inside the side wall portion of the electrode 11. The ferroelectric body 12 includes a bowl-shaped ferroelectric material 12 and an upper electrode 13 whose bottom surface is in contact with the bottom surface of the ferroelectric material 12 and whose side surface is in contact with the inside of the side wall of the ferroelectric material 12. Lower electrode 11
Is covered with a barrier layer 10 having conductivity, and the lower electrode 11 and the barrier layer 10 are electrically connected. The barrier layer 10 is disposed on the second interlayer insulating film 16 and is connected to the source region 4 by a plug 8 penetrating the films 15 and 16. A third interlayer insulating film 17 is disposed on the side of the storage capacitor unit 14, and a fourth interlayer insulating film 17 is formed on the storage capacitor unit 14.
An interlayer insulating film 18 is provided.

In the semiconductor memory device according to the first embodiment of the present invention, with respect to the switching transistor, an open / close signal is input to the gate electrode 6 also serving as a word line, thereby making the drain region 3 and the source region 4 conductive. Or open it. By inputting the data signal to the bit line 9 during conduction, the data signal propagates to the storage capacitor unit 14 and is stored as a small amount of charge. Also,
The stored signal is output to the bit line 9 by conducting again. On the other hand, the data signal stored by the release is held. If the ferroelectric substance 12 is inverted when the data signal is input and the data signal is stored by the polarization having the hysteresis characteristic, the data signal is retained regardless of conduction or opening. Will have.

FIG. 2 is an enlarged view of the storage capacitor section 14. In the lower electrode 11, the grain boundaries 20 are gathered and connected to each other. The ferroelectric body 12 is also an aggregate of grain boundaries 21 and the grain boundaries 21 are connected to each other. The upper electrode 13 is also an aggregate of grain boundaries 22, and the grain boundaries 22 are connected to each other. With respect to the longest diameter L of the opening on the upper surface of the storage capacitor section 14, the average particle diameter R of the grain boundary 20
20 is set to the relationship of Equation 1. By setting as described above, two or more grain boundaries 2 are necessarily formed in the thickness direction of the lower electrode 11.
0 can be arranged. Then, a bonding surface where the two or more grain boundaries 20 are bonded to each other is generated.

R20 <L / 10 Expression 1 The stress generated at the interface between the lower electrode 11 and the ferroelectric 12 is dispersed on the bonding surface where the grain boundaries 20 are bonded. As a result, peeling at the interface can be prevented.

Similarly, the average grain size R21 of the grain boundary 21 is expressed by the following equation (2).
And the average grain size R22 of the grain boundary 22 is set to the relationship of the equation (3).

R21 <L / 10 (Equation 2) R22 <L / 10 (Equation 3) As a result, the stress generated at the interface between the lower electrode 11 and the ferroelectric 12 and the upper electrode 13 and the ferroelectric 12 Stress generated at the interface between the grain boundaries 21 and the joining surface where the grain boundaries 22 are joined to each other. And peeling at these interfaces can be prevented. Conversely, in the ferroelectric substance 12 and the electrode films 11 and 13 having crystal diameters exceeding the relations of the formulas 1 to 3, a large change in crystal shape occurs during heat treatment, and it is difficult to maintain the shape before heat treatment. By satisfying the relations of Expressions 1 to 3, a polarization amount of the ferroelectric substance 12 of 10 μC / cm ² or more was obtained. With this polarization amount, good holding and reading operations can be performed in the memory device.

Further, the film thickness T11 of the thickest portion of the lower electrode 11 is set to the relation of the formula 4 with respect to the longest diameter L of the opening of the storage capacitor portion 14.

T11 <L / 3 (Equation 4) As described above, by suppressing the thickness T11 of the lower electrode 11 to a certain value or less, the deformation of the grain boundary 20 due to heat treatment or the like that causes a stress in the thickness direction can be prevented. Accumulation can be kept small. As a result, the lower electrode 11 and the ferroelectric
Stress generated at the interface of the substrate can be reduced.

Similarly, the film thickness T12 of the thickest part of the ferroelectric substance 12 is set to the relation of the equation (5).

T12 <L / 3 (Equation 5) This also makes it possible to reduce the stress generated at the interface between the lower electrode 11 and the ferroelectric substance 12. By dispersing the stresses associated with the respective crystal layers 11 and 12, it is possible to avoid deformation of the film. By satisfying the relations of Expressions 4 and 5, the ferroelectric substance 12
A polarization amount of 10 μC / cm ² or more was obtained.

That is, if the longest diameter L of the opening is 500 nm, the average particle size R21 of the ferroelectric substance 12 is less than 50 nm,
Preferably, it may be set to about 40 nm. Electrode film 11
And 13 may also be set to an average particle size of less than 50 nm, preferably around 25 nm. The maximum thickness T12 of the ferroelectric 12 is less than 167 nm, preferably 100
It may be set to around nm. Maximum film thickness T of lower electrode 11
11 may be set to less than 167 nm. Preferably 1
It is set to around 10 nm.

Further, regarding the crystal orientation of the ferroelectric substance 12, the strongest orientation component among the specific orientation components of the X-ray diffraction pattern of the ferroelectric substance 12 with respect to the intensity I1 of the strongest line in the powder X-ray diffraction pattern. It is desirable to set the intensity I2 of the component showing the property so as to have the relationship of Expression 6. As a result, various crystal planes are exposed on the surface of the film of the ferroelectric substance 12, so that stress generated at the interface between the electrodes 11, 13 and the ferroelectric substance 12 can be dispersed.

0.5> I2 / (I1 + I2) Equation 6 Conversely, a crystal having a high degree of orientation in one direction undergoes greater deformation in a certain direction than the other, and therefore receives the largest stress. become. As a result, the characteristics at the part which receives the most stress are remarkably inferior to those at other places, and high reliability cannot be obtained. By satisfying the relationship of Expression 6, a polarization amount of the ferroelectric 12 of 10 μC / cm ² or more was obtained.

Next, a method of manufacturing the semiconductor memory device according to the first embodiment of the present invention will be described.

(1) First, as shown in FIG. 3A, a switching transistor was formed. p-type silicon (S
i) A field oxide film 2 made of a silicon oxide film (SiO ₂ ) was formed on a substrate 1 by a selective oxidation (LOCOS) method. Next, a gate insulating film 5 was formed by thermally oxidizing the substrate 1. An n ⁺ type polysilicon film was formed by a thermal chemical vapor deposition (CVD) method, and a gate electrode 6 was formed by a photolithography method and a reactive ion etching (RIE) method. Ion implantation was performed on the substrate 1 using the oxide film 2 and the electrode 6 as a mask, followed by heat treatment to form a drain region 3 and a source region 4.

Next, as the first interlayer insulating film 15, a silicon oxide film is formed by plasma enhanced CVD (P-CVD).
Formed by the method. A contact hole was formed in the film 15 above the region 3, and a plug 7 of doped polysilicon was formed in this hole. Then, the bit line 9 was formed in the same manner as the gate electrode 6. A second interlayer insulating film 16 was formed on the film 15 in the same manner as the film 15. Films 15 and 1 over region 4
6 was provided with a contact hole, and a tungsten (W) plug 8 was formed in this hole. Third interlayer insulating film 17
Was formed on the film 16 in the same manner as the film 15.

(2) As shown in FIG. 3B, an opening 23 was formed by lithography and RIE so that the plug 8 was exposed.

(3) As shown in FIG. 4A, a compound of titanium nitride and aluminum nitride (TiA
1N) was formed to a thickness of about 20 nm by a sputtering method. Heat treatment was performed in ammonia gas at 800 ° C. to enhance the barrier properties. An iridium oxide (IrO ₂ ) film was formed as the lower electrode 11 by a sputtering method. Metal-organic CVD (MOCVD) on this electrode 11
A SrBi ₂ (Ta, Nb) ₂ O ₉ film was formed by using a method, and crystallization was performed by heat treatment to form a ferroelectric substance 12.

X-ray diffraction was performed on the ferroelectric substance 12 in this state. The strongest line in the powder X-ray diffraction pattern (1
05) The strength I1 was 6,500. In contrast, c
The intensity I2 of the strongest line (00 10) of the axial orientation is 5000
Met. These strengths satisfied the conditional expression of Expression 6.

(4) As shown in FIG. 4B, the upper electrode 13 was formed in the same manner as the lower electrode 11.

(5) Finally, as shown in FIG. 1, the barrier layers 10 to 13 existing on the film 17 were removed by chemical mechanical polishing (CMP) to complete the storage capacitor section 14. A fourth interlayer insulating film 18 was formed on the film 17 and the capacitor 14 in the same manner as the film 15. Capacity part 1
Heat treatment is performed for the purpose of removing the stress generated in No. 4.
The heat treatment may be performed at a temperature of 700 ° C. or less and within a range of one hour. In this range, the grain boundaries 20 to 22 do not grow and the grain sizes R21 to R22 do not increase.
Therefore, in order to suppress solid phase growth, it is preferable to lower the temperature and shorten the time. In order to further satisfy the conditional expression 6 for the X-ray diffraction, it is preferable that the rate of temperature increase in the heat treatment be 100 ° C./min or more. As a result, the solid phase growth during the temperature rise can be suppressed as much as possible, and the strength of the strongest line does not increase.

The obtained memory device can be driven at 2 V or less, and no defective bit was generated by 10E10 operations.
Read pulse 80nsec, Write pulse 120n
In the case of sec, sufficient record retention characteristics were obtained at a non-defective rate of 80% or more.

It was confirmed from SEM observation of the laminated section that there was no abnormality in the shape. Further, the longest diameter L of the opening was 500 nm.
The average particle size R21 of the ferroelectric material 12 is 40 nm,
And 13 were 25 nm in average particle diameter, the maximum thickness T12 of the ferroelectric 12 was 100 nm, and the maximum thickness T11 of the lower electrode 11 was 110 nm.

In the ferroelectric memory of the present invention, since the conditions for relaxing the stress in the capacitor portion 14 are set, the layers are less likely to be peeled off even during the lamination in a later step.
Since no abnormal stress is applied to No. 2, deterioration of the amount of polarization can be minimized. Since the capacitor section 14 can maintain a sufficient polarization margin even if it is miniaturized, a large-capacity ferroelectric memory can be mass-produced.

(Second Embodiment) FIG. 5 is a sectional view of a semiconductor memory device according to a second embodiment of the present invention. Similarly to the semiconductor memory device according to the first embodiment, the semiconductor memory device according to the second embodiment of the present invention is formed on the p-type semiconductor substrate 1 and the switching in which the gate electrode 6 also functions as a word line. It comprises a transistor, a storage capacitor portion 14 in which the lower electrode 11 is connected to the source region 4 of the transistor, and a bit line 9 connected to the drain region 3 of the transistor.

The switching transistor is the same as the transistor of the first embodiment.

The bit line 9 is arranged on the third interlayer insulating film 17 and is connected to the drain region 3 by a plug 7 penetrating through the films 15 to 17. On the bit line 9 and the film 17, a fourth interlayer insulating film 18 is arranged.

The storage capacitor section 14 is the same as the storage capacitor section of the first embodiment. A part of the bottom surface of the bottom of the lower electrode 11 is in contact with the barrier layer 25 having conductivity. Lower electrode 1
1 and the barrier layer 25 are conductive. The barrier layer 25
It is connected to the source region 4 by a plug 24 penetrating the film 15. The storage capacitor unit 14 is disposed on the film 15.
A film 16 is arranged on the side of the capacitance portion 14, and a film 17
Is arranged.

With the above configuration, the semiconductor memory device according to the second embodiment of the present invention operates similarly to the semiconductor memory device according to the first embodiment.

FIG. 6 is an enlarged view of the storage capacitor section 14 of the semiconductor memory device according to the second embodiment. Also in the second embodiment, grain boundaries 20 to 22 exist as in the second embodiment. And the volume density ρ of the ferroelectric 12
12, the volume density ρ11 of the lower electrode 11 and the volume density ρ13 of the upper electrode 13 are at least Equations 7 and 8
Are set so as to have one of the above relationships.

Ρ12> ρ11 (Equation 7) ρ12> ρ13 (Equation 8) At this time, the upper and lower electrode films 11 and 13 may have the same or different components, but the ferroelectric The upper and lower electrodes 1 correspond to the Young's modulus of the substance constituting the body film 12.
It is preferable that at least one of the electrode film materials 1 and 13 has a small Young's modulus.

That is, the volume density of at least one of the upper and lower electrode films 11 and 13 is made smaller than the volume density of the ferroelectric film 12. Since the ferroelectric film 12 is a part for inverting the polarization which is the basis of the operation of the ferroelectric memory,
The volume density of the film 12 has a large effect on the amount of polarization, and the amount of polarization is limited by external stress. In order to alleviate this stress, it is desirable that at least one of the upper and lower electrode films 11 and 13 has a structure having a low density to alleviate deformation stress. Then, by satisfying the relationship of Expressions 7 and 8, the polarization amount of the ferroelectric 12 is 10 μC /
cm ² or more was obtained.

Further, it is preferable to have the voids 26 to 28 in the electrode films 11 and 13 for stress relaxation. In particular, the gaps 26, 27 near the regions 26, 27 where the deformation stress is greatest, that is, near the bottom surface and the side surfaces of the capacitance portion 14.
It is desirable to have It is also preferable to have a gap 28 inside the upper electrode film 13. With these structures, the deformation stress applied to the ferroelectric film 12 can be reduced as described above.

As long as the entire upper surface of the barrier layer 25 is in contact with the contact portion of the lower electrode film 11, there is no problem even if the bottom surface of the lower electrode 11 other than the contact portion is entirely separated from the interlayer insulating film 19. It is also preferable that the void 28 exists in a portion other than the interface with the ferroelectric film 12 inside the upper electrode film 13.

Further, the surface angle A1 between the interface between the second interlayer insulating film 16 and the third interlayer insulating film 17 and the side surface of the film 11, which is indicated by the dotted line in FIG. When the surface angle A2 is not less than 95 degrees and not more than 160 degrees, it is more effective because stress can be relaxed also in shape.

In the ferroelectric memory of the present invention, since the conditions for relaxing the stress in the three-dimensional structure are set, the layers are unlikely to be peeled off even during the lamination in a later step, and the ferroelectric film 12 has abnormalities. Since no stress is applied, deterioration of the polarization amount can be minimized.

Next, a method of manufacturing a semiconductor memory device according to the second embodiment of the present invention will be described.

(1) First, a switching transistor is formed, but is omitted because it is the same as in the first embodiment.
Next, a silicon oxide film was formed as the first interlayer insulating film 15 by a plasma enhanced CVD (P-CVD) method. A contact hole was formed in the film 15 above the region 4, and a plug 24 of doped polysilicon was formed in the contact hole. At this time, the etch back was performed so that the recess became about 20 nm. The TiAlN barrier layer 25 is formed by sputtering to a thickness of about 30 nm, and 8
Heat treatment was performed in an ammonia gas at 00 ° C.

(2) As shown in FIG. 7B, the barrier layer on the film 15 was removed by the CMP method, and the barrier layer 25 was formed only in the contact hole. The film 16 was formed in the same manner as the film 15.

(3) As shown in FIG.
The barrier layer 25 is exposed by the fee method and the RIE method.
An opening was formed. IrO2 film as lower electrode 11
It was formed by the MOCVD method. On this electrode 11, Sr
Bi₂(Ta, Nb)₂O₉Using MOCVD method for film
A film was formed and crystallized by heat treatment. Ferroelectric 1
2 is PZT (Pb (Zr, Ti) O₃), PL
ZT ((Pb, La) (Zr, Ti) O₃), PLT
((Pb, La) TiO₃) Containing lead (Pb)
Ferroelectric or layer containing bismuth (Bi)
Compound SrBi ₂(Ta, Nb)₂O₉And Bi₄Ti
₃O₁₂, Bi-free layered compound Sr₂(T
a, Nb)₂O₇Etc. could be used. Including Pb
In the case of using an oxide having
Where the ferroelectric film 12 and the interlayer insulating film 17 are in direct contact with each other.
Then, in the thermal process, Pb-SiO₂Pb glass in the reaction between
It forms and causes peeling, so it is difficult to
It was necessary to provide a film.

As an upper electrode 13, an IrO ₂ film was formed by MOCV.
Formed by Method D. As for the materials of the electrodes 11 and 13, noble metals such as platinum (Pt), Ir, and ruthenium (Ru) may be used, but if an oxide conductor is used,
Even without the voids 26 to 28, the volume density could be reduced. In addition, there is an advantage that the oxide conductor has no contact effect, and hydrogen damage to the ferroelectric 12 can be reduced.

The gaps 26 to 28 in FIG.
In order to form the electrodes 11 and 13 by the method D, it is preferable to use a supply-limiting condition with poor embedding property so that overhang is easily generated. However, it is preferable to use conditions for controlling the reaction with a good embedding property when forming the ferroelectric substance 12. By using such conditions, the surface angles A3 and A5 are substantially equal, and the surface angles A1
Larger than The surface angles A4 and A6 are substantially equal and smaller than the surface angle A2. Due to this, the void 2
8 is easily formed.

(4) As shown in FIG.
The lower electrode layers 11 to 13 on the film 16 were removed by the P method to complete the capacitance section 14. The film 17 was formed in the same manner as the film 15.

Then, a heat treatment was performed for the purpose of removing the stress generated in the capacitance portion 14. In the heat treatment, a temperature of 70
The test was performed at a temperature of 0 ° C. or less for one hour or less. The atmosphere for the heat treatment was a non-reducing atmosphere. For example, oxygen (O ₂ ), nitrogen (N ₂ ), argon (Ar) and the like were used. When the treatment was performed in this atmosphere, oxygen was released from the oxide conductors of the electrodes 11 and 13, and the volume density could be reduced. A similar effect can be obtained by increasing the heat treatment temperature.

(5) Finally, as shown in FIG. 5, a contact hole is provided in the films 15 to 17 on the region 3 with a precision that does not overlap the capacitance portion 14, and a tungsten (W) plug 7 is formed in this hole. Was formed. Then, the bit line 9 was formed by forming an aluminum alloy film by a sputtering method and by a photolithography method and an RIE method. The fourth interlayer insulating film 18 was formed in the same manner as the film 15. A contact hole was opened and each connection wiring was made.

The obtained memory element could be driven at 2 V or less, and no defective bit was generated by 10E10 operations.
Read pulse 80nsec, Write pulse 120n
In the case of sec, sufficient record retention characteristics were obtained at a good product rate of 70% or more.

With these structures, it was possible to obtain the same amount of polarization even if the cell area was reduced by 40% as compared with the prior art.

From the SEM observation of the cross section of the laminated structure, it was confirmed that voids 26 and 27 were formed at the corners of the bottom and side surfaces of the opening, and that there was a void 28 in the upper electrode 13 which is considered to have been generated during CVD film formation. No voids were found in the dielectric film 12, indicating that the density was increased.

As described above, the present invention has been described with reference to the two embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention.

The storage capacitor section 14 of the present invention comprises plugs 8, 2
The lower electrode 11 may be formed on the field oxide film 2 via the interlayer oxide film 19 instead of using the lower electrode 4 instead of the lower electrode 11.

From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.

[0069]

As described above, according to the present invention,
It is possible to provide a semiconductor memory device in which a large stress hardly occurs at the interface between the metal and the ferroelectric in the storage capacitor portion.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a capacitor of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a process sectional view (part 1) for describing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a process sectional view (part 2) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a sectional view of a capacitance section of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a process sectional view (part 1) for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a process sectional view (part 2) for describing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Field oxide film 3 Drain region 4 Source region 5 Gate insulating film 6 Gate electrode (word line) 7, 8 Plug 9 Bit line 10 Barrier layer 11 Lower electrode 12 Ferroelectric 13 Upper electrode 14 Storage capacitor 15 1 interlayer insulating film 16 second interlayer insulating film 17 third interlayer insulating film 18 fourth interlayer insulating film 19 interlayer insulating film 20 grain boundary of lower electrode 21 grain boundary of ferroelectric film 22 grain boundary of upper electrode 23 opening 24 Plug 25 Barrier layer 26 to 28 Air gap A1 to A6 Face angle

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F083 AD24 AD31 AD48 FR02 JA12 JA15 JA17 JA36 JA38 JA39 JA43 KA01 KA05 MA06 MA17 MA20

Claims (7)

[Claims] A lower electrode having a switching transistor provided on a semiconductor substrate, a first bottom having a back surface connected to the transistor, and a first side wall electrically connected to the first bottom; A second bottom portion having a back surface in contact with the front surface of the first bottom portion, and a second side wall having an outer surface in contact with an inner surface of the first side wall; a dielectric film made of a ferroelectric; An upper electrode having a bottom surface in contact with the bottom surface and a side surface in contact with the inner surface of the second side wall; and an average particle size of each of the lower electrode, the upper electrode, and a crystal grain boundary of the dielectric film. Wherein at least one of the two is smaller than one tenth of a maximum width of the lower electrode. 2. The semiconductor memory device according to claim 1, wherein at least one of a maximum thickness of said lower electrode and a maximum thickness of said dielectric film is smaller than one third of said maximum width. 3. The non-oriented component of the crystal of the dielectric film is 50%.
3. The semiconductor memory device according to claim 1, wherein the ratio is not less than%. A lower electrode having a switching transistor provided on a semiconductor substrate, a first bottom having a back surface connected to the transistor, and a first side wall electrically connected to the first bottom; A second bottom portion having a back surface in contact with the front surface of the first bottom portion, and a second side wall having an outer surface in contact with an inner surface of the first side wall; a dielectric film made of a ferroelectric; An upper electrode having a bottom surface in contact with the bottom surface and a side surface in contact with the inner surface of the second side wall, wherein at least one of the volume densities of the lower electrode and the upper electrode is at least one of A semiconductor memory device having a smaller volume density. 5. The semiconductor memory device according to claim 4, wherein at least one of said lower electrode and said upper electrode has a gap. 6. The method according to claim 1, wherein the lower electrode is formed between the first bottom and the first bottom.
5. The semiconductor memory device according to claim 4, wherein a gap is provided near a side wall of the semiconductor memory device. 7. The semiconductor memory device according to claim 4, wherein said upper electrode has a void therein.