JP2002074974A - Boosted voltage control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a boosted voltage control circuit in which wasteful current consumption can be prevented and the rewriting time of data for a memory cell can be shortened. SOLUTION: With the electric charge generated by a boosting circuit 51, a capacitor 12 is charged during a setup time and the charge is accumulated, when NTRG is made 'L', a memory cell 54 is charged utilizing electric charges generated by the boosting circuit 51 and electric charges charged in the capacitor 12, also, after the capacitor 12 discharges electric charges, a transistor 11 is turned off by a timing control circuit 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boost voltage control circuit for controlling the application of a boost voltage generated by a boost circuit to a memory cell.

[0002]

2. Description of the Related Art In recent years, flash memories, which are widely used as recording media for information data in computer-applied equipment and are a kind of electrically rewritable recording medium, operate the equipment itself for rewriting the data. A booster circuit that requires a voltage higher than the power supply voltage for performing the data rewriting and generates a high voltage for performing data rewriting with a single power supply is used.

[0005] Such a booster circuit can generate a high voltage, but has a low current supply capability. Therefore, a booster voltage control circuit for efficiently supplying charges to memory cells constituting a flash memory is required. is there.

A conventional boosted voltage control circuit as described above will be described below with reference to the drawings. FIG. 5 (a)
FIG. 2 is a block diagram showing a configuration of a power supply system circuit including a conventional boosted voltage control circuit. In FIG. 5A, reference numeral 51 denotes a booster circuit for generating a voltage equal to or higher than a power supply voltage; 52, a write / erase control for switching and supplying the boosted voltage generated by the booster circuit 51 and the power supply voltage to the memory cell array 55; A circuit 53, a clamp diode for clamping the boosted voltage from the booster circuit 51, a memory cell 54 for storing data, a memory cell array 55 having a configuration in which a plurality of memory cells 54 are connected in a matrix, and a memory cell 54 Row decoder for selecting the word line (WL) of
57, a column decoder for selecting the bit line (BL) of the memory cell 54; 58, a source control circuit for selecting the source line (SL) of the memory cell 54; 59, an output terminal of the booster 51;

As shown in FIG. 5A, a conventional boosted voltage control circuit includes a booster circuit 51, a write / erase control circuit 52 connected to the booster circuit 51, and a clamp diode 5.
3.

The operation of the boosted voltage control circuit configured as described above will be described below with reference to FIG. FIG. 5B is a time chart showing the operation of the boosted voltage control circuit of FIG.

First, a MODE signal is set to a data rewrite mode. Thereby, the booster circuit 51 is driven, and the voltage VPP at the output terminal 59 of the booster circuit 51 increases. VPP is the withstand voltage VPP of the clamp diode 53
When the voltage rises from SET, a current flows through the clamp diode 53 to maintain VPP at VPPSET.

Next, when the NTRG signal becomes "L", VPP or a voltage (VPPL) lower than VPP is applied to the memory cell 54. When writing data, VPP
Is applied from the write / erase control circuit 52 to the WL via the row decoder 56, and VPPL is applied to the BL via the column decoder 57.

When data is erased, VPP is programmed /
SL from the erase control circuit 52 via the source control circuit 58
Is applied. Data rewriting is performed by applying VPP to each terminal of the memory cell.

[0010]

However, in the above-described conventional boosted voltage control circuit, the time (set-up time) from when the MODE signal is set to the data rewrite mode to when the NTRG signal becomes "L" is set. , VP
Clamp diode 5 because P exceeds VPPSET
3 has a problem that a current flows out to the ground side via 3 and wasteful current consumption occurs.

Further, when the NTRG signal becomes "L" and VPP is applied to the memory cell 54, the charge rapidly moves to the gate capacitance or the diffusion capacitance of the memory cell 54, so that the VPP temporarily drops. ΔVPP). Therefore, a time for boosting VPP to VPPSET is needed again, and the desired VPP or VPP
There is also a problem that the time for applying L is delayed, which results in a longer data rewriting time.

The present invention solves the above-mentioned conventional problems. The present invention can reduce the current flowing through the clamp diode, eliminate unnecessary current consumption, and suppress a temporary reduction in VPP. In addition, the present invention provides a boosted voltage control circuit capable of shortening the data rewriting time.

[0013]

In order to solve the above-mentioned problems, a boosted voltage control circuit according to the present invention has a booster circuit for boosting a power supply voltage to generate a boosted voltage higher than the power supply voltage. In a boosted voltage control circuit for controlling application of a boosted voltage from a circuit to a memory cell, a boosted voltage generated by the boosted circuit and the power supply voltage are switched and applied to the memory cell, thereby providing data. A write / erase control circuit for controlling writing and erasing of a transistor; a transistor having a first terminal connected to a connection point between the booster circuit and the write / erase control circuit;
Corresponding to the switching timing of the voltage applied to the memory cell by the erase control circuit,
A timing control circuit for controlling the timing of an on / off operation by applying a signal to the gate; a timing control circuit connected to a second terminal of the transistor; / Capacitor for charging / discharging the charge at the connection point with the erase control circuit.

As described above, during the set-up time, the charge generated by the booster circuit is charged and accumulated in the capacitor, and when NTRG becomes "L", the charge generated by the booster circuit and the charge stored in the capacitor are charged. To charge the memory cell, and after the capacitor discharges the charge, the transistor can be turned off by the timing control circuit.

[0015]

A boosted voltage control circuit according to a first aspect of the present invention has a booster circuit for boosting a power supply voltage to generate a boosted voltage higher than the power supply voltage, and a boosted voltage from the booster circuit. A boosted voltage control circuit for controlling application of the boosted voltage generated by the boosting circuit and the power supply voltage to the memory cell by switching and applying the boosted voltage to the memory cell. A write / erase control circuit to be controlled, a transistor having a first terminal connected to a connection point between the booster circuit and the write / erase control circuit, and switching of a voltage applied to the memory cell by the write / erase control circuit A timing control circuit for controlling on / off operation timing of the transistor by applying a signal to its gate in accordance with the timing; A capacitor connected to a second terminal of the transistor and charging and discharging a charge at a connection point between the booster circuit and the write / erase control circuit when the transistor is turned on by the timing control circuit; .

According to this configuration, during the set-up time, the charge generated by the booster circuit is charged and accumulated in the capacitor, and when NTRG becomes "L", the charge generated by the booster circuit and the capacitor are charged. The memory cell is charged using the stored electric charge, so that the set voltage VPPSET required for rewriting the data in the memory cell is supplied in a shorter time, and further, after the capacitor discharges the electric charge,
The transistor is turned off by the timing control circuit.

According to a second aspect of the present invention, there is provided a boosted voltage control circuit in which the transistor is turned on by the timing control circuit of the first aspect and the write / erase control circuit applies a boosted voltage from the booster circuit to the memory cell. And a boost circuit for boosting the charge of the capacitor through a terminal of the capacitor opposite to the connection end with the transistor.

According to this configuration, during the set-up time, the charge generated by the booster circuit is charged and accumulated in the capacitor, and when NTRG becomes "L", in addition to the charge generated by the booster circuit, the boost is added. By supplying the charged charge of the capacitor boosted by the circuit to the memory cell and charging the same, the set voltage VPPSET required at the time of data rewriting of the memory cell is supplied in a shorter time.

A boosted voltage control circuit according to a third aspect of the present invention includes a booster circuit for boosting a power supply voltage to generate a boosted voltage higher than the power supply voltage, and applying the boosted voltage from the booster circuit to a memory cell. In a boosting voltage control circuit for controlling, a write / erase control circuit for controlling writing and erasing of data by switching and applying a boosted voltage generated by the boosting circuit and the power supply voltage to the memory cell. A transistor having a first terminal connected to a connection point between the booster circuit and the write / erase control circuit, a capacitor connected to a second terminal of the transistor, and the memory by the write / erase control circuit. The voltage levels of the capacitor and the write / erase control circuit are compared with each other in accordance with the switching timing of the voltage applied to the cell. A voltage comparison circuit for controlling the timing of an on / off operation by applying a signal to the gate of the transistor, wherein the capacitor is connected to the transistor when the voltage comparison circuit turns on the transistor. And connected to the transistor so as to charge and discharge a charge at a connection point between the booster circuit and the write / erase control circuit.

According to this configuration, the charge generated by the booster circuit during the setup time is accumulated in the capacitor, and the charge and discharge of the capacitor are controlled by comparing the voltage levels of the capacitor and the memory cell.
Charges are supplied from the capacitors to the memory cells until the capacitors do not become capacitive loads, and an appropriate amount of charges is supplied to the memory cells according to the number of memory cells to be rewritten.

In the boosted voltage control circuit according to a fourth aspect, the transistor is turned on by the voltage comparison circuit according to the third aspect, and the write / erase control circuit applies a boosted voltage from the booster circuit to the memory cell. And a boost circuit for boosting the charge of the capacitor through a terminal of the capacitor opposite to the connection end with the transistor.

According to this configuration, during the set-up time, the charge generated by the booster circuit is charged and accumulated in the capacitor, and when NTRG becomes "L", in addition to the charge generated by the booster circuit, the boost is added. By supplying the charged charge of the capacitor boosted by the circuit to the memory cell and charging the same, the set voltage VPPSET required at the time of data rewriting of the memory cell is supplied in a shorter time.

Hereinafter, a boosted voltage control circuit according to an embodiment of the present invention will be specifically described with reference to the drawings. (Embodiment 1) A boosted voltage control circuit according to Embodiment 1 of the present invention will be described.

FIG. 1 is a block diagram showing a configuration of the boosted voltage control circuit according to the first embodiment. In FIG. 1, reference numeral 12 denotes a capacitor that charges the charge generated in the booster circuit 51 before data rewriting and supplies a charge to the memory cell 54 when data is rewritten. Reference numeral 11 denotes a transistor disposed between the booster circuit 51 and the capacitor 12. , 13 is a timing control circuit for controlling the on / off operation timing of the transistor 11, 14 is a boost circuit for boosting the capacitor 12, 15 is a first node of the capacitor 12, and 16 is an output terminal of the timing control circuit.

Reference numeral 51 is a booster circuit, 52 is a write / erase control circuit, 53 is a clamp diode, 54 is a memory cell, 55 is a memory cell array, 56 is a row decoder,
Reference numeral 7 denotes a column decoder, 58 denotes a source control circuit, and 59 denotes an output terminal of the booster circuit 51. These are the same as those in the conventional example shown in FIG.

As shown in FIG. 1, the boosted voltage control circuit according to the first embodiment includes a booster circuit 51 and a transistor 11
, A capacitor 12, a timing control circuit 13, a boost circuit 14, a write / erase control circuit 52, and a clamp diode 53.

The operation of the boosted voltage control circuit configured as described above will be described below. FIG. 2 is a time chart showing the operation of the boosted voltage control circuit of FIG.

First, the MODE signal is set to the data rewrite mode. Thereby, the booster circuit 51 starts to drive, and the voltage level VP of the output terminal 59 of the booster circuit 51
P rises. At this point, the write / erase control circuit 5
2 outputs a power supply voltage, and thus is in a non-conductive state with respect to VPP. On the other hand, since the output voltage Vsw of the timing control circuit 13 is “H”, the transistor 11 is on.

Therefore, the charge generated by the booster circuit 51 is charged in the capacitor 12 via the transistor 11, and the voltage Vch of the node 15 rises. VPP is the withstand voltage level of the clamp diode 53 (VPPSET)
When the current further rises, a current to the ground side starts to flow through the clamp diode 53, and VPP becomes VPPSET and maintains a constant voltage.

Next, the NTRG signal changes from "H" to "L", whereby the write / erase control circuit 52
The memory cell 54 to which a voltage is applied is selected by the row decoder 56 and the column decoder 57 at the time of conducting data to the PP and further writing data. When data is erased, the memory cell 54 to which a voltage is applied is selected by the source control circuit 58. At the same time, the output voltage Vboost of the boost circuit is applied to the capacitor 12, and the voltage Vch of the node 15 further rises from VPPSET.

The voltage Vch of the boosted capacitor is applied to the selected memory cell 54 in addition to the voltage VPP generated by the booster circuit 51. This gives N
A temporary decrease in VPP that occurs when the TRG signal becomes “L” can be suppressed so as to remain at ΔVPP1 from ΔVPP2 in the related art.

Next, after the capacitor 12 supplies charges to the memory cell 54, the output voltage Vsw of the timing control circuit 13 changes from "H" to "L", whereby
The capacitor 12 whose channel is lower than VPPSET is disconnected from the node 59 to prevent the booster circuit 51 from becoming a capacitive load.

As described above, the current flowing through the clamp diode can be reduced to eliminate unnecessary current consumption, prevent the capacitor from becoming a capacitive load of the booster circuit, and suppress a temporary decrease in VPP. Thus, data rewriting time can be reduced. (Embodiment 2) A boosted voltage control circuit according to Embodiment 2 of the present invention will be described.

FIG. 3 is a block diagram showing a configuration of the boosted voltage control circuit according to the second embodiment. In FIG. 3, reference numeral 21 denotes a voltage comparison circuit that compares the voltage level of the capacitor 12 with the voltage level applied to the word line (WL) of the memory cell 54, and controls the on / off operation of the transistor 11, and 22 denotes a voltage. The output terminal of the comparison circuit 21 and the input terminal 23 of the row decoder 56 are shown.

Incidentally, 11 is a transistor, 12 is a capacitor, 14 is a boost circuit, and 15 is a transistor 11
, Which are the same as those in the first embodiment.

Further, 51 is a booster circuit, 52 is a write / erase control circuit, 53 is a clamp diode, 54 is a memory cell, 55 is a memory cell array, 56 is a row decoder,
7 is a column decoder, 58 is a source control circuit, 59 is an output terminal of the booster circuit 51, and these are the same as those of the conventional example.

As shown in FIG. 3, the boosted voltage control circuit according to the second embodiment comprises a booster circuit 51 and a transistor 11
, A capacitor 12, a voltage comparison circuit 21, a boost circuit 14, a write / erase control circuit 52, and a clamp diode 53.

The operation of the boosted voltage control circuit configured as described above will be described below. FIG. 4 is a time chart showing the operation of the boosted voltage control circuit of FIG.

First, the MODE signal is set to the data rewrite mode. Thereby, the booster circuit 51 starts to drive, and the voltage level VP of the output terminal 59 of the booster circuit 51
P rises. At this point, the write / erase control circuit 5
2 is a non-conductive state with respect to VPP because it is outputting the power supply voltage, while the output voltage Vs of the voltage comparison circuit 21 is
Since w is “H”, the transistor 11 is on.

Therefore, the charge generated by boosting circuit 51 is charged in capacitor 12 through transistor 11, and voltage Vch at node 15 rises. VPP is the withstand voltage level of the clamp diode 53 (VPPSET)
When the current further rises, a current to the ground side starts to flow through the clamp diode 53, and VPP becomes VPPSET and maintains a constant voltage.

Next, the NTRG signal changes from "H" to "L". As a result, the write / erase control circuit 52
The memory cell 54 to which a voltage is applied is selected by the row decoder 56 and the column decoder 57 during data writing. At the time of data erasure, the memory cell 54 to which a voltage is applied is selected by the source control circuit 58.

At the same time, the output voltage Vboost of the boost circuit 14 is applied to the capacitor 12,
Voltage Vch further rises from VPPSET. The voltage Vch of the capacitor 12 boosted by the boost circuit 14 is applied to the selected memory cell 54 in addition to the voltage VPP generated by the boost circuit 51. Thereby, the VP generated when the NTRG signal becomes “L”
The temporary decrease of P is changed from ΔVPP2 as in the past to ΔVPP.
It can be suppressed to stay at PP1.

Next, the result of comparison by the voltage comparison circuit 21 is that the voltage Vch at the node 15 and the voltage Vme at the node 23
m becomes the same voltage level Veq, the voltage Vsw of the node 22 changes from “H” to “L”, and the transistor 1
1 turns off. Thereby, capacitor 12 is disconnected from node 59, and capacitor 12 can be prevented from becoming a capacitive load of booster circuit 51.

As described above, the current flowing through the clamp diode can be reduced to eliminate unnecessary current consumption, prevent the capacitor from becoming a capacitive load of the booster circuit, and suppress a temporary decrease in VPP. Thus, data rewriting time can be reduced.

[0045]

As described above, according to the first aspect of the present invention, the charge generated by the booster circuit is charged and accumulated in the capacitor during the set-up time, and when the NTRG becomes "L", By charging the memory cell using the charge generated by the booster circuit and the charge charged in the capacitor, the set voltage VPPSET required when rewriting the data in the memory cell is supplied in a shorter time, and the capacitor further charges the charge. After discharging, the transistor can be turned off by the timing control circuit.

Therefore, the current flowing through the clamp diode can be reduced to eliminate unnecessary current consumption, prevent the capacitor from becoming a capacitive load of the booster circuit, and suppress a temporary decrease in VPP. In addition, data rewriting time can be reduced.

According to the second aspect of the present invention, the charge generated by the booster circuit is charged and accumulated in the capacitor during the setup time, and the booster circuit is generated when NTRG becomes "L". By supplying the charged charge of the capacitor boosted by the boost circuit to the memory cell in addition to the charge thus charged, the set voltage VPPSET required when rewriting data in the memory cell can be supplied in a shorter time. .

Therefore, the current flowing through the clamp diode can be reduced to eliminate unnecessary current consumption, prevent the capacitor from becoming a capacitive load of the booster circuit, and suppress a temporary decrease in VPP. In addition, data rewriting time can be reduced.

According to the third aspect of the present invention, the electric charge generated by the booster circuit during the setup time can be stored in the capacitor. Therefore, the current flowing through the clamp diode can be reduced, and unnecessary current consumption can be eliminated.

In addition, since the charge and discharge of the capacitor are controlled by comparing the voltage levels of the capacitor and the memory cell, it is necessary to supply the charge from the capacitor to the memory cell until the capacitor does not become a capacitive load. Can be. Therefore, it is possible to prevent the capacitor from acting as a capacitive load of the booster circuit, and to suppress a temporary decrease in VPP.

Further, an appropriate amount of charge can be supplied to the memory cells according to the number of memory cells to be rewritten. Therefore, the electric charge generated by the booster circuit can be used more effectively, and an appropriate amount of electric charge can be supplied according to the load capacitance of the memory cell. This means that when the load capacity is large, the amount of charge supplied from the capacitor also increases. As a result, it is possible to play a role in suppressing a variation in time for applying a voltage necessary for data rewriting, and also to shorten data rewriting time.

According to the fourth aspect of the present invention, during the set-up time, the charge generated by the booster circuit is charged and accumulated in the capacitor, and when the NTRG becomes "L", the booster circuit generates the charge. By supplying the charged charge of the capacitor boosted by the boost circuit to the memory cell in addition to the charge thus charged, the set voltage VPPSET required when rewriting data in the memory cell can be supplied in a shorter time. .

Therefore, the current flowing through the clamp diode can be reduced to eliminate unnecessary current consumption, prevent the capacitor from becoming a capacitive load of the booster circuit, and suppress a temporary decrease in VPP. In addition, data rewriting time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a boosted voltage control circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation in the boosted voltage control circuit according to the first embodiment;

FIG. 3 is a block diagram showing a configuration of a boosted voltage control circuit according to a second embodiment of the present invention;

FIG. 4 is a time chart showing an operation in the boosted voltage control circuit according to the second embodiment;

FIG. 5 is a block diagram showing a configuration of a conventional boosted voltage control circuit and a time chart showing its operation.

[Explanation of symbols]

 Reference Signs List 11 transistor 12 capacitor 13 timing control circuit 14 boost circuit 15 first node of capacitor 16 output terminal of timing control circuit 21 voltage comparison circuit 22 output terminal of voltage comparison circuit 23 output terminal of write / erase control circuit 51 booster circuit 52 writing / Erase control circuit 53 Clamp diode 54 Memory cell 55 Memory cell array 56 Row decoder 57 Column decoder 58 Source control circuit 59 Output terminal of booster circuit

Claims (4)

[Claims] A booster circuit for boosting a power supply voltage to generate a boosted voltage equal to or higher than the power supply voltage, wherein the boosted voltage control circuit controls application of a boosted voltage from the booster circuit to a memory cell; A write / erase control circuit for controlling writing and erasing of data by switching and applying a boosted voltage generated by the booster circuit and the power supply voltage to a memory cell; A transistor having a first terminal connected to a connection point with a control circuit, and a signal to a gate of the transistor in response to switching timing of a voltage applied to the memory cell by the write / erase control circuit. A timing control circuit for controlling a timing of an on / off operation by applying a voltage, the timing control circuit being connected to a second terminal of the transistor, A boost voltage control circuit comprising: a capacitor that charges and discharges a charge at a connection point between the boost circuit and the write / erase control circuit when the transistor is turned on by a control circuit. 2. The transistor is turned on by a timing control circuit, and the terminal on the opposite side of the connection end of the capacitor to the transistor is connected to the write / erase control circuit at the timing of applying the boosted voltage from the booster circuit to the memory cell. 2. The boosted voltage control circuit according to claim 1, further comprising a boost circuit that boosts the charge of the capacitor through the booster. 3. A boosted voltage control circuit for boosting a power supply voltage to generate a boosted voltage equal to or higher than the power supply voltage, wherein the boosted voltage control circuit controls application of a boosted voltage from the booster circuit to a memory cell. A write / erase control circuit for controlling writing and erasing of data by switching and applying a boosted voltage generated by the booster circuit and the power supply voltage to a memory cell; A transistor having a first terminal connected to a connection point with a control circuit, a capacitor connected to a second terminal of the transistor, and a switching timing of a voltage applied to the memory cell by the write / erase control circuit. Correspondingly, each voltage level of the capacitor and the write / erase control circuit is compared, and according to the comparison result, A voltage comparison circuit for controlling the timing of an on / off operation by applying a signal to the gate; and writing the capacitor to the booster circuit via the transistor when the transistor is turned on by the voltage comparison circuit. A boosted voltage control circuit connected to the transistor so as to charge and discharge charges at a connection point with the erase control circuit. 4. A terminal on a side opposite to a connection end of the capacitor with the transistor at a timing when the voltage comparison circuit turns on the transistor and the write / erase control circuit applies a boosted voltage from the booster circuit to the memory cell. 4. The boosted voltage control circuit according to claim 3, further comprising a boost circuit that boosts the charge of the capacitor through the boost circuit.