JP2002074970A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which the power consumption is suppressed independently of a position of a memory cell, the speed is increased, and the timing design is easy. SOLUTION: This device is a semiconductor memory having a decoding circuit 1 fetching a row address signal and generating a memory cell row address decoding signal 9, a decoding circuit 2 generating memory cell group address decoding signals 10a-10p, a memory cell array 3 in which a memory cell group in which plural memory cells are arranged in a matrix state are arranged in a array state making it as a unit, a sense amplifier 4 detecting variation of bit lines connected to a memory cell of the memory cell array 3 selected by a column selecting signal 11 in which a column address signal is decoded and a memory cell row address decoding signal 9 and reading out data, and a read-amplifier 6 detecting minute potential difference of an I/O line connected to the sense amplifier 4. The device is also provided with a control signal generating circuit 8 changing generated timing of a control signal 14 of the read-amplifier 6 in accordance with a selected memory cell group making the row address signals 10a-10p as input.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a large-capacity, high-speed semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 9 shows a conventional semiconductor memory device. 1
Is a decode circuit that takes in a row address signal and generates a row address decode signal group, 2 is a decode circuit that takes in a memory cell group address signal and generates a memory cell group select signal, and 5 is a column circuit that takes in a column address signal and activates a column select signal. 9 is a row address decode signal group, 10 is a memory cell group selection signal, and 11 is a column selection signal.

Reference numeral 3 denotes a memory cell group in which a plurality of memory cells are arranged in a matrix, and a memory cell array in which the memory cells are arranged in an array. Reference numeral 4 denotes a sense amplifier, which is connected to a selected memory cell of the memory cell array 3. Data is read by detecting a change in the bit line. Reference numeral 6 denotes a read amplifier which detects and amplifies a minute potential difference of the I / O line pair 12 connected to the sense amplifier 4. Reference numeral 7 denotes an output circuit that outputs a result read from the memory cell.

Here, the column selection signal 11 has a parasitic capacitance / resistance such as a signal wiring load and a gate load from the vicinity of the decoder circuit 5 to the farthest end.
A signal delay occurs until the column selection signal 11 output from the terminal reaches the farthest end.

The same applies to the I / O line pair 12 which is the output of the sense amplifier 4, and the data read from the memory cell is supplied to the I / O line pair 12 between the farthest end and the vicinity from the read amplifier circuit 6. Also propagates, a signal delay occurs.

For convenience, the column selection signal near the decoder 5 is 11-n, the farthest column selection signal is 11-f, the I / O line pair near the read amplifier 6 is 12-n, and the farthest end is 11-n. In the memory cell array 3, the I / I line pair is 12-f, the memory cell group near the decoder 5 is 3a, and the farthest memory cell group is 3p.

Next, the operation of the circuit of FIG. 9 will be described with reference to FIG. At timing T0, the external clock transits to the H level. In response to this, at timing T1, an H-level one-shot pulse is generated as the column selection signal 11-n. This H-level one-shot pulse is generated by the column selection signal 11 at timing T2 due to wiring delay.
Propagate to -f.

The case where data is read from the memory cells in the memory cell group 3a will be described. The column selection signal 11-n is supplied to the memory cell group 3a
To start reading data from the memory cell at.
At the same time, the read amplifier control signal 14 transitions to the L level to initialize the read amplifier circuit 6 and its output, and stop the potential equalization / precharge of the I / O line pair 12-n.

The data read from the memory cell array 3 is supplied to the I / O via the sense amplifier 4 at a timing T1.
The data is transferred to the O line pair 12-n and propagated to the read amplifier circuit 6.

The case where data is read from the memory cells in the memory cell group 3p will be described. The column selection signal 11-f is supplied at timing T2 to the memory cell group 3p.
Starts reading data from the memory cell at. The read amplifier control signal 14 is already low at the timing T1.
Since the level has transitioned to the level, the read amplifier circuit 6 and its output have been initialized, and the equalization / precharge of the potential of the I / O line pair 12-f has also been stopped. I /
The data read to the O line 12-f is transmitted to the I / O line 12-f.
n, but signal delay occurs due to parasitic capacitance / resistance. The voltage amplitude of the I / O line pair at the time of data transfer is generally set to be as small as possible for the purpose of high-speed data transfer and power consumption reduction. The minimum required voltage level is uniquely determined.

Generally, an I / O line precharge voltage of about 10
% As a specified value, and the read amplifier control signal 14 is transited to the H level (timing T3 in the figure), thereby activating the read amplifier 6 and detecting the minute potential transmitted to the I / O line pair 12-n. The signal is amplified and transferred to the output circuit 7. At the same time, equalization / precharge of the I / O line pair 12-n is started to prepare for the next cycle of data transfer.

Although the equalizing / precharging of the I / O line pair is performed by the equalizing / precharging circuit provided in the read amplifier 6, it occurs when data is transferred from the memory cell group 3p to the read amplifier 6. With a signal delay similar to the one described. That is, the equalization / precharge of the I / O line pair 12-n started at the timing T3 is as follows.
Propagation is delayed by parasitic capacitance / resistance.
Equalization / precharge of the line pair 12-f is completed at timing T4. During this period, the read amplifier control signal 14 needs to be kept at the H level. I
After the equalization / precharge of the / O line pair 12-f is completed (that is, after a sufficient time has elapsed from the timing T4), the external clock transitions to the H level at the timing T5, and the read operation in the next cycle is performed. . Here, even when the memory cell group 3a is selected, the I / O line pair 1
It is necessary to keep the read amplifier control signal 14 at the H level until the equalization / precharge of 2-f is completed.

[0013]

In the semiconductor memory device configured as described above, the cycle of the read amplifier control signal 14 is determined by the timing regardless of the position of the selected memory cell (that is, the difference of the selected memory cell group). T1 to T6. (T1 to T3 = L level, T3 to T6 = H level) When the memory cell group 3a is selected, that is, when data is read from the I / O line pair 12-n, I / O
Since the equalizing / precharging of the O line pair 12-n is stopped during the timings T1 to T3, the charge of the I / O line 12-n which becomes L level is transmitted via the sense amplifier during the timings T1 to T3. And is discharged to the ground level. Here, the timings T1 to T3 are set so that the voltage amplitude of the I / O line pair 12-n is about 10 times the precharge level.
%, The voltage amplitude of the I / O line pair 12-n will be wider than the specified value if the time is longer than the time required for the value to become%. When the memory cell group 3p is selected, that is, when data is read from the I / O line pair 12-f, the delay time until data is propagated to the I / O line pair 12-n is reduced. Considering the timings T1 to T3, the potential amplitude of the I / O line pair 12-n becomes about 10% of the precharge level at the timing T3, but the I / O line pair 12-f is set. Already has a wider amplitude than the specified value. As a result, I / O line pair 1
As the current consumption associated with the charging and discharging of No. 2 increases, the time required to complete the equalizing / precharging increases, which hinders high-speed operation. Further, it is necessary to design the timing of the read amplifier control signal 14 in consideration of the timing of the I / O line which differs depending on the position of the memory cell group to be selected, and furthermore, considering the margin for the manufacturing / operation variation. Depending on the size of the design window, the design window may be very narrow.

The present invention solves the above-mentioned conventional problems. The voltage amplitude of the I / O line is stopped at a specified value irrespective of the position of the memory cell to be selected, thereby reducing power consumption and increasing the reading speed. It is another object of the present invention to provide a semiconductor memory device which facilitates timing design.

[0015]

In order to achieve this object, a semiconductor memory device according to the present invention is characterized in that the generation timing of a read amplifier control signal is shifted depending on the memory array to be selected. By providing the optimum read amplifier control signal according to the position, the current consumption can be suppressed by stopping the voltage amplitude of the I / O line at the specified value, and the readout speed is increased and the timing design is facilitated. .

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to a first aspect of the present invention includes a first decode circuit for receiving a row address signal and generating a memory cell row address decode signal;
A second decode circuit for taking in a row address signal and generating a memory cell group address decode signal; a memory cell array in which a plurality of memory cells are arranged in a matrix in a unit of a memory cell group; A sense amplifier that reads a data by detecting a change in a bit line connected to a memory cell of the memory cell array selected by a column selection signal obtained by decoding an address signal and the memory cell row address decode signal; A semiconductor memory device comprising: a read amplifier that detects and amplifies a minute potential difference between connected I / O lines,
A control signal generation circuit is provided which receives the row address signal as input and changes a generation timing of a control signal of the read amplifier according to a selected memory cell group.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the control signal generation circuit includes a first timing generation section for adjusting an output timing of the control signal by a memory cell group address decode signal. And a first switch unit for activating a memory cell group address decode signal supplied to a first timing generation unit by a control circuit activation signal, wherein the first timing generation unit includes the memory A plurality of delay units having different delay times are arranged in parallel corresponding to the cell group address decode signal.

According to a third aspect of the present invention, there is provided the semiconductor memory device according to the first or second aspect, wherein the corresponding row address decode signal selects the delay time of the delay unit constituting the first timing generator. The position of the memory cell group is
It is characterized in that it is configured to be large when it is far from the read amplifier and small when it is close to the read amplifier.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the first aspect, the control signal generation circuit includes a second switch section activated by a memory cell group address decode signal, and a control circuit activation signal. And a second timing generator comprising a plurality of stages of delay units for delaying the output of the second timing generator, and among the plurality of delay outputs delayed by the second timing generator via the second switch unit. One is selected as the control signal.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the correspondence between the delay unit group, the switch circuit and the row address decode signal constituting the second timing generator is determined by the row address decode signal. When the position of the memory array selected is far from the read amplifier, the switch circuit constituting the second switch unit is turned on so that a signal passed through a number of delay units is used as the control signal. When the distance is close, a switch circuit forming the second switch unit is turned on so that a signal passed through a small number of delay units is used as the control signal.

According to a sixth aspect of the present invention, there is provided a semiconductor memory device, wherein a first decode circuit for taking in a row address signal to generate a memory cell row address decode signal, and a memory cell group address decode signal taking in a row address signal. A memory cell array in which a plurality of memory cells are arranged in a matrix, and a memory cell array in which the memory cells are arranged in an array, a column selection signal obtained by decoding a column address signal, and the memory cell A sense amplifier for reading data by detecting a change in a bit line connected to a memory cell of the memory cell array selected by a row address decode signal and detecting a minute potential difference between an I / O line connected to the sense amplifier And a dummy amplifier with the same current capability as the sense amplifier. And a dummy I / O line connected to the dummy sense amplifier and having exactly the same wiring load as the I / O line, a control circuit activation signal and the dummy I / O line, and the read amplifier is controlled. A control signal generation circuit for generating a control signal, wherein the generation timing of the read amplifier control signal is determined by a signal delay of the dummy I / O line.

According to a seventh aspect of the present invention, in the semiconductor memory device according to the sixth aspect, the control signal generation circuit includes a detection circuit for activating an output by the dummy I / O line, and a control circuit activation signal. A third timing generator for adjusting the delay time by the output of the detection circuit and outputting the control signal, wherein the detection circuit is activated by a reference potential generation circuit and a detection signal activation signal. An output voltage of the reference potential generating circuit is applied to a first input of the first and second inputs of the differential amplifier, and the dummy I / O is applied to a second input. An O line is connected, an output of the detection circuit is supplied from an output side of the differential amplifier circuit, and the delay time is determined according to a logic of an output of the detection circuit.

According to a seventh aspect of the present invention, in the semiconductor memory device according to the seventh aspect, the third timing generator includes a plurality of switch circuits whose on / off states are switched by an output of the detection circuit, and the switch circuit. And delay units connected in series to the input and output paths of the plurality of delay units, and the plurality of delay units have different delay times.

According to a ninth aspect of the present invention, in the semiconductor memory device according to the seventh or eighth aspect, when the differential amplifier circuit is activated by the detection signal activation signal, From the output voltage, the dummy I /
When the level of the O line is low, the delay time of the third timing generator is set as the first delay time, and when the level of the dummy I / O line is higher than the output voltage of the reference potential generating circuit, the third delay time is set.
Is configured such that the delay time of the timing generation section is a second delay time longer than the first delay time.

Hereinafter, embodiments of the present invention will be described with reference to FIGS.
It will be described based on. (Embodiment 1) FIGS. 1 to 3 show (Embodiment 1).

FIG. 1 shows a semiconductor memory device of the first embodiment. The same components as those in FIG. 9 showing a conventional example are denoted by the same reference numerals, and a control signal is generated on the input side of a read amplifier control signal 14. The difference is that a circuit 8 is provided.

The control signal generating circuit 8 is configured as shown in FIG. The control signal generation circuit 8 receives the memory cell group selection signal 10 and generates the read amplifier control signal 14 after being activated by the control circuit activation signal 13, and includes a switch section 15 and a timing generation section 16. And a buffer 17.

The timing generator 16 is composed of delay units 16a to 16p having different delay times. Each of the delay times is determined by the position of the memory array group selected by the memory cell group selection signal 10 (from the read amplifier). Distance).

For example, if the memory cell group selection signal 10a selects a memory array group close to the read amplifier,
The delay time of the delay unit 16a is the shortest or zero, and if the memory cell group selection signal 10p selects the memory array group farthest from the read amplifier, the delay unit 1a
The delay time of 6p is set to correspond to a signal delay generated from the selected memory array group to the read amplifier 6.

The switch unit 15 includes switch circuits 15a to 15a to
15p, and has a one-to-one correspondence with the row address decode signal group 9. That is, the row address decode signal 9a is connected to the switch circuit 15a, the row address decode signal 9b is connected to the switch circuit 15b,..., And the row address decode signal 9p is connected to the switch circuit 15p.

The structure of the semiconductor memory device will be described in more detail with reference to FIG. At timing T0, the external clock transitions to the H level. In response to this, at timing T1, an H-level one-shot pulse is generated in the column selection signal 11-n. The one-shot pulse of H level propagates to the column selection signal 11-f. As described in the conventional example (FIGS. 9 and 10), the column selection signal 11-n and the column selection signal 11-f are used. 11-f
, A signal delay (T2-T1) occurs. (Here, the suffixes -n and -f indicate the case where the selected memory cell is located in a memory cell group close to the read amplifier and the case where the selected memory cell is located in a distant memory cell group as described with reference to FIG. The same applies to the following signals.) A case where data is read from a memory cell in the memory cell array 3-n will be described.

In order to select the memory cell array 3-n, the memory cell group selection signal 10-n is activated.
Therefore, the read amplifier control signal 14 is generated via the delay circuit 16a (small delay time) of the timing generator 16 (for example, corresponds to the memory cell group selection signal 10a in FIG. 2). And the column selection signal 11
-N is activated at the timing T1, and starts reading data from the selected memory cell in the memory cell array 3-n. Here, the read amplifier control signal 1
4 to the L level to initialize the read amplifier circuit 6 and its output, and to initialize the I / O line pair 1
Stop 2-n equalization / precharge. At the time when the potential difference of the I / O line pair 12-n has increased to about 10% of the precharge level by the data read from the memory cell (T3 in the figure), the read amplifier control signal 14 is set to the H level. By making a transition, the read amplifier is activated to start detection / amplification of a minute potential and transfer of data to an output circuit. At the same time, equalization / precharge of the I / O line pair 12-n is started to prepare for the next read operation. The I / O line pair 12-
Although a potential difference also occurs in f, the potential amplitude becomes a sufficiently small value (<10% of the precharge potential) because the read amplifier activating signal 14 can transition to the H level earlier than in the conventional example. Next, the memory cell array 3-
The case where data is read from the memory cell at f will be described. In order to select the memory cell array 3-f, the memory cell group selection signal 10-f is activated.
Therefore, the read amplifier control signal 14 is generated via the delay circuit 16p (large delay time) of the timing generator 16 (for example, corresponds to the memory cell group selection signal 10p in FIG. 2). The column selection signal 11-f is activated at timing T2 due to a wiring delay, and starts reading data from the memory cell selected in the memory cell array 3-f. Here, the timing when the read amplifier control signal 14 transitions to L is T2, which is determined by changing the delay time of the delay unit 16p to the column selection line 11-n.
This is because the delay is adjusted to be equal to the delay time of the column selection line 11-f. Data read from the memory cell to the I / O line pair 12-f has
/ O line pair 12-n. The I / O line pair 12
At the point in time when the potential difference of −n has increased to about 10% of the precharge voltage (T4 in the figure), the read amplifier control signal 14
To a high level to activate the read amplifier circuit 6. The timing at which the read amplifier control signal 14 transitions to the H level is also set by the delay time of the delay unit 16p. At the same time, the I / O line pair 12-n
Of the I / O line pair 12-f between the timing T2 and the timing T4, the potential amplitude generated by the I / O line pair 12-f depends on the wiring capacitance / resistance.
/ O line pair 12-n. However, compared to the conventional example, the read amplifier activation signal 14
Since the delay is adjusted at 6p, the level is sufficiently narrow.

As described above, the timing of the read amplifier control signal 14 in the selection of the memory array 3-n and the selection of the memory array 3-f can be optimized by the delay unit 16, so that the I / O line pair And the power amplitude can be stopped at a specified value to reduce the power consumption, increase the read speed, and facilitate the timing design.

(Embodiment 2) FIGS. 4 to 6 show (Embodiment 2). The semiconductor memory device shown in FIG. 4 is different only in that control signal generating circuit 8 shown in FIG. 1 is replaced by control signal generating circuit 18 having a different internal configuration.

The control signal generating circuit 18 is configured as shown in FIG. Reference numeral 19 denotes a timing generator which has delay units 19a to 19p having the same delay time, and each delay time corresponds to a signal delay time between two adjacent memory array groups.

Reference numeral 20 denotes a switch unit, which is a switch circuit 20a.
20p, and the memory cell group selection signal 10
One to one corresponds to a to 10p. 21 is a buffer circuit.

More specifically, memory cell group selection signal 10a
When the switch circuit 20a is turned on, the switch circuits 20b to 20p are in the off state, and the control circuit activation signal 13 is delayed by the delay unit 19a and supplied to the input of the buffer circuit 21 via the switch circuit 20a. Then, the read amplifier control signal 1 is output to the output of the buffer circuit 21.
4 occurs.

When the switch circuit 20b is turned on by the memory cell group selection signal 10b, the switch circuit 20
a, 20c to 20p are off, and the control circuit activating signal 13 is delayed by delayers 19a, 19b, supplied to the input of the buffer circuit 21 via the switch circuit 20b, and output to the output of the buffer circuit 21. A read amplifier control signal 14 is generated.

The same applies when the switch circuits 20c to 20p are turned on by the memory cell group selection signals 10c to 10p. The configuration of the semiconductor memory device will be described in more detail with reference to FIG.

First, at timing T0, the external clock goes high.
In response to this, at the timing T1, an H-level one-shot pulse is generated in the column selection signal 11-n. This H-level one-shot pulse is
As described in the first embodiment, the signal delay (T2-
T1) propagates to the column selection signal 11-f.

The case where data is read from the memory cells in the memory cell group 3a will be described. To select the memory cell group 3a, the memory cell group selection signal 10
-N is activated (corresponding to, for example, the memory cell group selection signal 10a in FIG. 5). Therefore, the read amplifier control signal 14 is generated via the delay circuit 19a of the timing generator 19. Then, the column selection signal 1
1-n is activated at timing T1, and starts reading data from the memory cells selected in the memory cell group 3a. Here, the read amplifier control signal 14 is caused to transition to the L level, thereby initializing the read amplifier circuit 6 and its output, as well as the I / O line pair 12-.
Stop equalization / precharge of n. According to the data read from the memory cell, the I / O line pair 1
At the point in time when the potential difference of 2-n has increased to about 10% of the precharge level (timing T3 in the figure), the read amplifier control signal 14 is transitioned to the H level to activate the read amplifier, thereby detecting / detecting the minute potential. Start amplification and data transfer to the output circuit. At the same time, the I / O line pair 12-
Start equalization / precharge of n to prepare for the next read operation. Although a potential difference also occurs in the I / O line pair 12-f between the timings T1 to T3, the read amplifier activation signal 14 can transition to the H level earlier than in the conventional example, so that the potential amplitude is sufficiently small. Value (<10% of the precharge potential).

A case where data is read from the memory cells in the memory cell group 3p will be described. In order to select the memory cell group 3p, the memory cell group selection signal 10
-F is activated (for example, corresponds to the memory cell group selection signal 10p in FIG. 2). Accordingly, the read amplifier control signal 14 is supplied to the delay circuits 19a to 19p of the timing generator 19.
Will be generated via The column selection signal 1
1-f is activated at timing T2 due to wiring delay, and starts reading data from the selected memory cell in the memory cell array 3-f. Here, the timing when the read amplifier control signal 14 changes to L is T2
Is the sum of the delay times of the delay units 19a to 19p. The delay time of each of the delay units 19 is equal to the signal delay between two adjacent memory cell groups (= the column selection signals 11-n to 11-n). This is because the signal delay is adjusted to be 11-f. I / O line pair 12-
The data read to f propagates to the I / O line pair 12-n with a wiring delay. When the potential difference between the I / O line pair 12-n has increased to about 10% of the precharge voltage (T4 in the figure), the read amplifier control signal 14 transitions to the H level to activate the read amplifier circuit 6. Become The timing at which the read amplifier control signal 14 transitions to the H level is also set based on the sum of the delay times of the delay units 19a to 19p. At the same time, equalization / precharge of the I / O line pair 12-n is started to prepare for the next read.
The potential amplitude generated in the / O line pair 12-f is wider than the I / O line pair 12-n due to the wiring capacitance / resistance. However, compared to the conventional example, the read amplifier activation signal 14
Since the delay is adjusted by the delay units 19a to 19p, the level becomes sufficiently narrow.

As described above, the timing of the read amplifier control signal 14 in the selection of the memory array 3-n and the selection of the memory array 3-f can be optimized by the delay unit 16, respectively. Power consumption can be suppressed by stopping the potential amplitude level at a specified value, and the reading speed can be increased / timing design can be facilitated.

(Embodiment 3) FIGS. 7 and 8 show (Embodiment 3). In the semiconductor memory device shown in FIG. 7, a dummy sense amplifier 22 is interposed between memory cell array 3 and sense amplifier 4, and control signal generating circuit 8 shown in FIG.
Is replaced by a control signal generating circuit 24 having a different internal configuration.

The dummy sense amplifier 22 is composed of a MOS transistor having the same current capability as the sense amplifier 4 and is activated simultaneously with the sense amplifier 4. 2
Reference numeral 3 denotes a dummy I / O line pair, which is formed of the same wiring material as the I / O line pair 12.

The control signal generation circuit 24 receives the control circuit activation signal 13 and the dummy I / O line pair 11 as input signals.
The read amplifier control signal 14 is generated as shown in FIG.

Reference numeral 29 denotes a detection circuit, which is a reference potential generation circuit 26.
And a differential amplifier circuit 25. Reference numeral 27 denotes a reference potential (Vref), which is connected to two input terminals of the differential amplifier circuit 25, respectively. 28 is a detection circuit start signal, and 30 is a NAND element. Reference numeral 33 denotes a timing generator, which includes switch circuits 31a and 31b and a delay unit 3
2a and 32b. Here, the delay unit 32
The delay times a and 32b are selected in FIG. 7 (signal delay time between the memory cell group and the read amplifier) /
Set to 2. Therefore, the delay time of the delay device 32a is much smaller than the delay time of the delay device 32b.

Here, the reference potential 27 is equal to I /
Required voltage amplitude of O line pair (~ 9 of precharge level)
0%), and if one of the dummy I / O line pairs 23 is lower than the reference potential 27 after the activation of the detection circuit activation signal 28, the switch circuit 31a of the timing generator 33 Is turned on, and the control circuit activation signal 13 is directly connected to the read amplifier activation signal 14 via the delay device 32a (delay time: small).

Conversely, if both of the dummy I / O line pairs are higher than the reference potential 27, the switch circuit 31b of the timing generator 33 is turned on, and the control circuit activation signal 13 is supplied to the delay unit 32b. (Delay time: large)
Generates the read amplifier activation signal 14 delayed.

[0050]

As described above, according to the semiconductor memory device of the present invention, the voltage amplitude of the I / O line is stopped at the specified value regardless of the position of the selected memory cell, the power consumption is suppressed, and the reading speed is increased. The timing can be designed easily.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to Embodiment 1 of the present invention;

FIG. 2 is a configuration diagram of a control signal generation circuit according to the embodiment;

FIG. 3 is an operation waveform diagram of the embodiment.

FIG. 4 is a configuration diagram of a semiconductor memory device according to Embodiment 2 of the present invention;

FIG. 5 is a configuration diagram of a control signal generation circuit according to the embodiment;

FIG. 6 is an operation waveform diagram of the embodiment.

FIG. 7 is a configuration diagram of a semiconductor memory device according to (Embodiment 3) of the present invention;

FIG. 8 is a configuration diagram of a control signal generation circuit according to the embodiment;

FIG. 9 is a configuration diagram of a conventional semiconductor memory device.

FIG. 10 is an operation waveform diagram of the conventional example.

[Explanation of symbols]

Reference Signs List 1 decode circuit (first decode circuit) 2 decode circuit (second decode circuit) 3 memory cell array 4 sense amplifier 5 decode circuit 6 read amplifier 7 output circuit 8 control signal generation circuit 9 row address decode signal group (memory cell row) 10 address select signal 10a-10p memory cell group address decode signal 11 column select signal 12 I / O line pair 13 control circuit activation signal 14 control signal of read amplifier 6 16 first timing generator 15a To 15p first switch section 16a to 16p delay unit 19 timing generation section (second timing generation section) 19a to 19p delay section 20 switch section (second switch section) 20a to 20p switch circuit 22 dummy sense amplifier 23 dummy I / O line 24 control signal generation Circuit 25 Differential amplifier circuit 26 Reference potential generation circuit 28 Detection signal activation signal 29 Detection circuit 31a, 31b Switch circuit 32a, 32b Delay unit 33 Timing generator (third timing generator)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) G11C 11/401 G11C 11/34 362H

Claims (9)

[Claims] A first decode circuit for taking in a row address signal to generate a memory cell row address decode signal; a second decode circuit to take in a row address signal to generate a memory cell group address decode signal; A memory cell array in which a plurality of memory cells are arranged in a matrix in a memory cell group as a unit and
A sense amplifier for reading data by detecting a change in a bit line connected to a memory cell of the memory cell array selected by a column selection signal obtained by decoding a column address signal and the memory cell row address decode signal; And a read amplifier for detecting and amplifying a minute potential difference of an I / O line connected to the semiconductor memory device, wherein a control signal for the read amplifier is provided in accordance with a memory cell group selected by inputting the row address signal. Semiconductor memory device provided with a control signal generation circuit for changing the generation timing of the data. 2. A control signal generating circuit, comprising: a first timing generator for adjusting an output timing of the control signal in accordance with a memory cell group address decode signal; and a control circuit activation signal for supplying the control signal to the first timing generator. A first switch section for activating a memory cell group address decode signal, wherein the first timing generating section includes a plurality of delay circuits having different delay times corresponding to the memory cell group address decode signal. 2. The device according to claim 1, wherein the devices are arranged in parallel.
13. The semiconductor memory device according to claim 1. 3. The delay time of the delay unit constituting the first timing generator is large when the position of the memory cell group selected by the corresponding row address decode signal is far from the read amplifier, and is close to the read amplifier. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured to be small in a case. 4. A control signal generation circuit, comprising: a second switch section activated by a memory cell group address decode signal; a second timing generation section comprising a plurality of delay units for delaying a control circuit activation signal. 2. The semiconductor device according to claim 1, wherein one of a plurality of delay outputs delayed by the second timing generator via the second switch is selected as the control signal. 3. Storage device. 5. The correspondence between a group of delay units, a switch circuit, and a row address decode signal constituting a second timing generator is determined when a position of a memory array selected by the row address decode signal is far from a read amplifier. A switch circuit forming the second switch unit is turned on so that a signal passed through a large number of delay units is used as the control signal. The switch circuit constituting the second switch section is made conductive so that
13. The semiconductor memory device according to claim 1. 6. A first decode circuit for taking in a row address signal to generate a memory cell row address decode signal, a second decode circuit to take in a row address signal and generate a memory cell group address decode signal, A memory cell array in which a memory cell group in which a plurality of memory cells are arranged in a matrix is arranged as a unit, and the memory selected by a column selection signal obtained by decoding a column address signal and the memory cell row address decode signal A sense amplifier for detecting a change in a bit line connected to a memory cell of a cell array and reading data, a read amplifier for detecting and amplifying a minute potential difference of an I / O line connected to the sense amplifier; Dummy sense amplifier with exactly the same current capability and connected to the dummy sense amplifier A control signal generating circuit for receiving a dummy I / O line having exactly the same wiring load as the I / O line, a control circuit activation signal and the dummy I / O line, and generating a control signal for controlling a read amplifier; Wherein the generation timing of the read amplifier control signal is determined by a signal delay of the dummy I / O line. 7. A control signal generating circuit, comprising: a detecting circuit for activating an output by the dummy I / O line; and a delay time of the control circuit activating signal, which is adjusted by an output of the detecting circuit, to control the control signal. And a third timing generator for outputting the signal. The detection circuit comprises a reference potential generation circuit and a differential amplifier circuit activated by a detection signal activation signal. , The output voltage of the reference potential generating circuit is applied to a first input of the second input, the dummy I / O line is connected to a second input, and the output of the differential amplifier circuit is 7. The semiconductor memory device according to claim 6, wherein an output of a detection circuit is supplied, and said delay time is determined according to a logic of an output of said detection circuit. 8. The third timing generator includes a plurality of switch circuits whose on / off states are switched by an output of the detection circuit, and a delay device connected in series to an input / output path of the switch circuit. 8. The semiconductor memory device according to claim 7, wherein said plurality of delay units have different delay times. 9. The third timing generator, wherein the differential amplifier circuit is activated by the detection signal activation signal when a level of the dummy I / O line is lower than an output voltage of a reference potential generation circuit. Is the first delay time, and when the level of the dummy I / O line is higher than the output voltage of the reference potential generating circuit, the delay time of the third timing generator is longer than the first delay time. 9. The semiconductor memory device according to claim 7, wherein said semiconductor memory device is configured to have a delay time of: