JP2002073713A - Circuit generating device, circuit generating method and cad designing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit generating device capable of generating a circuit having an equivalent function without redesigning the circuit and operatable at high speed, a circuit generating method and a CAD designing device for circuit formation. SOLUTION: This circuit generating device is provided with an input file 101 for inputting circuit information, a parallelizing verification means 102, a necessary parallelism extraction means 103 for selecting a parallelizable circuit from circuit information, a parallelism-determining means 104 for determining parallelism when the circuit extracted by the necessary parallelism extraction means 103 is converted into a parallelizing circuit, a parallelizing circuit generation means105 for generating circuit information on the parallelizing circuit from circuit information on a parallelizable circuit and parallelism determined by the parallelism-determining means 104 and an output file 108 for outputting circuit information generated from a recording file 106, a logic composition means 107 and the parallelizing circuit generation means 105.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a circuit generation device, a circuit generation method, and a CAD design device for circuit generation that can be used in the technical field of LSI design.

[0002]

2. Description of the Related Art Since integrated circuits such as ASICs (application-specific integrated circuits) and system LSIs have been increasing in scale year by year, all the circuit elements included in the integrated circuits have to be replaced with new ones. It is difficult to design.
At present, a design method has been developed which can reduce such a difficulty by reusing the design resources accumulated in the past to reduce the ratio of new design portions.

[0003] In addition, C used in current LSI design is
In an AD (Computer Aided Design) system, data such as a circuit description and drawings using symbols representing circuits are created, and the data is input to a synthesis tool such as a logic synthesis tool.
The method of converting to a logic circuit has become mainstream. further,
Under such a design method, the majority of logic circuits operate in synchronization with a clock that specifies the operation speed of the circuit.

[0004] A conventional circuit generator will be described below with reference to FIG.
This will be described with reference to FIG. Each component of the conventional example is mainly realized by software, but will be described below by replacing it with functional blocks.

FIG. 2 is a block diagram showing a configuration of a conventional circuit generator. This circuit generation device includes an input file 101, a logic synthesis unit 107, and an output file 108.

The operation of each unit shown in FIG. 2 will be described below. In FIG. 2, an input file 101 includes a circuit description in a hardware description language (HDL) representing a desired circuit, circuit description information describing a drawing or the like with a symbol representing the circuit, and a circuit operation representing a desired circuit operation speed. It has circuit information such as speed information. Here, the circuit description in the hardware description language is, for example, Verilog-HDL, V
This is an RTL description in HDL such as HDL. The drawing using symbols representing circuits is, for example, connection information between circuit elements such as logic gates and logic circuits corresponding to symbols representing circuits. Also, when the circuit is used by incorporating it into a higher-level circuit,
The circuit operation speed is equal to the operation speed of the host circuit. Further, the input file 101 may include the maximum operation speed information of the circuit as the circuit information.

Here, the circuit operating speed information and the maximum operating speed information are, for example, numerical values representing time intervals during which the clock operates, that is, clock cycles, or numerical values representing the delay time from input to output of the circuit. The maximum operation speed information is, for example, the shortest clock cycle at which the circuit can operate,
Alternatively, it refers to the minimum value of the delay time.

[0008] The circuit information including such circuit operation speed information is supplied to the logic synthesizing means 107, and the processing is passed to the logic synthesizing means 107. The logic synthesis unit 107 generates logic circuit information by performing logic synthesis on the circuit information supplied from the input file 101 with the operation speed information as a constraint. Here, the logic synthesis refers to information processing for converting, for example, the contents described in the RTL HDL into logic gates and the like constituting an LSI. Therefore, the logic circuit information is, for example, connection information of a logic gate or the like forming an LSI.

In general, in logic synthesis, the maximum operation speed is determined by the configuration of the circuit represented by the circuit information. Even when logic synthesis is performed using circuit operation speed information higher than the maximum operation speed as a constraint, a circuit operating at the maximum operation speed or higher is determined. It cannot be logically synthesized. A commercially available logic synthesis tool is used for such logic synthesis, and the logic circuit information generated by the logic synthesis means 107 is supplied to an output file 108, and the processing is passed to the output file 108. Output file 108
Outputs the logic circuit information supplied from the logic synthesis unit 107 to a file or the like.

[0010]

By the way, in the above-mentioned conventional circuit generating apparatus, when designing a circuit by incorporating it into a higher-level circuit, the operating speed of the integrated circuit is lower than the operating speed of the higher-level circuit incorporating the circuit. If you are slow
Circuits held as past design assets cannot be directly incorporated and used. Therefore, it is necessary to generate a new circuit having the same function as the circuit and operating at high speed.

Conventionally, in order to generate a circuit that operates at a high speed, it is necessary to redesign the circuit such as increasing the number of pipeline stages of the circuit. However, in such circuit redesign, LS
If the I-designer does not create the design resources by himself, and does not know the inside of the circuit in detail, there are problems such as a long design period and the inability to effectively use the circuit resources.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and a circuit having equivalent functions and capable of operating at high speed can be generated without redesigning the circuit. It is an object to provide a circuit generation device, a circuit generation method, and a CAD design device for circuit generation.

[0013]

In order to achieve the above object, parallelized circuit information is generated from circuit information describing a circuit description in a hardware description language representing a desired circuit, drawings including symbols representing the circuit, and the like. A circuit generating device is provided. The circuit generation device includes an information input unit for inputting the circuit information, a selection unit that selects a circuit that can be parallelized from the circuit information, and converts the circuit selected by the selection unit into a parallelized circuit. Means for determining the degree of parallelism, circuit information of the parallelizable circuit selected by the selecting means, and circuit information of the parallelized circuit generated from the degree of parallelism determined by the parallelism determining means. Circuit information generating means, and output means for outputting the circuit information generated by the circuit information generating means.

By using the circuit generating device having the above configuration,
It is possible to generate a parallelized circuit that performs parallel processing of circuits, and to generate a circuit that has equivalent functions and operates at high speed without the designer redesigning the stored circuit design information. Becomes possible.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of the circuit generation device according to the embodiment. This circuit generation device is mainly realized by software, but will be described below by replacing it with functional blocks.

In FIG. 1, reference numeral 101 denotes an input file, 1
02 is a parallelization verification unit, 103 is a necessary parallelism extraction unit,
Reference numeral 104 denotes a parallelism determining means, 105 denotes a parallelized circuit generating means, 106 denotes a recording file, and 107 and 108 denote logic synthesizing means and output files, respectively, which are the same as those of the conventional apparatus of FIG.

The input file 101 includes, in addition to a circuit description in a hardware description language representing a desired circuit, circuit description information describing drawings and the like using symbols representing the circuit, and circuit operation speed information representing a desired circuit operation speed. And other circuit information. Of these, the circuit description information is the parallelization verification means 1
02, the circuit operating speed information is supplied to the necessary parallelism extracting means 103 and the logic synthesizing means 107, and the processing is passed to the parallelization verifying means 102.

The parallelization verification means 102 determines whether the input file 1
The circuit characteristic indicated by the circuit description information supplied from 01 is inspected to determine whether the circuit can be parallelized. Here, the types of circuits that can be parallelized include, for example, a combinational logic circuit or a circuit in which the combinational logic circuit is pipelined. In order to inspect the characteristics of such a circuit, for example, a commercially available logic synthesis tool, a commercially available hardware description parsing tool, or the like can be used.

If the circuit can be parallelized, the circuit description information is supplied to the necessary parallelism extracting means 103, and the processing is passed to the necessary parallelism extracting means 103. If the circuit cannot be parallelized, the circuit description information is supplied to the logic synthesizing means 107, and the processing is passed to the logic synthesizing means 107.

The required parallelism extraction means 103 uses the circuit operation speed information supplied from the input file 101 and the circuit description information supplied from the parallelization verification means 102 to operate the circuit at a desired operation speed. The necessary degree of parallelism is extracted. Here, when the circuit information does not include the maximum operating speed information of the circuit, the circuit characteristics are inspected to obtain the maximum operating speed information of the circuit. In order to inspect the circuit characteristics, for example, a commercially available logic synthesis tool, a commercially available static timing analysis tool, a commercially available hardware description syntax analysis tool, or the like is used.

The required parallelism Nmin is a value of a clock cycle or delay time (SYSCL) which is circuit operation speed information.
K-DELAY) and the value of the shortest clock cycle or the maximum delay time, which is the maximum operating speed information of the circuit (CIRC
(UIT-DELAY) is obtained by the following equation.

[0022]

Nmin = ｛CIRCUIT-DELAY / S
YSCLK-DELAY} Minimum natural number greater than or equal to SYSCLK-DELA
If Y is equal to or greater than CIRCUIT-DELAY, the necessary degree of parallelism Nmin is 1.

The circuit information including the required degree of parallelism is supplied to the degree of parallelism determining means 104. The processing is passed to the parallel degree determining means 104. The parallel degree determining means 104 determines the parallel degree at the time of converting the circuit into a parallel circuit based on the required parallel degree supplied from the necessary parallel degree extracting means 103. The degree of parallelism is Nmi, where Nmin is the required degree of parallelism.
Any natural number equal to or greater than n. That is, the parallel degree N may be the necessary parallel degree Nmin. The degree of parallelism N can be specified by a designer, for example.
Alternatively, the necessary parallelism Nmin can be used as it is. Furthermore, using a commercially available logic synthesis tool, etc.,
It is also possible to evaluate the circuit characteristics and the like of the circuit element and determine the value based on a predetermined function.

The parallel degree obtained by the parallel degree determining means 104 is
It is supplied to the parallelized circuit generation means 105 together with the circuit information,
The processing is passed to the parallelized circuit generating means 105. The parallelized circuit generating means 105 generates newly parallelized circuit information based on the circuit information supplied from the parallelism determining means 104 and the parallelism determined by the parallelism determining means 104. FIGS. 3 to 11 to be described next are examples of conversion to a parallelized circuit.

FIG. 3 is a block diagram showing an example of a circuit to be parallelized. In the figure, SYSCLK 101 is a clock signal line, IN 101 is an input signal line, IFF 101 is an input signal storage device, C 101 is a combinational logic circuit (or a circuit in which the combinational logic circuit is pipelined, the same applies to the following description), and OFF 101 is The output signal storage device OUT101 is an output signal line.

The clock signal line SYSCLK101 has
A clock signal SYSCLK supplied from a higher-level circuit in which a circuit to be parallelized is incorporated is supplied, and the input signal storage device IFF101 and the combinational logic circuit C10 are supplied.
1. The output signal is supplied to the output signal storage device OFF101.

The input signal line IN101 is for supplying the input signal IN from an upper-level circuit in which a circuit to be parallelized is incorporated, and is connected to the input signal storage device IFF101. Even if the number of signal lines of the input signal IN is single,
There may be more than one.

The input signal storage device IFF101 stores the input signal IN supplied from the input signal line IN101 in synchronization with the clock signal SYSCLK. The stored signal is supplied to the combinational logic circuit C101.

The combinational logic circuit C101 performs a logical operation on the signal supplied from the input signal storage device IFF101. In this combinational logic circuit C101,
The shortest operable clock cycle or the maximum delay time (CIRCUIT-DELAY) is D, and the latency is M
And The calculation result is output signal storage device OFF101.
Supplied to In the combinational logic circuit C101, in the case of a pipelined circuit, the operation speed is determined by the frequency of the clock signal SYSCLK.

The output signal storage device OFF101 stores the signal supplied from the combinational logic circuit C101 in synchronization with the clock signal SYSCLK. The stored signal is output from the output signal line OUT101. The number of output signal lines OUT101 may be singular or plural.

The output signal line OUT101 is connected to the output signal OU.
This is supplied to a higher-level circuit in which a circuit for parallelizing T is incorporated. The maximum operating speed information of the circuit to be parallelized in FIG. 3 is D, and the latency is M + 2. Here, the latency refers to, for example, the clock signal SYSCLK from when the input signal IN is supplied from the input signal line IN101 to the parallelizing circuit in FIG. 3 to when the logical operation result is output to the outside from the output signal line OUT101. The number of operations. This is equal to the number of pipeline stages of the circuit to be parallelized.

Next, a parallelizing circuit generated based on the parallelizing circuit shown in FIG. 3 will be described. FIG. 4, FIG. 5, and FIG. 6 are block diagrams each showing an example of a parallelized circuit constituted by parallelized circuit information. In these figures, the same circuit components and signal elements as in FIG.
The same reference numerals are given.

The first parallel circuit shown in FIG. 4 is an example in which the priority is given to the reduction of the delay time of the output signal and the reduction of the latency. The delay time of the output signal refers to, for example, the time when the clock signal SYSCLK operates and the time when the output signal storage device is turned off.
It refers to the time until the signal stored in 101 is output from the output signal line OUT101. FIG. 7 is a diagram showing a time-series change of each signal line in the parallelization circuit of FIG.

The second parallel circuit shown in FIG. 5 is an example in which expansion of the output delay margin of the combinational logic circuit and reduction of the latency are prioritized. The output delay margin is
For example, the combinational logic circuits C101, C102, C10
3 means the time until the output signal is stored in the output signal storage device OFF101. Combinational logic circuit C101, C
The larger the output delay margin of 102 and C103, the more stable the parallel circuit can operate at high speed. FIG. 8 is a diagram showing a time-series change of each signal line in the parallel circuit of FIG.

Further, the third parallel circuit shown in FIG.
This is an example in which priority is given to extending the output delay margin of the combinational logic circuit and shortening the delay time of the output signal. FIG. 9 is a diagram showing a time-series change of each signal line in the parallel circuit of FIG. (First Parallelized Circuit) The first parallelized circuit shown in FIG. 4 will be further described. This first parallel circuit is shown in FIG.
When compared with the parallel clock signal line C
LK101, CLK102, CLK103, input signal storage devices IFF102, IFF103, combinational logic circuits C102, C103, signal lines CO101, CO10
2, CO103, a signal selection device SEL101, and a signal selection device output line SO101. In this parallelization circuit, when the parallelism supplied from the parallelism determination means 104 is N, by using N parallel clock signals, input signal storage devices, combinational logic circuits, and signal lines, Processing can be executed in N parallel.

In each circuit shown in FIG. 4, each block branched from the input signal line IN101 includes:
The numbers are added in the order of the processing charge. That is, 1
The clock signal line is CLK101, the input signal storage device is IFF101, the combinational logic circuit is C101, and the signal line is CO101. Similarly, if an arbitrary number from 1 to N is i, the i-th clock signal line is CLK1
02, the input signal storage device is IFF102, the combinational logic circuit is C102, and the signal line is CO102. Also,
The Nth clock signal line is CLK103, the input signal storage device is IFF103, the combinational logic circuit is C103,
The signal line is CO103.

Next, the operation of the first parallelizing circuit will be described with reference to FIG. Parallel clock signal CLK
[1], CLK [i], and CLK [N] are clock signals for processing the input signal IN input to the parallelization circuit in parallel, and are input signal storage devices IFF, respectively.
101, IFF102, IFF103, and combinational logic circuits C101, C102, C103.
Parallelized clock signals CLK [1], CLK [i], CL
The operation cycle of K [N] is equal to N of the clock signal SYSCLK.
A cycle corresponding to one operation.

Parallelized clock signals CLK [1], CLK
[I] and CLK [N] operate in the order of processing the signal values supplied from the input signal line IN101 in synchronization with the operation of the clock signal SYSCLK. That is, the parallelized clock signal CLK [1] is responsible for processing the first input signal, and therefore the first clock signal line SYSCLK10
1 and the clock signal SYSCLK
Is N times as large as the period. Similarly, the parallel clock signal CL
K [i] is responsible for processing the i-th input signal,
It is generated in synchronization with the i-th clock signal line SYSCLK101 and has a period N times as long as the clock signal SYSCLK. Further, the parallelized clock signal CLK [N] is
Since it is in charge of the processing of the Nth input signal, it is generated in synchronization with the Nth clock signal line SYSCLK101, and has a cycle N times the clock signal SYSCLK.

Input signal storage devices IFF101, IFF1
02, the IFF 103 converts the signal supplied from the input signal line IN101 into the parallel clock signal CLK, respectively.
[1], stored by the operation of CLK [i] and CLK [N]. That is, the input signal storage device IFF101 converts the signal from the input signal line IN101 into the parallel clock signal C
LK [1], and stores the input signal storage device IF
F102 stores the signal from the input signal line IN101 by the operation of the parallelized clock signal CLK [i], and the input signal storage device IFF103 stores the signal from the input signal line IN101 in the operation of the parallelized clock signal CLK [N]. Remember by The number of input signal lines IN101 may be one or more. The stored signals are respectively associated with combinational logic circuits C101, C102,
It is supplied to C103.

The combinational logic circuits C101, C102,
C103 performs a logical operation on the supplied signals.
Here, C101, C102 and C103 are all shown in FIG.
Is a circuit having the same configuration as the combinational logic circuit C101 shown in FIG. The result of the logical operation is indicated by signal lines CO101 and CO10.
2. The signal is supplied to the signal selection device SEL101 via the CO103.

The signal selection device SEL101 is connected to the signal line CO.
One of the signals of the combinational logic circuits C101, C102, and C103, which are input via the circuits 101, CO102, and CO103, selects one signal for which the logical operation processing has been completed. The logical operation of the input signal IN is performed by the clock signal S
Since the processing is completed in the order of input in synchronization with the operation of YSCLK, selection can be made by using an output of, for example, an N-ary binary counter device synchronized with the operation of the clock signal SYSCLK.

It is assumed that the latency of the combinational logic circuit C101, that is, the number of pipeline stages is M. At this time,
If C101 is a combinational circuit, M is set to 0. Further, as shown in FIG. 7, the first signal supplied from the input signal line IN101 is ID [1]. This ID
Assuming that the operation of the clock signal SYSCLK for storing [1] in the input signal storage device IFF101 is the first operation, the logical operation result C [1] is output to the signal line CO101 only when the clock signal SYSCLK ( M + 1) *
After the Nth operation.

Similarly, if the i-th signal supplied from the input signal line IN101 is ID [i],
The operation of the clock signal SYSCLK for storing [i] in the input signal storage device IFF102 is the i-th operation, and the logical operation result C [i] is output to the signal line CO102 because (M + 1) of the clock signal SYSCLK. ) * N
+ I-1 after the first operation.

Further, assuming that the N-th signal supplied from the input signal line IN101 is ID [N], this ID
The operation of the clock signal SYSCLK for storing [N] in the input signal storage device IFF103 is the Nth operation, and the logical operation result C [N] is output to the signal line CO103 only when (M + 1) of the clock signal SYSCLK is output. ) * N
After the (+ N-1) th operation.

As described above, in the first parallel circuit, the pipeline operation is performed with the N operations of the clock signal SYSCLK as one cycle. Therefore, the signal line on which the logical operation processing has been completed is operated by the clock signal SYSCLK. The number can be uniquely selected by the remainder when the number is divided by N. As the N-ary binary counter device of the signal selection device SEL101, for example, 1 is set immediately after the first operation of the clock signal SYSCLK.
, I immediately after the i-th operation, and N immediately after the N-th operation.
Is used, the signal selecting device SEL101 selects the signal line CO101 when the value is N, and selects the signal line CO10 when the value is i−1.
2, the signal line CO103 can be selected when the value is N-1. The selected signal is output from the signal selection device S
The signal is output from the EL 101 to the output signal storage device OFF101 via the output line SO101.

The output signal storage device OFF101 stores the signal supplied from the signal selection device SEL101 by the operation of the clock signal SYSCLK. The number of signal lines of the output signal OUT may be singular or plural. The signal stored in the output signal storage device OFF101 is output by the operation of the clock signal SYSCLK.

The output signal line OUT101 is connected to the output signal OU
This is for supplying T to the outside of the parallel circuit. FIG. 10 is a block diagram showing an equivalent circuit of the first parallelized circuit. In the equivalent circuit of FIG.
104 maximum operating speed information (CIRCUIT-DELA)
Y) is D / N, and latency is (M + 1) * N + 1
It has become. Here, D is the shortest clock cycle in which the combinational logic circuit C101 shown in FIG. 3 that is not parallelized can operate or the maximum delay time (CIRCUIT-DE).
LAY), and M is the latency. Therefore, by performing conversion processing into a parallelized circuit by the circuit generation device shown in FIG. 1, the latency (M +) having a function equivalent to that of the circuit shown in FIG.
1) Circuit information of * N + 1 parallel circuits can be generated. (Second parallel circuit) The second parallel circuit shown in FIG. 5 will be further described. This second parallel circuit is shown in FIG.
Output signal storage device OFF101
, And the parallelized clock signal lines CLK101, CLK101,
CLK102, CLK103, input signal storage device IFF
102, IFF103, combinational logic circuit C102,
C103, output signal storage devices PFF101, PFF102, PFF1 for holding respective logical operation results
03, signal lines CO101, CO102, CO103, signal selection device SEL101, signal selection device output line SO10
1 is added. In this parallelized circuit,
If the degree of parallelism supplied from the degree-of-parallel determination means 104 is N, the process is executed in N parallel by using N parallel clock signals, input signal storage devices, combinational logic circuits, and signal lines. it can.

Each circuit shown in FIG. 5 includes, in order to facilitate understanding, each block branched from the input signal line IN101.
The numbers are added in the order of the processing charge. That is, 1
The first clock signal line is CLK101, the input signal storage device is IFF101, the combinational logic circuit is C101, the output signal storage device is PFF101, and the signal line is CO101. Similarly, if i is any number from 1 to N,
The i-th clock signal line is CLK102, the input signal storage device is IFF102, the combinational logic circuit is C102,
Output signal storage device is PFF102, signal line is CO102
It is. The N-th clock signal line is CLK10
3. The input signal storage device is IFF103, the combinational logic circuit is C103, the output signal storage device is PFF103, and the signal line is CO103.

Next, the operation of the second parallelizing circuit will be described. The parallelized clock signals CLK [1], CLK [i],
CLK [N] is the signal IN input to the parallel circuit.
Are processed in parallel, and the input signal storage devices IFF101, IFF102, IF
F103, combinational logic circuits C101, C102, C
103. Parallel clock signal CLK
The operation cycle of [1], CLK [i], and CLK [N] is a cycle corresponding to N operations of the clock signal SYSCLK.

The parallelized clock signals CLK [1], CLK
[I] and CLK [N] operate in the order of processing the signal values supplied from the input signal line IN101 in synchronization with the operation of the clock signal SYSCLK. That is, the parallelized clock signal CLK [1] is responsible for processing the first input signal, and therefore the first clock signal line SYSCLK10
1 and the clock signal SYSCLK
Is N times as large as the period. Similarly, clock signal CLK
[I] is responsible for processing the i-th input signal, so i
The clock signal is generated in synchronization with the clock signal line SYSCLK101 and has a cycle N times as long as the clock signal SYSCLK. Further, since the clock signal CLK [N] is responsible for processing the Nth input signal, the clock signal CLK [N] is generated in synchronization with the Nth clock signal line SYSCLK101 and has a cycle N times the clock signal SYSCLK.

Input signal storage devices IFF101, IFF1
02 and the IFF 103 convert the signal supplied from the input signal line IN101 into the parallel clock signal CLK, respectively.
[1], stored by the operation of CLK [i], CLK [N]. That is, the input signal storage device IFF101 converts the signal from the input signal line IN101 into the parallel clock signal C
LK [1], and stores the input signal storage device IF
F102 stores the signal from the input signal line IN101 by the operation of the parallelized clock signal CLK [i], and the input signal storage device IFF103 stores the signal from the input signal line IN101 in the operation of the parallelized clock signal CLK [N]. Remember by The number of input signal lines IN101 may be one or more. The stored signals correspond to the corresponding combinational logic circuits C101, C102,
It is supplied to C103.

The combinational logic circuits C101, C102,
C103 performs a logical operation on the supplied signals.
Here, C101, C102 and C103 are all shown in FIG.
Is a circuit having the same configuration as the combinational logic circuit C101 shown in FIG. The logical operation results are stored in the output signal storage device P, respectively.
It is supplied to FF101, PFF102, PFF103.

Output signal storage devices PFF101, PFF1
02, the PFF 103 is a combinational logic circuit C101,
The signals supplied from C102 and C103 are respectively converted into parallel clock signals CLK [1] and CLK [1].
[I], and stored by the operation of CLK [N]. The stored signals are signal lines CO101, CO102, C
The signal is supplied to the signal selection device SEL101 via O103.

The signal selector SEL101 is connected to the signal line CO.
One of the signals of the combinational logic circuits C101, C102, and C103, which are input through the circuits 101, CO102, and CO103, selects one signal for which the logical operation processing has been completed. The logical operation of the input signal IN is performed by the clock signal S
Since the processing is completed in the order of input in synchronization with the operation of YSCLK, selection can be made by using an output of, for example, an N-ary binary counter device synchronized with the operation of the clock signal SYSCLK.

Let M be the latency of the combinational logic circuit C101, that is, the number of pipeline stages. At this time,
If C101 is a combinational circuit, M is set to 0. In addition, as shown in FIG. 8, the first signal supplied from the input signal line IN101 is ID [1]. This ID
Assuming that the operation of the clock signal SYSCLK for storing [1] in the input signal storage device IFF101 is the first operation, the logical operation result C [1] is output to the signal line CO101 only when the clock signal SYSCLK ( M + 1) *
After the (N + 1) th operation.

Similarly, if the i-th signal supplied from the input signal line IN101 is ID [i], this ID
The operation of the clock signal SYSCLK for storing [i] in the input signal storage device IFF102 is the i-th operation, and the logical operation result C [i] is output to the signal line CO102 because (M + 1) of the clock signal SYSCLK. ) * N
After the + i-th operation.

Further, assuming that the N-th signal supplied from the input signal line IN101 is ID [N], this ID
The operation of the clock signal SYSCLK for storing [N] in the input signal storage device IFF103 is the Nth operation, and the logical operation result C [N] is output to the signal line CO103 only when (M + 1) of the clock signal SYSCLK is output. ) * N
After the + N-th operation.

As described above, in the second parallel circuit, the pipeline operation is performed with the N operations of the clock signal SYSCLK as one cycle. Therefore, the signal line on which the logical operation process has been completed is the signal line of the clock signal SYSCLK. The operation number can be uniquely selected by the remainder when divided by N. The N-ary binary counter device includes, for example, a clock signal SYSCL.
1 immediately after the first operation of K, i
Is output immediately after the Nth operation and 1 is output immediately after the (N + 1) th operation.
In the case of 1, when the value is 1, the signal line CO101 is selected, when the value is i, the signal line CO102 is selected, and when the value is N, the signal line CO103 is selected. The selected signal is output from the signal selection device SEL101 via the output line SO101 (output signal line OUT101).

The output signal line OUT101 is connected to the output signal OU.
This is for supplying T to the outside of the parallel circuit. The number of signal lines of the output signal OUT may be singular or plural.

FIG. 10 shows an equivalent circuit of the first parallelized circuit.
Is also a block diagram of an equivalent circuit of the second parallel circuit. In the equivalent circuit of FIG. 10, the combinational logic circuit C10
4 maximum operating speed information (CIRCUIT-DELAY)
Is D / N, and the latency is (M + 1) * N + 1. Here, D is the shortest clock cycle or the maximum delay time (CIRCUIT-DELA) operable by the combinational logic circuit C101 shown in FIG. 3 which is not parallelized.
Y) and M is the latency. Therefore,
Latency (M + 1) having a function equivalent to that of the circuit shown in FIG. 3 and capable of operating at a maximum N-times operating speed by being converted into a parallelized circuit by the circuit generation device shown in FIG.
The circuit information of the * N + 1 parallel circuit can be generated. (Third Parallel Circuit) The third parallel circuit shown in FIG. 6 will be further described. This third parallel circuit is shown in FIG.
When compared with the parallel clock signal line C
LK101, CLK102, CLK103, input signal storage devices IFF102, IFF103, combinational logic circuits C102, C103, output signal storage devices PFF101, PFF10 for holding respective logical operation results
2, PFF103, signal lines CO101, CO102, C
O103, a signal selection device SEL101, and a signal selection device output line SO101 are added. In this parallelization circuit, when the parallelism supplied from the parallelism determination means 104 is N, N parallel clock signals,
By using an input signal storage device, a combinational logic circuit, and a signal line, processing can be performed in N parallel.

Each circuit in FIG. 6 includes, in order to facilitate understanding, each block branched from the input signal line IN101.
The numbers are added in the order of the processing charge. That is, 1
The first clock signal line is CLK101, the input signal storage device is IFF101, the combinational logic circuit is C101, the output signal storage device is PFF101, and the signal line is CO101. Similarly, if i is any number from 1 to N,
The i-th clock signal line is CLK102, the input signal storage device is IFF102, the combinational logic circuit is C102,
Output signal storage device is PFF102, signal line is CO102
It is. The N-th clock signal line is CLK10
3. The input signal storage device is IFF103, the combinational logic circuit is C103, the output signal storage device is PFF103, and the signal line is CO103.

Next, the operation of the third parallel circuit will be described. The parallelized clock signals CLK [1], CLK [i],
CLK [N] is the signal IN input to the parallel circuit.
Are processed in parallel, and the input signal storage devices IFF101, IFF102, IF
F103, combinational logic circuits C101, C102, C
103. Parallel clock signal CLK
The operation cycle of [1], CLK [i], and CLK [N] is a cycle corresponding to N operations of the clock signal SYSCLK.

The parallel clock signals CLK [1], CLK
[I] and CLK [N] operate in the order of processing the signal values supplied from the input signal line IN101 in synchronization with the operation of the clock signal SYSCLK. That is, since the clock signal CLK [1] is responsible for processing the first input signal, the clock signal CLK [1] is generated in synchronization with the first clock signal line SYSCLK101 and has a cycle N times the clock signal SYSCLK. Similarly, the clock signal CLK [i] is
Since it is in charge of the processing of the i-th input signal, it is generated in synchronization with the i-th clock signal line SYSCLK101 and has a cycle N times the clock signal SYSCLK. Further, since the clock signal CLK [N] is responsible for processing the Nth input signal, the Nth clock signal line SYSC
The clock signal SY generated in synchronization with the LK101
This is N times the cycle of SCLK.

Input signal storage devices IFF101, IFF1
02 and the IFF 103 convert the signal supplied from the input signal line IN101 into the parallel clock signal CLK, respectively.
[1], stored by the operation of CLK [i], CLK [N]. That is, the input signal storage device IFF101 converts the signal from the input signal line IN101 into the parallel clock signal C
LK [1], and stores the input signal storage device IF
F102 stores the signal from the input signal line IN101 by the operation of the parallelized clock signal CLK [i], and the input signal storage device IFF103 stores the signal from the input signal line IN101 in the operation of the parallelized clock signal CLK [N]. Remember by The number of input signal lines IN101 may be one or more. The stored signals correspond to the corresponding combinational logic circuits C101, C102,
It is supplied to C103.

The combinational logic circuits C101, C102,
C103 performs a logical operation on the supplied signals.
Here, C101, C102 and C103 are all shown in FIG.
Is a circuit having the same configuration as the combinational logic circuit C101 shown in FIG. The logical operation results are stored in the output signal storage device P, respectively.
It is supplied to FF101, PFF102, PFF103.

Output signal storage devices PFF101, PFF1
02, the PFF 103 is a combinational logic circuit C101,
The signals supplied from C102 and C103 are respectively converted into parallel clock signals CLK [1] and CLK [1].
[I], and stored by the operation of CLK [N]. The stored signals are signal lines CO101, CO102, C
The signal is supplied to the signal selection device SEL101 via O103.

The signal selecting device SEL101 is connected to the signal line CO.
One of the signals of the combinational logic circuits C101, C102, and C103, which are input through the circuits 101, CO102, and CO103, selects one signal for which the logical operation processing has been completed. The logical operation of the input signal IN is performed by the clock signal S
Since the processing is completed in the order of input in synchronization with the operation of YSCLK, selection can be made by using an output of, for example, an N-ary binary counter device synchronized with the operation of the clock signal SYSCLK.

It is assumed that the latency of the combinational logic circuit C101, that is, the number of pipeline stages is M. At this time,
If C101 is a combinational circuit, M is set to 0. Further, as shown in FIG. 9, the first signal supplied from the input signal line IN101 is ID [1]. This ID
Assuming that the operation of the clock signal SYSCLK for storing [1] in the input signal storage device IFF101 is the first operation, the logical operation result C [1] is output to the signal line CO101 only when the clock signal SYSCLK ( M + 1) *
After the (N + 1) th operation.

Similarly, assuming that the i-th signal supplied from the input signal line IN101 is ID [i], this ID
The operation of the clock signal SYSCLK for storing [i] in the input signal storage device IFF102 is the i-th operation, and the logical operation result C [i] is output to the signal line CO102 because (M + 1) of the clock signal SYSCLK. ) * N
After the + i-th operation.

Further, assuming that the N-th signal supplied from the input signal line IN101 is ID [N], this ID
The operation of the clock signal SYSCLK for storing [N] in the input signal storage device IFF103 is the Nth operation, and the logical operation result C [N] is output to the signal line CO103 only when (M + 1) of the clock signal SYSCLK is output. ) * N
After the + N-th operation.

As described above, in the third parallel circuit, the pipeline operation is performed with the N operations of the clock signal SYSCLK as one cycle, so that the signal line on which the logical operation process has been completed is the signal line of the clock signal SYSCLK. The operation number can be uniquely selected by the remainder when divided by N. The N-ary binary counter device includes, for example, a clock signal SYSCL.
1 immediately after the first operation of K, i
Is output immediately after the Nth operation and 1 is output immediately after the (N + 1) th operation.
In the case of 1, when the value is 1, the signal line CO101 is selected, when the value is i, the signal line CO102 is selected, and when the value is N, the signal line CO103 is selected. The selected signal is output from the signal selection device SEL101 to the output signal storage device OFF101 via the output line SO101.

The output signal storage device OFF101 stores the signal supplied from the signal selection device SEL101 by the operation of the clock signal SYSCLK. The number of signal lines of the output signal OUT may be singular or plural. The signal stored in the output signal storage device OFF101 is output by the operation of the clock signal SYSCLK.

The output signal line OUT101 is connected to the output signal OU.
This is for supplying T to the outside of the parallel circuit. FIG. 11 is a block diagram showing an equivalent circuit of the third parallel circuit. In the equivalent circuit of FIG.
105 operating speed information (CIRCUIT-DELA)
Y) is D / N and the latency is (M + 1) * N + 2
It has become. Here, D is the shortest clock cycle in which the combinational logic circuit C101 shown in FIG. 3 that is not parallelized can operate or the maximum delay time (CIRCUIT-DE).
LAY), and M is the latency. Therefore, by performing conversion processing into a parallelized circuit by the circuit generation device shown in FIG. 1, the latency (M +) having a function equivalent to that of the circuit shown in FIG.
1) Circuit information of * N + 2 parallel circuits can be generated.

Here, returning to the circuit generating apparatus shown in FIG. 1 again, when the parallelized circuit generating means 105 generates the circuit information converted into the above-described parallelized circuit, the circuit description information is stored in the recording file 106. Is stored in The processing is passed to the recording file 106.

The recording file 106 stores the converted circuit description information. The parallelized circuit information is supplied to the logic synthesizing means 107, and the processing is passed to the logic synthesizing means 107.

The logic synthesizing means 107 stores the recording file 10
Then, the circuit description information supplied from 6 is logic-synthesized using the circuit operation speed information as a constraint to generate logic circuit description information. This logic synthesis is information processing for converting, for example, the contents described in RTL HDL into logic gates and the like constituting an LSI. The generated logic circuit description information is
For example, connection information of logic gates constituting an LSI.
A commercially available logic synthesis tool is used for the logic synthesis, and the logic circuit description information generated by the logic synthesis unit 107 is supplied to an output file 108, and the processing is performed by the output file 108.
Passed to.

The output file 108 is output to the logic
The logic circuit description information supplied from 7 is output to a file or the like. Next, the flow of actual circuit description information executed by the circuit generation device according to the embodiment will be described.

FIG. 12 is a diagram showing a specific example of circuit information representing an integrated circuit to be parallelized. Input file 10 of FIG.
1, a combinational circuit composed of two adders and one multiplier corresponding to the logical operation circuit C101 is input.

Here, assuming that the designer expects the circuit of FIG. 12 to operate at a clock cycle of 10 ns, the circuit operating speed information indicating the circuit operating speed is 1
It is set to 0. At this point, it is assumed that the circuit information does not include the maximum operating speed information of the circuit. Circuit information (Fig. 12)
Is supplied to the parallelization verification unit 102. The circuit operation speed information (10) is supplied to the necessary degree of parallelism extraction means 103 and the logic synthesis means 107, and the processing is passed to the parallelization verification means 102.

The parallelization verification means 102 determines whether the input file 1
The characteristic of the circuit represented by the circuit information supplied from 01 is inspected to determine whether the circuit can be parallelized. For example, as a result of inspecting the circuit characteristics of the circuit shown in FIG. 12 using a hardware description syntax analysis tool or the like, if it is found that the circuit is a combinational logic circuit or a circuit in which the combinational logic circuit is made into a pipeline, FIG. The circuit is determined to be parallelizable.

If the circuits can be parallelized, the circuit description information is supplied to the necessary parallelism extracting means 103, and the processing is passed to the necessary parallelism extracting means 103. Required parallelism extraction means 10
3 extracts the degree of parallelism necessary for the circuit to operate at a desired operation speed, based on the circuit operation speed information supplied from the input file 101 and the circuit description information supplied from the parallelization verification means 102. . Here, since the circuit information does not include the maximum operating speed information of the circuit, it is necessary to inspect the circuit characteristics and obtain the maximum operating speed information of the circuit. A commercially available logic synthesis tool and a commercially available static timing analysis tool are used to inspect the characteristics of the circuit. As a result, if it is determined that the maximum operation speed of the circuit represented by the circuit information is, for example, 30 ns, the maximum operation speed information is set to 30.

If the circuit operating speed information is 10 and the maximum operating speed information is 30, the required parallelism Nmin is 3
Becomes The circuit information including the required degree of parallelism is supplied to the degree-of-parallelism determination means 104. The processing is passed to the parallel degree determining means 104.

The parallel degree determining means 104 determines the degree of parallelism when converting a circuit into a parallelized circuit based on the required parallel degree supplied from the necessary parallel degree extracting means 103. Now
Since the required degree of parallelism Nmin is 3, this required degree of parallelism 3
Shall be used as it is. Parallel degree determining means 104
Is supplied to the parallelized circuit generator 105 together with the circuit information, and the processing is performed by the parallelized circuit generator 10.
Passed to 5.

The parallelized circuit generating means 105 generates newly parallelized circuit information based on the circuit information supplied from the parallelism determining means 104 and the parallelism determined by the parallelism determining means 104. Here, a description will be given as an example of conversion to the third parallel circuit shown in FIGS. 3, 6, 9, and 12 described above.

FIG. 13 is a block diagram showing a parallelized circuit. FIG. 14 is a diagram showing a time-series change of each signal line in the parallel circuit of FIG. FIG. 15 is a diagram showing an equivalent circuit of the parallel circuit of FIG.

As shown in the equivalent circuit of FIG. 15, the maximum operation speed (D / N) is 10 ns, and FIGS.
The maximum operation speed information of the circuit information represented by is 10. The latency of the circuit of FIG. 15 is 5 (= N + 2).
Becomes Therefore, by executing the conversion process, FIG.
2. Circuit information having a latency of 5 and having a function equivalent to that of the circuit shown in FIG. 2 and capable of operating at a maximum of three times the operation speed was generated.

The generated information of the parallelization circuit is supplied to the recording file 106. The processing is passed to the recording file 106. The logic synthesizing unit 107 outputs the input file 10
1, or by logically synthesizing the circuit information supplied from the recording file 106 using the operation speed information as a constraint, thereby generating logic circuit information. As a logic synthesis method, for example, by using a commercially available logic synthesis tool or the like, connection information of a logic gate or the like constituting an LSI can be generated.

In general, in logic synthesis, the maximum operation speed is determined by the configuration of the circuit represented by the circuit information. Even when logic synthesis is performed using circuit operation speed information higher than the maximum operation speed as a constraint, a circuit that operates at the maximum operation speed or higher is determined. It cannot be logically synthesized. Therefore, the result of logically synthesizing the circuit information shown in FIG. 13 having the maximum operation speed of 30 ns according to the conventional method at the circuit operation speed of 10 ns is as follows.
Is merely generated.

On the other hand, in the circuit information generated by the above-described circuit generation device, the maximum operation speed is 10 ns.
As a result of logically synthesizing the circuit information shown in FIGS. 13 to 15 at a circuit operation speed of 10 ns, a logic circuit having an operation speed of 10 ns can be generated. The logic circuit information generated by the logic synthesis unit 107 is supplied to an output file 108, and the processing is passed to the output file 108. The output file 108 outputs the logic circuit information supplied from the logic synthesis unit 107 to a file or the like, and can be used as LSI design data.

[0090]

As described above, according to the circuit generation device of the present invention, the same processing is executed in parallel for the circuit element whose operation speed is slower than the operation speed of the upper circuit incorporating the circuit element. A parallel circuit can be generated. Therefore, the following effects can be obtained.

First, by generating a circuit having a function equivalent to that of the related art and capable of operating at high speed, the circuit design of an LSI having a high operating speed becomes easy. Second, even when the operating speed of a circuit element is lower than the operating speed of a higher-level circuit in which the circuit element is incorporated, a redesign by a designer to speed up the circuit operation as compared with the related art. Can be reduced, which contributes to shortening the LSI design period.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a circuit generation device according to an embodiment;

FIG. 2 is a block diagram illustrating a configuration of a conventional circuit generation device.

FIG. 3 is a block diagram illustrating an example of a circuit to be parallelized.

FIG. 4 is a block diagram showing a first parallelized circuit configured by parallelized circuit information;

FIG. 5 is a block diagram illustrating a second parallel circuit configured by parallel circuit information;

FIG. 6 is a block diagram illustrating a third parallel circuit configured by parallel circuit information;

FIG. 7 is a diagram showing a time-series change of each signal line in the first parallel circuit.

FIG. 8 is a diagram showing a time-series change of each signal line in the second parallel circuit.

FIG. 9 is a diagram showing a time-series change of each signal line in the third parallelization circuit.

FIG. 10 is a block diagram showing an equivalent circuit of a first parallel circuit (second parallel circuit).

FIG. 11 is a block diagram showing an equivalent circuit of a third parallel circuit.

FIG. 12 is a block diagram showing a specific example of circuit information representing an integrated circuit to be parallelized.

13 is a block diagram showing a parallel circuit obtained by parallelizing the integrated circuit of FIG.

FIG. 14 is a diagram showing a time-series change of each signal line in the parallel circuit of FIG. 13;

FIG. 15 is a block diagram showing an equivalent circuit of the parallelized circuit of FIG.

[Explanation of symbols]

101 input file, 102 parallelization verification means, 10
3 ... necessary parallelism extraction means, 104 ... parallelism determination means, 1
05: parallel circuit generation means, 106: recording file, 1
07: logic synthesis means, 108: output file

Claims (12)

[Claims] 1. A circuit generating apparatus for generating parallelized circuit information from circuit information describing a circuit description in a hardware description language representing a desired circuit or a drawing by a symbol representing a circuit, the circuit information being input. Information input means, a selecting means for selecting a circuit which can be parallelized from the circuit information, and a parallel degree determining means for determining a parallel degree when converting the circuit selected by the selecting means into a parallelized circuit. From the circuit information of the parallelizable circuit selected by the selection means and the degree of parallelism determined by the degree of parallelism determination means,
A circuit generation device, comprising: circuit information generation means for generating circuit information of a parallelized circuit; and output means for outputting circuit information generated by the circuit information generation means. 2. The parallelization determining means extracts a degree of parallelism necessary for operating at a desired operation speed from operation speed information of a desired circuit input from the information input means. 2. The circuit generation device according to claim 1, wherein a degree of parallelism required for conversion into the data is determined. 3. The circuit generating apparatus according to claim 1, further comprising a logic synthesizing unit that performs logic synthesis of the circuit information of the parallelized circuit at a stage subsequent to the circuit information generating unit. 4. The parallel degree determining means extracts a parallel degree necessary for operating at a desired operating speed from operating speed information of a desired circuit input from the information input means,
A circuit for determining a degree of parallelism required for conversion into a parallelized circuit, and further comprising a logic synthesizing unit for performing logic synthesis of circuit information of the parallelized circuit at a subsequent stage of the circuit information generating unit. Item 2. The circuit generation device according to item 1. 5. A CAD design device comprising the circuit generation device according to claim 1. 6. A CAD design device comprising the circuit generation device according to claim 2. 7. A CAD design device comprising the circuit generation device according to claim 3. 8. A CAD design device comprising the circuit generation device according to claim 4. 9. An information input step for inputting circuit information describing a circuit description in a hardware description language representing a desired circuit or a drawing by a symbol representing a circuit, and a circuit parallelizable from the circuit information. A selecting step of selecting, a parallel degree determining step of determining a parallel degree when converting the circuit selected in the selecting step to a parallel circuit, circuit information of the parallelizable circuit selected by the selecting step, And a circuit information generating step of generating circuit information of the parallelized circuit from the parallel degree determined by the parallel degree determining step, and an output step of outputting the circuit information generated by the circuit information generating step. Characteristic circuit generation method. 10. An information input step for inputting circuit information, such as a circuit description in a hardware description language representing a desired circuit, a drawing or the like by a symbol representing the circuit, and desired circuit operation speed information. A selecting step of selecting a circuit that can be parallelized from the information, based on the circuit information and the circuit operation speed information,
An extraction step of extracting a degree of parallelism required to operate at a desired operation speed; and from the information extracted in the extraction step, a degree of parallelism when converting the circuit selected in the selection step into a parallelized circuit. Determining a degree of parallelism to be determined; circuit information of the parallelizable circuit selected by the selecting step; and circuit information generating step of generating circuit information of the parallelized circuit from the degree of parallelism determined by the degree of parallelism determining step And an output step of outputting the circuit information generated by the circuit information generation step. 11. An information input step for inputting a circuit description in a hardware description language representing a desired circuit or a drawing by a symbol representing the circuit, and a circuit parallelizable from the circuit information. A selecting step of selecting, a parallel degree determining step of determining a parallel degree when converting the circuit selected in the selecting step to a parallel circuit, circuit information of the parallelizable circuit selected by the selecting step, And a circuit information generating step of generating circuit information of the parallelized circuit from the parallel degree determined by the parallel degree determining step; and a logic synthesizing step of logically synthesizing the parallelized circuit information generated by the circuit information generating step. An output step of outputting a result of the logic synthesis in the logic synthesis step. 12. An information input step for inputting circuit information, such as a circuit description in a hardware description language representing a desired circuit or a drawing by a symbol representing the circuit, and desired circuit operation speed information, A selecting step of selecting a circuit that can be parallelized from the information, based on the circuit information and the circuit operation speed information,
An extraction step of extracting a degree of parallelism necessary to operate at a desired operation speed; and from the information extracted in the extraction step, a degree of parallelism when converting the circuit selected in the selection step into a parallelized circuit. Determining a degree of parallelism to be determined; circuit information of the parallelizable circuit selected by the selecting step; and circuit information generating step of generating circuit information of the parallelized circuit from the degree of parallelism determined by the degree of parallelism determining step A logic synthesis step of logic-synthesizing the parallelized circuit information generated by the circuit information generation step; and an output step of outputting a logic synthesis result in the logic synthesis step. Method.