JP2002072986A - Liquid crystal driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct leak measurements of display data latches which are incorporated in the driver of a liquid crystal display device in a short time. SOLUTION: A set/reset function is added to a shift register 106 which generates the timing of inputting display data into display data latches 102(1) to 102(n). Then, by simultaneously setting all bits of the register 106 to an on or an off state from the outside, the leak measurements of all of the display data latches 102(1) to 102(n) are performed in only two leak measurements.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type liquid crystal display device having a liquid crystal cell corresponding to each pixel in a rectangular display area. And a liquid crystal driving device that drives based on display data that is sequentially input in time series.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a basic circuit configuration of a conventional liquid crystal driving device. This liquid crystal driving device
A matrix type liquid crystal display device having a liquid crystal cell corresponding to each pixel of the rectangular display area is displayed, and display data sequentially input in time series for each clock corresponding to each liquid crystal cell of each column of the liquid crystal display device. As shown in FIG. 3, an input circuit 101 and n display data latches 1 each composed of, for example, a D flip-flop are driven as shown in FIG.
02 (1) to 102 (n) and an n-stage shift register 1
03 and n D / A conversion units 104 (1) to 104 (104)
(N) and n output circuits 105 (1) to 105 (n)
It is composed of

The input circuit 101 has a function of taking in, for example, 8-bit display data Dx sequentially and time-sequentially input from the outside of the liquid crystal driving device at the rising timing of the clock FY and outputting it to the internal data bus 108 as display data LDx. Having.

[0004] The n display data latches 102 (1) to 102 (1)
02 (n) are provided corresponding to the liquid crystal cells in each column of the liquid crystal display device, respectively, and respond to display data capture signals input at timings corresponding to the liquid crystal cells in each column of the liquid crystal display device. The display data LDx output on the internal data bus 108.

The n-stage shift register 103 is set to the number of shift stages corresponding to the number of columns of the liquid crystal cells of the liquid crystal display device. The shift operation of the display data fetch signal S in accordance with the clock FY causes the shift register 103 to input every clock FY. It has a function of selectively outputting display data capture signals from output terminals G1 to Gn of sequentially different shift stages. That is, the shift register 103 converts the display data LDx output from the input circuit 101 into n display data latches 102 (1) to 102 (1).
02 (n) has a function of generating a timing to be captured.

[0006] The n D / A conversion units 104 (1) to 104 (104)
(N) indicates n display data latches 102 (1) to 102 (1) to (10).
2 (n) to generate a gray scale voltage based on the display data LDx stored respectively.

[0007] The n output circuits 105 (1) to 105
(N) denotes n D / A converters 104 (1) to 104 (1) to 104
It has the function of amplifying the grayscale voltages generated in (n) and outputting them as analog output voltages Y1 to Yn from the output terminals.

Next, the internal signal timing of the liquid crystal driving device will be described with reference to FIG. The display data Dx applied to the input circuit 101 is taken into the input circuit 101 at the timing of the clock FY, and is output from the internal data bus 108 as the display data LDx. The shift register 103 shifts the display data fetch signal S by a shift operation according to the clock FY, so that the display data fetch signals S1 to Sn are sequentially output from the output terminals G1 to Gn of different shift stages every time the clock FY is input. It will output selectively.

The display data capture signals S1 to S
n are input to the display data latches 102 (1) to 102 (n), respectively, so that the display data fetch signals S1 to S
At the timing of n, the display data latch 102
The gates (1) to 102 (n) are opened, and at this time, the display data LDx is fetched.

[0010]

In the liquid crystal driving device having the above configuration, the display data latches 102 (1) to 102 (1) to
When inspecting the leak current 102 (n), it is necessary to measure the leak current of the display data latches 102 (1) to 102 (n) in both the open state and the closed state of the gate. In the configuration of the liquid crystal driving device in FIG. 3, the display data capture signal S is shifted in accordance with the clock FY, so that the leakage of the display data latches 102 (1) to 102 (n) with the gate open is provided. Measure the current. FIG. 4 shows the leakage current measurement position (timing)
Are indicated by arrows. To measure the leakage current, for example, a current measuring device is provided in a power supply path to the display data latches 102 (1) to 102 (n), and the display data latch 102
(1) By measuring the current flowing to 102 (n),
You can ask.

In the above-described configuration, as the number of columns of the image display device increases and the shift register 103 has more bits, the leakage current when inspecting the leakage current of the display data latches 102 (1) to 102 (n) is increased. There is a problem that the number of times of measurement increases and the measurement time increases.

The display data latches 102 (1) to 102 (1) to 1
02 (n) is open and the remaining n-1 gates are closed, so that one of the display data latches 102 (1) -102 (n) is displayed. If the leak current of the data latch when the gate is open is measured, the leak current of the remaining n-1 display data latches when the gate is closed is automatically measured.

Therefore, the display data latch 102
If the leak current when the gate is open is measured for two display data latches of (1) to 102 (n), all display data latches 102 (1) to 102 (n) are measured.
For (n), the leakage current when the gate is closed is measured.

Before the shift operation of the display data latch signal S is started, the display data latches 102 (1) to 102 (1) to 102 (1) to
Since all the gates of 2 (n) are closed, if the leakage current is measured at this time, all the display data latches 10
This means that the leakage current when the gate is closed is measured for 2 (1) to 102 (n).

An object of the present invention is to provide a liquid crystal driving device capable of inspecting a leak current of a display data latch in a short time.

[0016]

According to a first aspect of the present invention, there is provided a liquid crystal driving apparatus comprising: a matrix type liquid crystal display having liquid crystal cells corresponding to respective pixels in a display area; The liquid crystal cell is driven based on display data sequentially input in time series for each clock corresponding to each of the liquid crystal cells, and includes a plurality of display data latches and a shift register.

A plurality of display data latches are provided corresponding to the liquid crystal cells of each column of the liquid crystal display device, respectively, and the display data latch signals input at timings corresponding to the liquid crystal cells of each column of the liquid crystal display device, respectively. Has a function to capture and hold display data in response to

The shift register has a number of shift stages corresponding to the number of columns of the liquid crystal cells of the liquid crystal display device. Normally, a shift operation corresponding to a clock causes a display data capture signal to be sequentially output from a shift stage that is sequentially different for each clock input. It has a function of selectively outputting and simultaneously outputting display data capture signals from all shift stages in response to the input of the set signal.

According to this configuration, by supplying the set signal to the shift register, the display data fetch signal is simultaneously output from all the shift stages of the shift register. As a result, the gates of all the display data latches can be simultaneously opened. Therefore, it is possible to perform a leak current measurement with a gate opened for a plurality of display data latches in one measurement. As a result, the leak current of the display data latch can be inspected in a short time.

A liquid crystal driving device according to a second aspect of the present invention is:
2. The liquid crystal driving device according to claim 1, wherein the shift register stops outputting the display data fetch signal from all shift stages in response to the input of the reset signal.

According to this configuration, by supplying the reset signal to the shift register, the output of the display data fetch signal from all shift stages of the shift register is stopped. As a result, the gates of all the display data latches can be simultaneously closed. Therefore, it is possible to execute the leak current measurement in a state where the gates are closed for a plurality of display data latches in one measurement. As a result, for a plurality of display data latches, it is possible to execute the leak current measurement in a state where the gate is opened and in a state where the gate is closed in two measurements,
The leak current of the display data latch can be inspected in a short time.

According to a third aspect of the present invention, there is provided a liquid crystal driving device.
3. The liquid crystal driving device according to claim 2, further comprising: a test control unit that receives a test signal and a test mode switching signal, and supplies a set signal to the shift register when the test signal is active and the test mode switching signal is active. The reset signal is supplied to the shift register when the test signal is active and the test mode switching signal is inactive.

According to this configuration, the operation state of the liquid crystal driving device can be easily switched by changing the combination of the state of the test signal and the state of the test mode switching signal supplied to the test control unit.

[0024]

FIG. 1 is a block diagram showing a basic configuration of a liquid crystal driving device according to an embodiment of the present invention. This liquid crystal driving device sequentially converts a matrix type liquid crystal display device having a liquid crystal cell corresponding to each pixel of a rectangular display area into a liquid crystal cell of each column of the liquid crystal display device in a time-series manner for each clock. , And as shown in FIG. 1, an input circuit 101, and n display data latches 102 (1) to 102 (n) each composed of, for example, a D flip-flop, n-stage shift register 106 and n D / A conversion units 104
(1) to 104 (n) and n output circuits 105 (1)
105 (n) and the test control unit 107.

An input circuit 101, n display data latches 102 (1) to 102 (n), n D / A converters 104 (1) to 104 (n), and n output circuits 105
Since (1) to 105 (n) have the same configuration as that of FIG. 3 of the conventional example, detailed description will be omitted.

The difference from the conventional example is that an n-stage shift register 106 is used instead of the n-stage shift register 103, and a test control unit 107 for testing a leak current is added. .

The n-stage shift register 106 is set to the number of shift stages corresponding to the number of columns of the liquid crystal cells of the liquid crystal display device, and usually, the display data fetch signal S corresponding to the clock FY.
Selectively outputs display data capture signals from output terminals G1 to Gn of shift stages that are sequentially different for each input of clock FY, and captures display data from all shift stages in response to the input of the set signal. A signal is output at the same time, and the output of the display data capture signal from all shift stages is stopped in response to the input of the reset signal.

That is, the shift register 103
It has a function of generating a timing at which the display data LDx output from the input circuit 101 is to be taken into each of the n display data latches 102 (1) to 102 (n). This shift register 106 is a cascade-connected N-stage D flip-flop with a set / reset input, and has, for example, a configuration as shown in FIG.

The test control unit 107 is composed of a logic circuit, and includes a test signal TEST and a test mode switching signal S.
When the test signal TEST is active and the test mode switching signal SET is active, the set signal SS is supplied to the shift register 106. When the test signal TEST is active and the test mode switching signal SET is inactive, , A reset signal RS is supplied to the shift register 106.

Here, the operation of the test control unit 107 will be specifically described. The test control unit 107 is controlled by a test signal TEST and a test mode switching signal SET,
For example, when performing the same normal operation as in FIG. 3, the test signal TEST is set to a low level (inactive). The operation at this time is the same as in the conventional example. At this time, the test mode switching signal SET is optional.

When measuring the leak current, the test signal TEST is set to a high level (active).
FIG. 2 is a timing waveform when the test signal TEST is set to a high level (when a leak current is measured). Test signal TES input to test control section 107
When the test mode switching signal SET is at the high level when T becomes the high level, the shift register 106 is set, and the state of the output signals G1 to Gn of all the shift stages of the shift register 106 is changed to the high level of all the bits. State can be set. If the leak current is measured at this time, it means that the leak current is measured when all the gates of the display data latches 102 (1) to 102 (n) are open.

When the test signal TEST is at a high level and the test mode switching signal SET is at a low level, the shift register 106 is reset and the shift register 1 is reset.
06, the state of the output signals G1 to Gn of all shift stages can be set to the state of all bit low levels. When the leak current is measured at this time, the display data latch 10
This means that the leak current was measured when all the gates 2 (1) to 102 (n) were closed.

FIG. 2 shows an example of a leak current measurement position (timing) in the embodiment by arrows. The previous arrow indicates that all display data latches 102 (1) to 102 (1) to
The timing of the measurement of the leak current in a state where the gates of 2 (n) are all closed is indicated by a later arrow. This is the timing for measuring the current.

According to the liquid crystal driving device of this embodiment,
By applying the set signal to the shift register 106, the display data capture signals S1 to Sn are simultaneously output from all the shift stages of the shift register 106 (all bits are at the high level), and the shift register 10
By giving the reset signal to 6, the output of the display data fetch signals S1 to Sn from all the shift stages of the shift register 106 is stopped (all the bits are in the low level state). As a result, all display data latches 1
02 (1) to 102 (n) can have their gates open at the same time, and all display data latches 102 (1) to 102 (n) can have their gates closed at the same time.

Therefore, the plurality of display data latches 10
2 (1) to 102 (n), the leak current measurement with the gate open can be performed by one measurement, and a plurality of display data latches 102 (1) to 102 (1) to 102 (n) can be executed.
For 2 (n), it is possible to perform the leak current measurement in a state where the gate is desired to be closed by one measurement. as a result,
In a liquid crystal driving device in which the shift register 106 has multiple bits with multiple outputs, the leakage current can be inspected in a short time.

The operation state of the liquid crystal driving device can be easily switched by changing the combination of the state of the test signal TEST and the state of the test mode switching signal SET given to the test control section 107.

[0037]

According to the liquid crystal driving device of the first aspect,
By applying the set signal to the shift register, the display data fetch signal is simultaneously output from all the shift stages of the shift register. As a result, the gates of all the display data latches can be simultaneously opened. Therefore, it is possible to perform a leak current measurement with a gate opened for a plurality of display data latches in one measurement. As a result, the leak current of the display data latch can be inspected in a short time.

According to the liquid crystal driving device of the present invention, by outputting the reset signal to the shift register, the output of the display data fetch signal from all the shift stages of the shift register is stopped. As a result, the gates of all the display data latches can be simultaneously closed. Therefore, it is possible to execute the leak current measurement in a state where the gates are closed for a plurality of display data latches in one measurement. As a result, for a plurality of display data latches, the leak current measurement with the gate open and the gate closed can be performed in two measurements, and the leak current inspection of the display data latch can be performed in a short time. It can be performed.

According to the liquid crystal driving device of the third aspect, the operation state of the liquid crystal driving device can be easily switched by changing the combination of the states of the test signal and the test mode switching signal supplied to the test control unit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal driving device according to an embodiment of the present invention.

FIG. 2 is a time chart showing an operation at the time of inspection of the liquid crystal driving device of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a conventional liquid crystal driving device.

FIG. 4 is a time chart showing an operation at the time of inspection of the liquid crystal driving device of FIG. 3;

FIG. 5 is a block diagram illustrating a specific example of a shift register.

[Explanation of symbols]

 Reference Signs List 101 input circuit 102 display data latch 103 shift register 104 D / A converter 105 output circuit 106 shift register 107 test control unit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA06 NC15 NC21 NC22 NC26 ND56 ND60 5C006 AA16 AC21 AF42 AF51 AF53 AF59 BB11 BC11 BF03 BF04 EB01 FA00 5C058 AA06 BA01 BA35 BB05 BB10 BB25 5C080 AA10 BB05 JJ05 DD12 DD15 DD02

Claims (3)

[Claims] 1. A matrix type liquid crystal display device having a liquid crystal cell corresponding to each pixel of a display area, and a liquid crystal cell of each column of the liquid crystal display device is sequentially and time-sequentially recorded for each clock. A liquid crystal driving device that is driven based on input display data, wherein the liquid crystal driving device is provided corresponding to each liquid crystal cell of each column of the liquid crystal display device, and has a timing corresponding to each liquid crystal cell of each column of the liquid crystal display device. A plurality of display data latches that respectively capture and hold the display data in response to the display data capture signal input at the same time, and have a number of shift stages corresponding to the number of liquid crystal cell columns of the liquid crystal display device. The display data capture signal is selectively output from a shift stage which is sequentially different for each input of the clock by a shift operation corresponding to the clock signal, and responds to the input of the set signal. A liquid crystal driving device that includes a shift register for outputting the display data accept signal simultaneously from all the shift stages Te. 2. The liquid crystal driving device according to claim 1, wherein the shift register stops outputting the display data fetch signal from all shift stages in response to the input of the reset signal. 3. A test control unit for inputting a test signal and a test mode switching signal is provided, and a set signal is supplied to a shift register when the test signal is active and the test mode switching signal is active. 3. The liquid crystal driving device according to claim 2, wherein a reset signal is supplied to the shift register when a signal is active and the test mode switching signal is inactive.