JP2002064521A - Transmitting apparatus and method, and program storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmitter that sets a correct time stamp to transmitting data with a simple configuration. SOLUTION: A transmission buffer memory 14 sequentially stores transmitting data to each buffer provided to its inside. A 1394 DMA controller 15 controls data transmission by each buffer of the transmission buffer memory 14 and acquires a time when the data transmission is finished in the case that transmission of data stored in one buffer is finished. A CPU 11 calculates a time stamp of the data stored in the buffer on the basis of the time when the data transmission is finished and a time required for transmission of data stored in other buffers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a transmission apparatus, a transmission method, and a program storage medium, and more particularly, to a transmission apparatus, a transmission method, and a program storage medium for transmitting time-stamped data.

[0002]

2. Description of the Related Art FIG. 1 shows a conventional IEEE (Institute of Ele).
FIG. 2 is a block diagram showing a configuration of a part of an apparatus for transmitting data by isochronous transmission via a bus (hereinafter, referred to as a 1394 bus) based on the criterion of ctrical and electronic engineers (1394).

[0003] The transmission buffer 1 temporarily stores isochronous transmission data transmitted by isochronous transmission. The isochronous transmission data stored in the transmission buffer 1 is used as an isochronous packet.
When transmitted via the 1394 bus, the dedicated CPU 2 transmits the cycle time (13
Get time on 94 bus).

[0004] The dedicated CPU 2 generates a time stamp based on the obtained cycle time, and adds the generated time stamp to the isochronous transmission data stored in the transmission buffer 1.

[0005] When the DV data is stored in the isochronous packet, the time stamp is CIP (Common Isoc).
hronous Packet), the value set in the SYT field,
Or, if the isochronous packet is MPEG (Moving Picture
If the transport stream packet is based on the Experts Group (-2) standard, the SPH (Source Packet Heade
r).

[0006]

As described above, a buffer and a dedicated CPU are required in order to set and transmit a correct time stamp to data stored in a packet, and a device configuration is complicated. And there is a problem that it becomes expensive.

The present invention has been made in view of such a situation, and an object of the present invention is to make it possible to set a time as a correct time stamp on data to be transmitted with a simple configuration.

[0008]

According to a first aspect of the present invention, there is provided a transmitting apparatus, comprising: a storage unit for sequentially storing data to be transmitted in a first area and a second area; and a first area or a second area. Transmission control means for controlling data transmission for each of
When transmission of data stored in the area is completed, an obtaining unit that obtains a time when the data transmission is completed, a time when the data transmission is completed, and a time when the data stored in the second area is transmitted. Calculating means for calculating the time of the next transmission of the data stored in the first area based on the required time.

[0009] The transmission control means can control data transmission according to a method defined in IEEE1394.

[0010] The transmitting device can include the data of the DVCR system in the data.

[0011] The transmitting device may include MPEG data in the data.

[0012] According to a fifth aspect of the present invention, there is provided the transmitting method, wherein the data to be transmitted is sequentially stored in the first area and the second area; A transmission control step of controlling the transmission of the data stored in the first area, an acquisition step of acquiring a time when the transmission of the data is completed, a time when the transmission of the data is completed, and a second step of: A calculating step of calculating the time of the next transmission of the data stored in the first area based on the time required for transmitting the data stored in the area.

According to a sixth aspect of the present invention, there is provided a program for storing a program in a storage medium for sequentially storing data to be transmitted in a first area and a second area; A transmission control step of controlling data transmission, an acquisition step of acquiring the time at which the data transmission has ended when the transmission of the data stored in the first area has ended, a time at which the data transmission has ended, and Second
And calculating a next transmission time of the data stored in the first area based on a time required for transmitting the data stored in the area.

In the transmission device according to the first aspect, the transmission method according to the fifth aspect, and the program storage medium according to the sixth aspect, data to be transmitted is sequentially stored in the first area and the second area. Data transmission is controlled for each of the stored first areas or the second areas, and when the transmission of the data stored in the first area is completed, the time when the data transmission is completed is obtained, The transmission time of the data stored in the first area is calculated based on the time when the transmission of the data stored in the first area is completed and the time required for transmitting the data stored in the second area.

[0015]

FIG. 2 is a block diagram showing the configuration of an embodiment of the transmitting apparatus according to the present invention.

The CPU 11 controls the entire transmitting device. CPU
11 executes a transmission program to control the hard disk controller 12 to read AV (Audio Video) data from the hard disk 13 and store the read AV data in the transmission buffer memory 14 as isochronous transmission data. . The CPU 11 uses a 1394 DMA (Dire
ct Memory Access) is stored in the transmission buffer 14 based on the cycle time (time on the 1394 bus) received from the controller 15 and the time required for transmitting the isochronous transmission data stored in the transmission buffer 14. A time stamp is set on the isochronous transmission data.

The hard disk controller 12 controls recording or reading of data on the hard disk 13. For example, the hard disk controller 12 has a CPU
11, the data supplied from the CPU 11 or the interface 16 is recorded on the hard disk 13 and the data read from the hard disk 13 is
The data is supplied to U11, the interface 16, or the transmission buffer memory 14.

The transmission buffer memory 14 is formed by securing an area of a part of a main memory in which a program executed by the CPU 11 is stored. Transmission buffer memory 1
4 may be configured by a dedicated semiconductor memory.

As shown in FIG. 3, the transmission buffer memory 14 includes buffers 51-1 to 51-4. The buffers 51-1 to 51-4 form a circular buffer (circulating buffer) based on a link list managed by the CPU 11.

That is, when data is stored in the transmission buffer memory 14, when data is stored at the end of the buffer 51-1, the next data is stored at the head of the buffer 51-2. When data is stored in the transmission buffer memory 14, when data is stored at the end of the buffer 51-2, the next data is stored at the head of the buffer 51-3. When data is stored in the transmission buffer memory 14, when data is stored at the end of the buffer 51-3, the next data is stored at the head of the buffer 51-4. When data is stored in the transmission buffer memory 14, when data is stored at the end of the buffer 51-4, the next data is stored at the head of the buffer 51-1.

When data is read from the transmission buffer memory 14, when data is read from the end of the buffer 51-1, the next data is read from the head of the buffer 51-2. When data is read from the transmission buffer memory 14, when data is read from the end of the buffer 51-2, the next data is stored in the buffer 51-2.
-3 is read from the beginning. Transmission buffer memory 14
, When data is read from the end of the buffer 51-3, the next data is read from the head of the buffer 51-4. When data is read from the transmission buffer memory 14, the buffer 51
When data is read from the end of -4, the next data is read from the head of the buffer 51-1.

The 1394 DMA controller 15 transfers the data stored in the transmission buffer memory 14 by a specified amount in each cycle of isochronous transmission of the 1394 bus.
Transferred (read), and the transferred data
The packet is transmitted as an isochronous packet on the 1394 bus with a 94 packet header attached.

FIG. 4 shows a DVCR (Digital Video Cassette R).
It is a figure which shows the example of the isochronous packet which stores the data of an ecording method.

The isochronous packet is, for example, 1394
Packet header, header CRC (Cyclic Redundancy Chec)
k), a CIP (Common Isochronous Packet) header, n data blocks, and a data CRC. The data stored in the transmission buffer memory 14 includes a CIP header, n data blocks, and a data CRC.
Consists of That is, the 1394 packet header and
The header CRC is added by the 1394DMA controller 15.

In the 1394 packet header arranged at the head of the isochronous packet, a data length field storing the number of bytes of the packet to be transmitted, a tag field storing a label related to the format of the isochronous packet, and an isochronous packet are transmitted. The channel field stores the number of the channel to be used, the tcode field stores the code that specifies the type of isochronous packet and the type of transaction, and the sy field stores the synchronization code used for application-specific control. Be placed.

The header CRC stores a code for detecting a header error.

In the CIP header, a SID field in which the transmission node ID is stored, and a data block size D are stored.
BS field, FN field that stores the number of data divisions, QPC field that stores the size of padding,
An SPH field for storing a header flag of a source packet, a DBC field for storing a count value of a data block, an FMT field for storing a format type indicating a data format stored in the data block, and the like are arranged.

The data stored in the data block is
When the format is DVCR, the CIP header contains
The number of fields per second, the video format, and the time stamp for frame synchronization are stored.

The time stamp for frame synchronization is shown in FIG.
Is stored in the SYT field shown in.

As the time stamp for frame synchronization of the DVCR stored in the SYT field, a value obtained by adding a fixed delay (450 μs) to the cycle time (time on the 1394 bus) corresponding to the beginning of the frame is set. . The receiving apparatus can generate a frame synchronization signal corresponding to a fixed delay based on the DVCR frame synchronization time stamp stored in the SYT field and the 1394 bus cycle time.

The data block stores image or audio data to be transmitted. In an isochronous packet, the number of data blocks can be zero. That is, it is possible to prevent data blocks from being included in the isochronous packet. At this time, the isochronous packet includes a 1394 packet header and a header CR.
Consists of only C and CIP headers.

The data CRC stores a code for detecting an error in a data block.

FIG. 5 is a diagram showing a cycle structure of data transmission on the 1394 bus. In the 1394 bus, data is divided into packets and transmitted in a time-division manner on the basis of a cycle having a length of 125 μS. This cycle is created by a cycle start signal supplied from a node having a cycle master function (any of the devices connected to the 1394 bus). The isochronous packet secures a band (corresponding to a channel, which is a unit of time but called a band) necessary for transmission from the beginning of every cycle. Therefore, in isochronous transmission, transmission of data within a certain time is guaranteed. However, if a transmission error occurs, there is no protection mechanism and data is lost. At a time not used for isochronous transmission in each cycle, the node that has secured the 1394 bus as a result of arbitration sends out an asynchronous packet. In asynchronous transmission, reliable transmission is guaranteed by using acknowledgment and retry, but the transmission timing is not constant.

The 1394 DMA controller 15 has a buffer 5
When the DMA transfer of the data for isochronous transmission ends for each of 1-1 to 51-4, the CPU 11 interrupts the CPU 11 to execute a DMA transfer end interrupt process. When interrupting the CPU 11, the 1394 DMA controller 15 acquires the cycle time of the 1394 bus at the time of completion of the transmission, and supplies the acquired cycle time to the CPU 11.

Subsequently, the 1394 DMA controller 15 reads the isochronous transmission data stored in any of the following buffers 51-1 to 51-4, and
The isochronous packet in each cycle of the bus is transmitted as an isochronous packet without interruption.

The CPU 11 sends a message from the 1394DMA controller 15
To obtain the cycle time of the 1394 bus when the transmission on the 1394 bus is completed, and to DMA transfer the obtained cycle time and the data stored in the other buffers 51-1 to 51-4. From the required number of cycles of the 1394 bus, the cycle time at which the data stored in the buffer whose transfer has been completed starts to be DMA-transferred next is calculated.

The CPU 11 calculates a time stamp to be set for the data stored in the buffer based on the cycle time at which the data stored in the buffer whose transfer has been completed starts to be DMA-transferred next.

For example, the transmission buffer memory 14 includes four buffers 51-1 to 51-4, and data stored in each of the buffers 51-1 to 51-4 is transmitted in 200 cycles of the 1394 bus. In this case, 600 cycles are required for transmitting the data stored in the buffers 51-2 to 51-4.

When the transmission of the data stored in the buffer 51-1 is completed, the cycle time of the 1394 bus is n.
, The next transmission of the data stored in the buffer 51-1 is started when the cycle time is (n + 600 * (cycle period)).

The CPU 11 reads the isochronous transmission data from the hard disk 13 via the hard disk controller 12 and writes the data to the buffer 51-1. The CPU 11 sets the time stamp of the data written in the buffer 51-1 to (n + 600 * (cycle cycle))
, And set the generated time stamp.

By doing so, the CPU 11 can set an accurate time stamp on the data stored in the isochronous packet.

The drive 17 reads data or a program recorded on the mounted magnetic disk 31, optical disk 32, magneto-optical disk 33 or semiconductor memory 34, and reads the data or the program.
The data is supplied to the CPU 11 or the main memory via the interface 16.

The CPU 11 through the interface 1
6 are interconnected by an internal bus.

Next, the processing of isochronous transmission by the transmitting device that executes the transmitting program will be described.

FIG. 6 is a flowchart for explaining isochronous transmission processing executed by the CPU 11 and the 1394 DMA controller 15. In step S11, the CP
U11 stores empty packets in the buffers 51-1 to 51-4 constituting the transmission buffer memory 14. Empty packets do not contain data blocks,
Consists of only the CIP header.

In step S12, the 1394 DMA controller 15 executes a DMA transfer process for the data stored in the transmission buffer memory 14, and the process ends.

The receiving device that has received the empty packet transmitted by the transmitting device discards the received empty packet. By sending an empty packet, 1394
The DMA controller 15 can acquire the cycle time without transmitting data to be transmitted. Further, the 1394 DMA controller 15 does not transmit data to be transmitted with an incorrect time stamp.

FIG. 7 is a flowchart for explaining the details of the DMA transfer process executed by the 1394 DMA controller 15. In step S31, the 1394 DMA controller 15 transfers the isochronous transmission data stored in any of the buffers 51-1 to 51-4, and
It is transmitted as an isochronous packet via the 94 bus.

When the process of step S31 is first executed for any of the buffers 51-1 to 51-4, the 1394 DMA controller 15 transmits an empty packet to the 1394 bus.

In step S32, the 1394 DMA controller 15 determines whether all the data stored in any one of the buffers 51-1 to 51-4 has been transferred, and If it is determined that all the data stored in any one of the four data has not been transferred, the process returns to step S31, and the data transfer process is repeated.

In step S32, the buffer 51-
When it is determined that all the data stored in any one of 1 to 51-4 has been transferred, the process proceeds to step S33, and the 1394 DMA controller 15 obtains the cycle time on the 1394 bus and obtains the cycle time. Cycle time to CPU
Notify 11

In step S34, the 1394 DMA controller 15 executes a DMA end interrupt, and
Returning to 31, the process is repeated.

When transmitting an empty packet before transmitting data to be transmitted and transmitting the data to be transmitted, a correct cycle time on the 1394 bus is obtained. , Cycle time on the 1394 bus.

Next, the processing of the DMA termination interrupt by the CPU 11 executing the transmission program, which is executed when the transfer of the data stored in the buffer 51-1 is completed, will be described with reference to the flowchart of FIG. ,explain.

In step S51, the CPU 11 determines
4 Acquire the cycle time of the 1394 bus at the time of completion of the transmission, supplied from the DMA controller 15.

In step S52, the CPU 11 obtains the number of cycles necessary for transferring the data stored in the other buffers, buffers 51-2 to 51-4.

At step S53, the CPU 11
Based on the cycle time at the end of the transfer and the number of cycles calculated in the process of step S52, the buffer 51-
A cycle time at which data transmission starts from 1 is determined.

In step S54, the CPU 11 sends the hard disk controller
In the buffer 51- as data for isochronous transmission.
1 is stored.

In step S55, the CPU 11 sets a time stamp on the isochronous transmission data stored in the buffer 51-1 based on the cycle time at which the next transmission starts, which is obtained in the processing in step S53. Ends.

When the transfer of the data stored in the buffers 51-2 to 51-4 is completed, the CPU 11 performs the same processing by the same processing as the isochronous transmission data stored in the buffers 51-2 to 51-4. To set a timestamp.

As described above, the CPU 11 controls the transmission buffer 1
4 can set a correct time stamp to the isochronous transmission data stored in the transmission data.

Therefore, the transmitting apparatus according to the present invention
There is no need to provide a CPU, and a correct time stamp can be set in an isochronous packet with a simple configuration.

The transmitting apparatus according to the present invention uses the SY of the DVCR.
As described above, the time stamp is set in the T field, but the SP of the MPEG-2 transport stream packet is described.
As long as the time stamp is set to data such as H, the time stamp can be set to any type of data.

The 1394 DMA controller 15 obtains the cycle time at the end of the transmission and
Described that the time stamp is generated based on the cycle time at the end of the transmission. However, the 1394 DMA controller 15 acquires the cycle time at the start of the transmission, and the CPU 11 A time stamp may be generated based on the cycle time.

The series of processes described above can be executed by hardware, but can also be executed by software. When a series of processing is executed by software, a program constituting the software can execute various functions by installing a computer built into dedicated hardware or installing various programs. It is installed from a program storage medium to a possible general-purpose personal computer or the like.

As shown in FIG. 2, a program storage medium for storing a program installed in a computer and made executable by the computer includes a magnetic disk 31 (including a floppy disk) and an optical disk 32 (CD-ROM (CD-ROM)). Compact Disc-Read Only Memory), DV
D (including a Digital Versatile Disc), a magneto-optical disk 33 (including an MD (Mini-Disc)), or a package medium including a semiconductor memory 34, a ROM in which a program is temporarily or permanently stored, , A hard disk 13 and the like. The storage of the program in the program storage medium can be performed by a router,
This is performed using a wired or wireless communication medium such as a local area network, the Internet, or digital satellite broadcasting via an interface such as a modem.

In this specification, the step of describing a program stored in a program storage medium is not limited to processing performed in chronological order according to the described order, but is not necessarily performed in chronological order. , And also includes processes executed in parallel or individually.

In this specification, the system is
It represents the entire device composed of a plurality of devices.

[0069]

According to the transmission device of the first aspect, the transmission method of the fifth aspect, and the program storage medium of the sixth aspect, transmission is performed to the first area and the second area. Data is sequentially stored, and data transmission is controlled for each of the first area and the second area. When the transmission of data stored in the first area is completed, the time when the data transmission is completed is obtained. Then, the time of the next transmission of the data stored in the first area is calculated based on the time when the data transmission is completed and the time required for transmitting the data stored in the second area. With this configuration, it is possible to set a correct time for data to be transmitted with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing the configuration of a conventional device.

FIG. 2 is a block diagram illustrating a configuration of an embodiment of a transmission device according to the present invention.

FIG. 3 is a diagram illustrating a configuration of a transmission buffer memory 14;

FIG. 4 is a diagram showing an example of DVCR data.

FIG. 5 is a diagram showing a cycle structure of data transmission on a 1394 bus.

FIG. 6 is a flowchart illustrating a process of isochronous transmission.

FIG. 7 is a flowchart illustrating details of a DMA transfer process.

FIG. 8 is a flowchart illustrating processing of a DMA end interrupt.

[Explanation of symbols]

11 CPU, 14 buffer memory for transmission, 15 1
394 DMA controller, 31 magnetic disk, 32 optical disk, 33 magneto-optical disk, 34 semiconductor memory, 51-1 to 51-4 buffer

Claims (6)

[Claims] 1. A storage unit for sequentially storing data to be transmitted in a first area and a second area, and transmission control for controlling transmission of the data for each of the first area and the second area. Means, when transmission of the data stored in the first area is completed, acquisition means for acquiring a time at which the transmission of the data is completed; time at which the transmission of the data is completed; and Transmitting means for calculating the time of the next transmission of the data stored in the first area based on the time required to transmit the data stored in the area . 2. The transmission apparatus according to claim 1, wherein the transmission control unit controls transmission of the data by a method defined in IEEE1394. 3. The transmitting apparatus according to claim 1, wherein the data includes data of a DVCR system. 4. The transmitting apparatus according to claim 1, wherein the data includes MPEG data. 5. A storage step of sequentially storing data to be transmitted in a first area and a second area, and transmission control for controlling transmission of the data for each of the first area and the second area. A step of: when the transmission of the data stored in the first area is completed, an acquiring step of acquiring a time at which the data transmission is completed; a time at which the data transmission is completed; and Calculating a next transmission time of the data stored in the first area based on a time required to transmit the data stored in the area. . 6. A storage step of sequentially storing data to be transmitted in a first area and a second area, and transmission control for controlling transmission of the data for each of the first area and the second area. A step of: when the transmission of the data stored in the first area is completed, an acquiring step of acquiring a time at which the data transmission is completed; a time at which the data transmission is completed; and Calculating the time of the next transmission of the data stored in the first area based on the time required to transmit the data stored in the area. A program storage medium that stores a readable program.