JP2002064182A - Integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit where the configuration of an external interface part such as a pad, terminal and the like is reduced for less size and price with higher integration. SOLUTION: A signal outputted outside from a signal processing circuit 10 is inputted, by twos, in a quadruple signal generating circuit 20, and converted into a single quadruple digital signal, then outputted from a semiconductor integrated circuit 1 through an output pad 30. If a quadruple signal is inputted in the semiconductor integrated circuit, each input signal ID1, is inputted in a binary signal generating circuit 50 through an input pad 40, and converted into two binary digital signals SI1 and SI2, and then inputted in the signal processing circuit 10. Thus, the number of pads and terminals comes to a half.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to integrated circuits,
In particular, the present invention relates to an integrated circuit that is smaller, has a higher degree of integration, and can be less expensive.

[0002]

2. Description of the Related Art In recent years, with the rapid miniaturization of semiconductor processes, a circuit having a very large gate scale can be configured on a semiconductor chip with a smaller area. It is expected to be even higher in the future. Under such circumstances, a circuit previously configured on a substrate using a plurality of semiconductor chips or a circuit configured as a single device is now realized on a single semiconductor chip. More and more cases are being done.

[0003]

By the way, although the degree of integration of the circuit itself on the semiconductor chip has been improved as described above, from the pad to the terminal necessary for interfacing the inside of the semiconductor chip with the outside, The size of the portion has not been reduced as much as the process miniaturization of the circuit portion. For this reason, even if the area of the circuit realized by the internal gate is reduced, a phenomenon called a so-called pad limit in which the area of the entire chip is determined by the area required for arranging the pads outside the chip has begun to be seen. As a result, even if the area required for internal gates is reduced, the total area of the chip cannot be drastically reduced unless the number of interfaces with the outside can be reduced. Alternatively, it is a great barrier to reduce product cost in realizing more functions and circuits on a semiconductor chip.

Accordingly, it is an object of the present invention to provide a smaller, more highly integrated, and less expensive integrated circuit which can reduce the configuration of external interface portions such as pads and terminals.

[0005]

In order to solve the above-mentioned problems, an integrated circuit according to the present invention performs desired signal processing and outputs a plurality of first multi-level signals having two or more signal levels. Processing means, and first multi-level signal conversion means for converting the plurality of first multi-level signals to be output into second multi-level signals having a smaller number of signals and a higher signal level;
Output means for outputting the converted second multi-level signal.

Preferably, a second multi-level signal for converting an input third multi-level signal having three or more signal levels into a fourth multi-level signal having a larger number of signals and a lower signal level The image processing apparatus further includes a conversion unit, and the signal processing unit performs the desired signal processing based on the converted plurality of fourth multi-level signals.

Preferably, the first multi-level signal converting means includes a reference voltage supplying means for supplying three or more reference voltages corresponding to the number of signal levels of a signal to be converted; Reference voltage selecting means for selecting and outputting any one of the supplied reference voltages based on the state of the multi-level signal. More preferably, the reference voltage selection unit is configured to select one of the supplied reference voltages based on states of the plurality of first multi-level signals, and Control means for controlling the output of the logic circuit so that noise based on the state transition of the logic circuit is not output. Specifically, the first
The multi-level signal conversion means is constituted by a digital / analog converter. More specifically, the first multi-level signal is:
m binary signals, wherein the second multi-level signal is one signal having 2 ^m signal levels, and wherein the first multi-level signal converting means includes m binary signals. 2 ^m based on
A multi-level signal having a plurality of signal levels is generated.

In another integrated circuit according to the present invention, a third multi-level signal having three or more signal levels to be input is
A second multi-level signal converting means for converting into a fourth multi-level signal having a larger number and a lower signal level than the multi-level signal; and a desired signal based on the plurality of converted fourth multi-level signals. Signal processing means for performing processing.

[0009] Preferably, the second multi-level signal conversion means supplies reference voltage of a plurality of signal levels which are boundaries between signal levels of each value of the input multi-level signal. Comparing means for comparing the input third multi-valued signal with each of the plurality of supplied reference voltages; and generating the plurality of fourth multi-valued signals based on the comparison result. A logic circuit. Also preferably, the second multi-level signal conversion means further includes a control means for controlling an output of the logic circuit so that a noise based on a state transition of the logic circuit is not output from the logic circuit. . Specifically, the second multi-level signal conversion means is constituted by an analog / digital converter. More specifically, the third multi-level signal is one multi-level signal having 2 ^m signal levels, the fourth multi-level signal is m binary signals, The second multi-level signal conversion means is 2 ^m
M multi-level signals having m signal levels
Generate a value signal.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
This will be described with reference to FIGS. FIG. 1 is a block diagram illustrating a configuration of a semiconductor integrated circuit 1 according to the present embodiment. The semiconductor integrated circuit 1 includes a signal processing circuit 10, m quaternary signal generation circuits 20 _{-1 to} 20 _-m , and m output pads 30 _-1 to 30 _-3.
0 _-m , n input pads 40 _-1 to 40 _-n and n 2 pads
It has value signal generation circuits 50 _-1 to 50 _-n .

The signal processing circuit 10 includes a memory, an arithmetic processing circuit, various logic circuits, and the like, and is a circuit that performs desired signal processing for the semiconductor integrated circuit 1 to realize a function as a chip. For this signal processing circuit 10, through n binary signal generation circuits 50 _-1 to 50 _-n ,
2n binary digital signals S _{I1 to} S _{I (2n)} are input,
2m via _m quaternary signal generation circuits 20 _{-1 to} 20 _-m
Two binary digital signals S _{O1 to} S _{O (2m)} are output.

The quaternary signal generation circuit 20 _-j (j = 1 to m)
Are 2m 2 outputs from the signal processing circuit 10, respectively.
Two signals S in the value digital signals S _{O1 to} S _{O (2m)
O (2j-1),} based on the _{S O (2j) (j =} 1~m), and outputs to generate a four-level digital output signal OD _j of one corresponding output pad 30 _-j.

When there are two binary digital signals S _o1 and S _O2, there are four combinations of these two digital signal values. In order to express all four states with a single node, it is conceivable that the output level, which is generally binary, is output as a quaternary level. In this way, information of two binary digital signals can be output from one terminal and one pad. When the four levels are set to level 0, level 1, level 2, and level 3 in order from the lowest level, the level is increased by two when the signal S _o1 is at the H level, and is increased when the signal S _O2 is at the H level. Is raised by one level, the states of the two signals can be expressed as shown in FIG. 2 corresponding to the H level and the L level of the signal S _o1 and the signal S _O2 . The quaternary signal generation circuit 20 _-j converts two binary digital signals into one quaternary digital signal in this manner.

The specific configuration of the quaternary signal generation circuit 20- _j that performs such processing will be described with reference to FIG. FIG. 3 is a diagram showing a configuration of the first quaternary signal generation circuit _20-1 . The quaternary signal generation circuit _20-1 includes the decoding unit 2
1, a signal transition control gate unit 22, a reference voltage supply unit 23, and a switch unit 24.

As shown in FIG.
And a AND circuit.
Two signals S to be applied_o1, S_O2Based on the state of the
Four levels, one of which is high level (H level)
Control signal C₀ ~ C_Three Generate Circuit as shown in FIG.
In the decoding unit 21 having the configuration, the signal signal S_o1And signal
S_O2Level system when the original is low level (L level)
Control signal C₀ Becomes H level, and the signal S_o1Is L level
At signal S_O2Is at the H level, the level control signal C ₁ Is H
Level and the signal S_o1Is H level and signal S_O2Is L
At the time of level, the level control signal C_Two Becomes H level,
Signal S_o1And signal S_O2At the time of the original H level
Control signal C_Three Becomes H level.

The signal transition control gate section 22 outputs the signals S _o1 ,
A control gate for preventing the noise, such as hazard rests level control signal C ₀ -C ₃ when the S _O2 transitions, composed of four gates corresponding to four-level control signal C ₀ -C ₃ of Is done. Each of these four gates
When a control mask signal from a control unit (not shown) in the semiconductor integrated circuit 1 is valid, it has a function of holding the input signal value up to that time and masking the input signal.

The reference voltage supply section 23 is a circuit for generating a reference voltage for generating a quaternary signal. The reference voltage supply unit 23 converts each of the four voltage levels divided by the three resistors disposed between VDD and VSS into a corresponding switch 2.
The voltage is applied to 4- _k (k = 1 to 4). In the present embodiment, the resistance values of these three configurations are 3r, 2r, and 3r from the VDD side as shown in the figure. At this time, each level is as follows: level 3 = VDD level 2 = VDD * 5/8 level 1 = VDD * 3/8 level 0 = VSS.

The switch section 24 has four switches 24 _{-1 to} 24 _-4 corresponding to the four voltage levels applied from the reference voltage supply section 23. When any one of the switches is turned on, The reference voltage supply unit 23 is connected to the switch.
The more applied voltage level is applied to the corresponding output pad. Each of the switches 24- _k is an analog switch that is turned on when an H level control signal is _supplied to the terminal S.

The quaternary signal generation circuit 20 _{-1 having} such a configuration is used.
, The two input binary digital signals S _o1 and S _O2
However, as shown in FIG. 2, one quaternary digital signal OD ₁
Is converted to

Each of the m output pads 30 _-1 to 30 _-m is wire-bonded to a terminal of a package of the semiconductor integrated circuit 1 using a gold wire or the like.
This is a terminal inside the semiconductor integrated circuit 1 for outputting a signal to the outside via the terminal. In the semiconductor integrated circuit 1,
Through the m output pads 30 _-1 to 30 _-m , m quaternary output signals OD _{1 to} OD _m are output.

Each of the n input pads 40 _-1 to 40 _-n is wire-bonded to a terminal of a package of the semiconductor integrated circuit 1 using a gold wire or the like.
This is a terminal inside the semiconductor integrated circuit 1 to which a signal is input from outside via the terminal. In the semiconductor integrated circuit 1, n 4 pads are provided via the n input pads 40 _-1 to 40 _-n.
Input signals ID ₁ ~ID _n values are entered.

The binary signal generation circuit 50 _-i (i = 1 to n)
Are _n quaternary input signals ID input to the semiconductor integrated circuit 1 via the _n input pads 40 _-1 to 40 _-n , respectively.
₁ ～ID based on one signal ID _i in _n, 2 pieces of signal S in binary digital signal of 2n present S _I1 to S _{I (2n)
I (2i-1)} and S _{I (2i)} (i = 1 to n) are generated and output to the signal processing circuit 10. More specifically, the binary signal generation circuit 50 _-i has, for example, a circuit configuration 4 as shown in FIG.
The four-level digital signal set to the level as shown in FIG. 2 generated by the value signal generation circuit _20-1 is decoded into two binary digital signals.

The specific configuration of the binary signal generation circuit 50- _i for performing such processing will be described with reference to FIG. FIG. 4 is a diagram showing a configuration of the first binary signal generation circuit _50-1 . Binary signal generating circuit 50 _-1 includes a reference voltage supply unit 51,3 amino comparators 52 _-1 to 52 _-3 and the encoding unit 53.

The reference voltage supply section 51 is a circuit for generating a comparison reference voltage of a comparator for restoring a quaternary signal into a binary signal. The reference voltage supply unit 51 compares the intermediate three voltage levels divided by the four resistors arranged between VDD and VSS with the corresponding comparators 52 _-k (k = 1 to
3). In the present embodiment, the resistance values of these three configurations are all the same as shown in the figure. At this time, the voltage level given to each comparator 52- _k is as follows: Comparator _52-3 : VDD.times.3 / 4 Comparator _52-2 : VDD.times.2 / 4 Comparator _52-1 : VDD.times.1 / 4.

The three comparators 52 _{-1 to} 52 _-3 are provided corresponding to the three voltage levels applied from the reference voltage supply unit 51, respectively.
0 and 4 value signal ID ₁ input to _-1, the reference voltage supply unit 5
Compare with each reference voltage applied from 1. And each, when the 4/5 value signals ID ₁ input high level, the signal level is H level comparison result signal C ₁ ~
The C _3, and outputs to the encoding unit 53. If the signal ID ₁ is input to the binarization signal generation circuit 50 _-1 was the signal of the same specification as that produced in the four-value signal generation circuit 20 _-1 described above, the comparator 52 _-1 to 52 _-3 signal C ₁ -C ₃ comparison result output from, the state shown in FIG.

The encoding unit 53 includes an inverter as shown in the drawing, a circuit constituted by the OR element and the AND element, substantially a signal C ₁ -C ₃ comparison result input from the comparator 52 _-1 to 52 _-3 Encoding, 2
The two binary signals S _I1 and S _I2 are generated and the signal processing circuit 10
Output to The relationship between the input comparison result signals C _{1 to} C ₃ and the output signals S _I1 and S _I2 in the encoding unit 53 having the circuit configuration shown in FIG. 4 is as shown in FIG. This means that the reverse conversion of the conversion from the binary digital signal to the quaternary digital signal performed by the signal generation circuit 20 is performed.

In the semiconductor integrated circuit 1 having such a configuration, in the signal processing circuit 10, desired processing is performed by a desired circuit based on a binary signal, as in a normal semiconductor integrated circuit. The signals output from the signal processing circuit 10 to the outside are input to the quaternary signal generation circuits 20 _-j (j = 1 to m) two by two.

In the quaternary signal generating circuit 20 _-j , the decoding unit 21 generates signals C _{0 to} C ₃ indicating four states indicated by two binary signals, and thereby the switches 24 _{-1 to} 24-24. _-4 is turned on, and the voltage level applied from the reference voltage supply unit 23 is output to the switch. That is, as shown in FIG. 2, conversion from two binary digital signals to one quaternary digital signal is performed. At this time, the signal transition control gate unit 2
2 controls signal switching so that noise such as a hazard does not appear. The signal output from the quaternary signal generation circuit 20 _-j is output from the semiconductor integrated circuit 1 via the output pad 30.

When such a quaternary signal is input to the semiconductor integrated circuit 1, each input signal ID _i (i =
1 to n) are input to the binary signal generation circuit 50 via the input pad 40. In the binary signal generation circuit 50,
Three reference voltage supply unit 5 to the comparator 52 _-1 to 52 _-3
1 and 4 value of the level of the boundary to become the signal level is applied from, in each of the comparators 52 _-1 to 52 _-3, the input signal ID _i is compared with the signal level to be the respective boundary. By encoding the comparison result, two binary digital signals S _I1 and S _I2 are generated as shown in FIG. The generated binary digital signal is input to the signal processing circuit 10 and used for desired signal processing.

As described above, in the semiconductor integrated circuit 1 according to the present embodiment, the signals at the time of input / output are quaternary signals, so that one terminal and one pad are used to provide two binary digital signals. A signal is output or two binary digital signals are input. Therefore, when inputting and outputting the same number of signals, the number of terminals and pads is set to 2
This can be reduced to の of the case of handling as a value signal. Therefore, the problem that the area of the semiconductor integrated circuit 1 cannot be reduced due to the pad, which is called a pad limit, can be solved, and the area of the semiconductor integrated circuit 1 can be further reduced. As a result, the effect of cost reduction due to process miniaturization can be effectively utilized, and a small-sized and inexpensive semiconductor chip can be provided.

Note that the present invention is not limited to the present embodiment, and any suitable various modifications are possible. For example, in the above-described embodiment, an 8-level signal and a 16-level signal using a quaternary signal as a multi-level signal are used, and three binary digital signals and four binary digital signals are used as one. Input and output may be performed via individual pads and terminals.

In the semiconductor integrated circuit 1 described above, the signal processing circuit 10 has 2n input signal lines and 2m input signal lines.
It is assumed that three output signal lines are provided. However, this does not indicate that the input signal and the output signal are even numbers, and it is easy to simply explain the binary signal generation circuits 50 _-1 to 50 _-n and the quaternary signal generation circuits 20 _{-1 to} 20 _-m. In order to Therefore, any number of input signals and output signals may be provided, including odd numbers. Further, a signal line for performing bidirectional data transfer may be provided. Such a signal line can be similarly converted into a quaternary signal and converted from a quaternary signal. Further, a multi-level signal may exist in the signal used in the signal processing circuit 10 in the first place. If the multi-level signal is the same as the multi-level signal generated by the quaternary signal generation circuit 20 or the multi-level signal input to the binary signal generation circuit 50, the signal is directly output or the direct signal processing circuit is output. 10 may be input.

Further, the quaternary signal generation circuit 2 of the present embodiment
As shown in FIG. 6, a circuit configuration for outputting a plurality of digital signals with one terminal and a pad corresponding to 0 can be configured using a so-called D / A converter of a relatively low bit. In addition, a circuit configuration for inputting a plurality of digital signals with one terminal and a pad corresponding to the binary signal generation circuit 50 of the present embodiment, as shown in FIG. It can be configured using a / D converter. It is clear that the semiconductor integrated circuit 1b as shown in FIG. 6 is also within the scope of the present invention.

The comparator 52_-1~ 52_-3comparison
Result C₁ ~ C_Three Based on the signal S _I1, S_I2Restore
The method is performed by the encoding unit 53 as shown in FIG.
Is not limited to any logic circuit, or
May be restored by any means. In addition, four-level signal
Like the signal transition control gate unit 22 provided in the circuit 20
The constituent parts of the encoding unit 53 of the binary signal generation circuit 50
It may be provided at a later stage. To do so
The transition of the signal generated by the binary signal generation circuit 50
The condition can be guaranteed.

For example, although input / output is normally performed by a binary signal, input / output is performed by a quaternary signal, for example, when a chip test of a semiconductor integrated circuit is performed, input / output is performed by a quaternary signal. The output may be selectively performed. In the operation at the time of the test, although a certain level of signal accuracy is ensured, there is a demand for efficient input / output of data as much as possible. Therefore, it is effective to apply input / output using such a quaternary signal. . In addition, a configuration may be adopted in which input and output are performed on only some of the selected signals using such quaternary signals.

[0036]

As described above, according to the present invention, the configuration of the external interface such as pads and terminals can be reduced, thereby providing a smaller, more highly integrated and less expensive integrated circuit. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a relationship between a binary signal and a quaternary signal in the quaternary signal generation circuit of the semiconductor integrated circuit illustrated in FIG. 1;

FIG. 3 is a block diagram showing a configuration of a quaternary signal generation circuit of the semiconductor integrated circuit shown in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of a binary signal generation circuit of the semiconductor integrated circuit illustrated in FIG. 1;

FIG. 5 is a diagram illustrating a relationship between an input signal and an output signal of the binary signal generation circuit illustrated in FIG. 4;

FIG. 6 is a block diagram illustrating another configuration example of the semiconductor integrated circuit according to the embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 10 ... Signal processing circuit, 20 ... 4-value signal generation circuit, 21 ... Decoding part, 22 ... Signal transition control gate part, 23 ... Reference voltage supply part, 24 ... Switch part
Reference Signs List 30 output pad, 40 input pad, 50 binary signal generation circuit, 51 reference voltage supply section, 52 comparator, 53 encoding section, 60 D / A conversion circuit, 70
... A / D conversion circuit

Claims (11)

[Claims] 1. A signal processing means for performing desired signal processing and outputting a plurality of first multi-valued signals having two or more signal levels; and outputting the plurality of first multi-valued signals to the signal. An integrated circuit comprising: first multi-level signal conversion means for converting into a second multi-level signal having a smaller number and higher signal level; and output means for outputting the converted second multi-level signal. 2. A second multi-level signal converting means for converting an input third multi-level signal having three or more signal levels into a fourth multi-level signal having a greater number of signals and a lower signal level. The signal processing means performs the desired signal processing based on the converted plurality of fourth multi-level signals.
An integrated circuit according to claim 1. 3. The first multi-level signal conversion means, wherein the first multi-level signal conversion means comprises: reference voltage supply means for supplying three or more reference voltages corresponding to the number of signal levels of a signal to be converted; 2. The integrated circuit according to claim 1, further comprising: reference voltage selecting means for selecting and outputting any one of the supplied reference voltages based on the state of the reference voltage. 4. A logic circuit for selecting one of the supplied reference voltages based on a state of the plurality of first multi-valued signals, the logic circuit comprising: 4. The integrated circuit according to claim 3, further comprising control means for controlling an output of said logic circuit so that noise based on a state transition of said logic circuit is not output. 5. The integrated circuit according to claim 1, wherein said first multi-level signal conversion means comprises a digital / analog converter. 6. The first multi-level signal is m binary signals, and the second multi-level signal has 2 ^m signal levels.
2. The integrated circuit according to claim 1, wherein the first multi-level signal conversion unit generates a multi-level signal having 2 ^m signal levels based on the ^m binary signals. 3. 7. A second multi-level signal for converting an input third multi-level signal having three or more signal levels into a fourth multi-level signal having a larger number and a lower signal level than the multi-level signal. An integrated circuit comprising: conversion means; and signal processing means for performing desired signal processing based on the converted plurality of fourth multi-level signals. 8. A reference voltage supply means for supplying each reference voltage of a plurality of signal levels which is a boundary between signal levels of each value of the input multi-value signal, Comparing means for comparing the input third multi-level signal with each of the plurality of supplied reference voltages; and a logic circuit for generating the plurality of fourth multi-level signals based on the comparison result The integrated circuit according to claim 7, comprising: 9. The second multi-level signal conversion means further includes control means for controlling the output of the logic circuit so that the logic circuit does not output noise based on the transition of the state of the logic circuit. An integrated circuit according to claim 8. 10. The integrated circuit according to claim 7, wherein said second multi-level signal conversion means comprises an analog / digital converter. 11. The third multi-level signal is one multi-level signal having 2 ^m signal levels; the fourth multi-level signal is m binary signals; 8. The integrated circuit according to claim 7, wherein the two multi-level signal conversion units generate m binary signals based on the multi-level signals having 2 ^m signal levels.