JP2002064181A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit where a crosstalk through a semiconductor substrate is reduced, resulting in shorter distance between circuit blocks, with no increase in a chip area and a cost. SOLUTION: A substrate noise removing circuit 38 is provided which positively controls the electric potential of a semiconductor substrate so that leaking-of the noise of a power source or a ground of a first circuit block 34 into another second circuit block 32 is offset. Thus, a crosstalk through the semiconductor substrate is reduced, resulting in shorter distance between the circuit blocks, with no increase in chip area and cost.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit in which an analog circuit and a digital circuit are mixed.

[0002]

2. Description of the Related Art In recent years, with the progress of high integration of semiconductor integrated circuits aiming at a system-on-chip, development of high-performance semiconductor integrated circuits mixed with digital circuits including front-end analog circuits has been advanced. I have.

FIG. 1 is a circuit diagram showing an example of a conventional analog / digital mixed semiconductor integrated circuit. In FIG. 1, an analog circuit 12 and a digital circuit 14 are mixedly mounted on a semiconductor integrated circuit 10. Between the analog circuit 12 and the digital circuit 14, a substrate resistance 1
There are six. Analog circuit 12, Digital circuit 14
Are connected to a power supply VDD and a ground GND via inductance components L1 to L4 corresponding to packages and bonding wires.

The analog circuit 12 is a front end unit for converting a minute input signal into a digital signal, and corresponds to, for example, an optical receiving circuit in an optical communication IC or an analog / digital conversion circuit in a signal processing IC. I do. The digital circuit processes a signal supplied from the analog circuit and outputs the processed signal to the outside. In the figure, the connection relationship between the analog circuit 12 and the digital circuit 14 is omitted for simplification.

FIG. 2A shows that the digital circuit 14 has a terminal 1
7 shows a signal waveform output from the digital circuit 7, and FIG. 2B shows a voltage waveform of the ground terminal 18 of the digital circuit 14. FIG. 2C shows an input signal waveform of the analog circuit 12, and FIG. 2D shows an output signal waveform of the analog circuit. However,
In order to clarify the influence on the analog circuit 12, only the digital circuit 14 operates, and the analog circuit 12
No signal is input. When the digital circuit 14 operates, crosstalk to the analog circuit 12 occurs. As a result, the analog circuit 12 generates noise despite no input.

[0006]

FIG. 3 is a sectional view showing a device structure of a CMOS semiconductor integrated circuit, and FIG. 4 is an equivalent circuit diagram thereof. 3 and 4, the same parts as those in FIG. 1 are denoted by the same reference numerals. 3 and 4, the ground GNDa of the transistor 24 constituting the digital circuit 14 is shown.
And the ground GNDb of the transistor 22 forming the analog circuit 12 are connected via a substrate resistor 16 of a P-type semiconductor substrate. Due to such coupling of the P-type semiconductor substrate, power supply or ground noise generated in the digital circuit 14 leaks into the ground of the analog circuit 12 via the substrate resistor 16 to generate crosstalk.

[0007] Further, the noise of the power supply or the ground that causes the crosstalk tends to increase as the frequency becomes higher, because the inductances L1 to L4 are the main factors. Although the power supply is insulated by the N-type wells 23 and 25 shown in FIG. 3, the junction capacity between the N-type wells 23 and 25 and the P-type semiconductor substrate (indicated by C1 and C2 in FIG. 4) is large. The impedance is low and the insulation is low with respect to the high-frequency components of noise, which is a problem in talk. Note that C
3-C6 is the capacitance between the input / output terminal and the power supply or ground,
Or it is the parasitic capacitance of the protection element of the input / output terminal.

Although such crosstalk is inherently small, the problem becomes evident as the speed of the semiconductor integrated circuit increases because the crosstalk has a large high-frequency component. Furthermore,
When an amplifier having a large gain is used to increase the sensitivity of an analog circuit that handles a minute input signal, crosstalk is amplified by the amplifier and appears at the output, so that it cannot be ignored. As described above, in a semiconductor integrated circuit in which an analog circuit and a digital circuit coexist, noise of a digital circuit leaks into the analog circuit due to crosstalk through the semiconductor substrate, which hinders an increase in the speed and sensitivity of the analog circuit. There was a problem that.

It is possible to suppress such crosstalk via the semiconductor substrate by increasing the distance between the analog circuit and the digital circuit. However, this countermeasure results in an increase in chip area and an increase in cost. There were challenges.

The present invention has been made in view of the above points, and can reduce crosstalk via a semiconductor substrate, does not require a large distance between circuit blocks, and increases chip area and cost. It is an object of the present invention to provide a semiconductor integrated circuit that does not cause the problem.

[0011]

According to the first aspect of the present invention, the ground or power supply noise of the first circuit block which generates noise is offset from leaking into the other second circuit block. In addition, by having a substrate noise elimination circuit that actively controls the potential of the semiconductor substrate, crosstalk through the semiconductor substrate can be reduced.

According to the second aspect of the present invention, the substrate noise elimination circuit feedback-controls the potential of the semiconductor substrate based on the reference potential from the second circuit block, thereby generating the first noise. It is possible to actively control the potential of the semiconductor substrate so as to cancel the noise of the ground or the power supply of the circuit block from leaking into another second circuit block.

According to a third aspect of the present invention, the substrate noise elimination circuit is based on an error between a first reference potential from the first circuit block and a second reference potential from the second circuit block. By controlling the potential of the semiconductor substrate in a feedforward manner, the noise of the ground or power supply of the first circuit block, which generates noise, is offset from the leakage of the semiconductor substrate to the other second circuit block. The potential can be actively controlled.

According to a fourth aspect of the present invention, there is provided a coupling degree control circuit for controlling the coupling degree for supplying an output of the substrate noise elimination circuit to the semiconductor substrate. Active control can reduce crosstalk.

According to the fifth aspect of the present invention, the semiconductor substrate is a high-resistance substrate, so that crosstalk can be further reduced.

According to the invention described in Supplementary Note 6, the coupling degree control circuit has a temperature sensor, and controls the coupling degree in accordance with a temperature detected by the temperature sensor to cope with a change in the coupling degree due to a temperature change. Thus, the degree of coupling can be actively controlled.

In the invention described in Supplementary Note 7, the coupling degree control circuit has a noise detection circuit that detects noise included in an output of the second circuit block, and the coupling control circuit includes a noise detection circuit that detects a noise included in the output of the second circuit block. By controlling the degree of coupling, a change in the degree of coupling can be detected by noise, and the degree of coupling can be actively controlled correspondingly.

In the invention described in Supplementary Note 11, the first circuit block is a digital circuit and the second circuit block is an analog circuit. Therefore, it is necessary to increase the distance between the analog circuit and the digital circuit. Thus, a semiconductor integrated circuit in which analog circuits and digital circuits are mixed can be easily realized without increasing the chip area and cost.

[0019]

FIG. 5 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit in which analog circuits and digital circuits are mixed according to the present invention.

In FIG. 1, an analog circuit 32 and a digital circuit 34 are mixedly mounted on a semiconductor integrated circuit 30.
Between the analog circuit 32 and the digital circuit 34, there are substrate resistors 36a and 36b made of a semiconductor substrate. A power supply terminal 32a and a ground terminal 32b of the analog circuit 32 are connected to a power supply VDD and a ground G via inductance components L11 and L12 corresponding to a package and a bonding wire.
The power supply terminal 34a and the ground terminal 34b of the digital circuit 34 are connected to the power supply VDD and the ground GND via inductance components L13 and L14 corresponding to packages and bonding wires.

The analog circuit 32 is a high-sensitivity front-end unit for converting a minute input signal into a digital signal. For example, the analog circuit 32 is an optical receiving circuit in an optical communication IC or an analog / digital conversion in a signal processing IC. It corresponds to a circuit. The digital circuit processes a signal supplied from the analog circuit and outputs the processed signal to the outside. Note that the connection relationship between the analog circuit 32 and the digital circuit 34 is omitted in the figure for simplification.

The substrate noise removing circuit 38 includes the analog circuit 3
2 of the semiconductor substrate to which the output terminal is connected based on the reference potential.
The potential at the point A, which is the connection point, is feedback-controlled. Thereby, the potential at the point A of the semiconductor substrate is controlled so that the substrate noise in the analog circuit 32 is reduced. For this reason, the point A of the semiconductor substrate to be controlled is preferably located near the digital circuit 34.

FIG. 6 is a circuit diagram of a first embodiment of the substrate noise elimination circuit 38. 5, the same parts as those in FIG. 5 are denoted by the same reference numerals. 6, the bias circuit 40 in the substrate noise elimination circuit 38 has a negative electrode connected to the ground terminal 32b of the analog circuit 32, a positive electrode connected to the non-inverting input terminal of the operational amplifier 42, and an operational amplifier 42. Ground terminal 32 biased by a predetermined voltage to the non-inverting input terminal of
The potential of b is supplied. The output terminal of the operational amplifier 42 is connected to the inverting input terminal to form a voltage follower. An output terminal of the operational amplifier 42 is connected to a capacitor 44.
Is connected to a point A which is a connection point between the substrate resistors 36a and 36b.

Thus, the feed hack control is performed so that the noise at the ground terminal 32b of the analog circuit 32 is minimized. Since the crosstalk component becomes a problem only at the high frequency, the output of the operational amplifier 42 is capacitively coupled to the point A by using the capacitor 44 to cut off the low frequency component.
If the operational amplifier 42 has a capability of driving a direct current,
It goes without saying that DC coupling can be performed by eliminating the capacitance.

FIG. 7 is a circuit configuration diagram of a second embodiment of the substrate noise elimination circuit 38. This is an embodiment in which the reference potential is taken from the power supply terminal 32a of the analog circuit 32. 6, the same parts as those in FIG. 6 are denoted by the same reference numerals. 7, the bias circuit 40 in the substrate noise elimination circuit 38 has a positive electrode connected to the power supply terminal 32a of the analog circuit 32,
The negative electrode is connected to the non-inverting input terminal of the operational amplifier 42, and the potential of the ground terminal 32b biased by a predetermined voltage is supplied to the non-inverting input terminal of the operational amplifier 42. The output terminal of the operational amplifier 42 is connected to the inverting input terminal to form a voltage follower. The output terminal of the operational amplifier 42 is connected to the substrate resistance 36a,
It is connected to point A which is a connection point of 36b.

Thus, the feed hack control is performed so that the noise at the power supply terminal 32a of the analog circuit 32 is minimized. Since the power supply VDD is strongly coupled to the ground GND at high frequencies due to the junction capacitance between the N-type well and the P-type semiconductor substrate, the same effect as in the embodiment of FIG. 6 can be obtained.

FIG. 8A shows a signal waveform output from the terminal 37a by the digital circuit 34 shown in FIG.
(B) shows the voltage waveform of the ground terminal 37b of the digital circuit 34. FIG. 8C shows an input signal waveform of the analog circuit 32, and FIG. 8D shows an output signal waveform of the analog circuit 32. However, in order to clarify the effect on the analog circuit 32, only the digital circuit 34 operates and the terminal 3
No signal is input to the analog circuit 32 from 7c.

FIGS. 8A to 8D show the waveforms of the present invention in FIG.
Compared with the conventional waveforms (A) to (D), the crosstalk to the analog circuit 32 is greatly reduced although the noise at the output terminal 37a and the ground terminal 37b of the digital circuit 34 are the same. It is clear that there is.

FIG. 9 is a circuit diagram of a second embodiment of a semiconductor integrated circuit in which analog circuits and digital circuits are mixed according to the present invention. In the figure, an analog circuit 52 and a digital circuit 54 are mixedly mounted on a semiconductor integrated circuit 50.
Between the analog circuit 52 and the digital circuit 54, there are substrate resistances 56a and 56b made of a semiconductor substrate. A power supply terminal 52a and a ground terminal 52b of the analog circuit 52 are connected to a power supply VDD and a ground G via inductance components L21 and L22 corresponding to a package and a bonding wire.
The power supply terminal 54a and the ground terminal 54b of the digital circuit 54 are connected to the power supply VDD and the ground GND via inductance components L23 and L24 corresponding to packages and bonding wires.
The analog circuit 52 is a high-sensitivity front-end unit that converts a minute input signal into a digital signal.

The substrate noise elimination circuit 58 includes the analog circuit 5
The reference potential of the digital circuit 54 and the reference potential of the digital circuit 54 are supplied, and the potential at the point B which is the connection point of the substrate resistances 56a and 56b of the semiconductor substrate to which the output terminal is connected is feedforward controlled based on both reference potentials. This allows
The potential at the point B on the semiconductor substrate is controlled so that the substrate noise in the analog circuit 52 is reduced. Although fine control is possible in the feedback control, there is a limit in speeding up, and high-speed control becomes possible by using the feedforward control.

FIG. 10 is a circuit diagram of a first embodiment of the substrate noise elimination circuit 58. In the figure, the same parts as those in FIG. 9 are denoted by the same reference numerals. In FIG. 10, the substrate noise elimination circuit 5
8, the negative electrode of the bias circuit 60 is connected to the ground terminal 52b of the analog circuit 52, the positive electrode is connected to the inverting input terminal of the differential amplifier 62 via the resistor R2, and the negative electrode of the bias circuit 61 is connected to the digital circuit. 54 grounding terminals 54b
And the positive electrode is connected to a differential amplifier 62 via a resistor R1.
And the inverting input terminal and the non-inverting input terminal of the differential amplifier 62 are supplied with the potentials of the ground terminals 52b and 54b biased by a predetermined voltage.

The inverting input terminal of the differential amplifier 62 is connected to an inverting output terminal via a resistor R3, and the non-inverting input terminal is connected to a ground terminal 52 of the analog circuit 52 via a resistor R4.
b to form a negative feedback amplifier circuit. Differential amplifier 6
The non-inverting output terminal 2 is connected via a capacitor 64 and a resistor 65 to a point B which is a connection point between the substrate resistors 56a and 56b.

Thus, a constant multiple of the noise at the ground terminal 54b of the digital circuit 54 is added to the substrate potential at the point B, and the feedforward control is performed. In this case, the degree of coupling to the substrate is determined by the gain of the differential amplifier 62 and the resistance of the resistor 65, and the gain and the resistance are determined according to the attenuation rate of the semiconductor substrate, that is, the resistance of the substrate resistors 56a and 56b. design.

FIG. 11 is a circuit diagram showing a second embodiment of the substrate noise elimination circuit 58. In the figure, the same parts as those in FIG. 10 are denoted by the same reference numerals, and the description thereof will be omitted. FIG. 11 differs in that the resistors R1 to R4 are deleted and the differential amplifier 62 is configured in an open loop. Such a simplification can be achieved by designing the gain of the differential amplifier 62 to be sufficiently stable. A substrate noise elimination circuit 58 is provided between the non-inverting output terminal of the differential amplifier 62 and the point B.
In order to eliminate the phase mismatch between the output of
A phase control circuit 66 is provided.

FIG. 12A shows a signal waveform output from the terminal 57a by the digital circuit 54 shown in FIG.
2 (B) shows a voltage waveform of the ground terminal 57b of the digital circuit 54. FIG. 12C shows an input signal waveform of the analog circuit 52, and FIG.
5 shows an output signal waveform of the first embodiment. However, to clarify the effect on the analog circuit 52, only the digital circuit 54 operates,
No signal is input to the analog circuit 52 from the terminal 57c.

When comparing the waveforms of the present invention shown in FIGS. 12A to 12D with the conventional waveforms shown in FIGS. 2A to 2D, the noise at the output terminal 57a and the noise at the ground terminal 57b of the digital circuit 54 are the same. However, it is clear that the crosstalk to the analog circuit 52 is greatly reduced.

FIG. 13 is a circuit diagram of a third embodiment of the semiconductor integrated circuit according to the present invention in which analog circuits and digital circuits are mixed. In the figure, the same parts as those in FIG. 9 are denoted by the same reference numerals. In FIG. 13, an analog circuit 52 and a digital circuit 54 are mixedly mounted on a semiconductor integrated circuit 50. Between the analog circuit 52 and the digital circuit 54, there are substrate resistances 56a and 56b made of a semiconductor substrate.
Power supply terminal 52a, ground terminal 52b of analog circuit 52
Are connected to a power supply VDD and a ground GND via inductance components L21 and L22 corresponding to packages and bonding wires, and a power supply terminal 54a and a ground terminal 54b of the digital circuit 54 are connected to inductance components corresponding to packages and bonding wires. L23, L
24, it is connected to the power supply VDD and the ground GND. The analog circuit 52 is a high-sensitivity front-end unit that converts a minute input signal into a digital signal.

The substrate noise elimination circuit 58 includes the analog circuit 5
The reference potential of the digital circuit 54 and the reference potential of the digital circuit 54 are supplied, and the potential at the point B which is the connection point of the substrate resistances 56a and 56b of the semiconductor substrate to which the output terminal is connected is feedforward controlled based on both reference potentials. The degree-of-coupling control circuit 68 controls the degree of coupling of the output of the substrate noise elimination circuit 58 to the point B according to the temperature, the noise of the analog circuit, and the like. That is, the degree of coupling is increased / decreased so as to offset fluctuations in the substrate resistance or the like due to temperature.

Thus, the potential at the point B on the semiconductor substrate is controlled so that the substrate noise in the analog circuit 52 is reduced. If the degree of coupling to the substrate changes due to temperature fluctuation or the like, normal noise removal becomes impossible. However, by dynamically controlling the degree of coupling, noise can be more stably removed.

FIG. 14 is a circuit diagram of a first embodiment of the substrate noise elimination circuit 58 and the coupling degree control circuit 68. In the figure, the same parts as those in FIG. 13 are denoted by the same reference numerals. In FIG. 14, the negative electrode of the bias circuit 60 in the substrate noise removing circuit 58 is connected to the ground terminal 52b of the analog circuit 52,
The positive electrode is connected to the inverting input terminal of the differential amplifier 62 via the resistor R2, the negative electrode of the bias circuit 61 is connected to the ground terminal 54b of the digital circuit 54, and the positive electrode is connected to the resistor R2.
1 is connected to the non-inverting input terminal of the differential amplifier 62, and the inverting input terminal and the non-inverting input terminal of the differential amplifier 62 have ground terminals 52b biased by a predetermined voltage.
Each of the potentials is supplied.

The inverting input terminal of the differential amplifier 62 is connected to an inverting output terminal via a resistor R3, and the non-inverting input terminal is connected to a ground terminal 52 of the analog circuit 52 via a resistor R4.
b, the non-inverting output terminal of the differential amplifier 62 is connected to the substrate resistors 56a,
It is connected to point B which is a connection point of 56b.

The coupling degree control circuit 68 comprises a temperature sensor 70, a controller 71 and a ROM 72. The temperature detected by the temperature sensor 70 is supplied to the controller 71. The controller 71 reads out control data corresponding to the detected temperature from the ROM 72, variably controls the resistance value of the variable resistor 69, and dynamically controls the degree of coupling. The resistance value of the variable resistor 69 can be digitally controlled by, for example, a selector. However, it is also necessary to use an FET as a resistor and control the gate bias of the FET in an analog manner. Is also possible. Thus, a fixed multiple of the noise at the ground terminal 54b of the digital circuit 54 is added to the substrate potential at the point B, and the feedforward control is performed.

In the above embodiment, the temperature is detected and the resistance value of the variable resistor 69 is variably controlled in order to compensate for a change in the coupling degree due to a change in the substrate resistance or the like due to the temperature. Alternatively, the configuration may be such that the substrate resistance is detected and the resistance of the variable resistor 69 is variably controlled in accordance with the substrate resistance.

FIG. 15 is a circuit diagram of a second embodiment of the substrate noise elimination circuit 58 and the coupling degree control circuit 68. 14, those parts that are the same as those corresponding parts in FIG. 14 are designated by the same reference numerals, and a description thereof will be omitted. 15, the coupling degree control circuit 68 includes a noise detection circuit 74, a controller 75, and a ROM 76. The noise detection circuit 74 detects the level of noise included in the output signal of the analog circuit 52 and supplies the same to the controller 71. The controller 75 reads out control data according to the detected noise level from the ROM 76 and variably controls the resistance value of the variable resistor 69 to dynamically control the degree of coupling. That is, when the detection noise level is high, control is performed to increase the degree of coupling, and the substrate noise is reduced.

As described above, by detecting the noise of the output of the analog circuit 52, although the control is complicated, pseudo feed hack control can be performed, and fine control can be performed. During the input of the analog signal to the analog circuit 52, noise cannot be detected. For example, after the power is turned on, stabilization is performed, control data corresponding to the detected noise level is read, and input of the analog signal is performed. It is preferable to hold the control data during the operation.

FIG. 16 is a circuit diagram of a third embodiment of the substrate noise elimination circuit 58 and the coupling degree control circuit 68. 14, those parts that are the same as those corresponding parts in FIG. 14 are designated by the same reference numerals, and a description thereof will be omitted. 16, a positive electrode of a bias circuit 60 is connected to an inverting input terminal of a differential amplifier 62 via a variable resistor 80, and a positive electrode of the bias circuit 61 is connected to a variable resistor 82.
Is connected to the non-inverting input terminal of the differential amplifier 62 via

The inverting input terminal of the differential amplifier 62 is connected to an inverting output terminal via a resistor R3, and the non-inverting input terminal is connected to a ground terminal 52 of the analog circuit 52 via a resistor R4.
b, and the non-inverting output terminal of the differential amplifier 62 is connected to the substrate resistors 56a, 56
It is connected to point B, which is the connection point of b.

The coupling degree control circuit 68 comprises a temperature sensor 70, a controller 77 and an analog conversion circuit 78. The temperature detected by the temperature sensor 70 is
The analog conversion circuit 78 converts the detected temperature into an analog control signal value. The controller 77 supplies this analog control signal value to the variable resistors 80 and 82 and variably controls the resistance values of the variable resistors 80 and 82 to dynamically control the degree of coupling.

FIG. 17 is a circuit diagram of a fourth embodiment of a semiconductor integrated circuit according to the present invention in which an analog circuit and a digital circuit are mixed. 5, the same parts as those in FIG. 5 are denoted by the same reference numerals. In FIG. 17, an analog circuit 92 and a digital circuit 94 are provided in a semiconductor integrated circuit 90 using a high-resistance substrate.
And are mixed. A high-resistance substrate resistor 9 made of a semiconductor substrate is provided between the analog circuit 92 and the digital circuit 94.
6a and 96b are present.

A power supply terminal 92a and a ground terminal 92b of the analog circuit 92 are connected to a power supply V via an inductance component L31, L32 corresponding to a package or a bonding wire.
The power supply terminal 94a and the ground terminal 94b of the digital circuit 94 are connected to the power supply VDD and the ground GND via inductance components L33 and L34 corresponding to packages and bonding wires. The analog circuit 92 is a high-sensitivity front-end unit that converts a minute input signal into a digital signal. In the figure, the analog circuit 92 is shown for simplicity.
The connection between the digital circuit 94 and the digital circuit 94 is omitted.

FIG. 6 or FIG.
Is supplied with a reference potential of the analog circuit 92 (for example, the potential of a ground terminal 92b biased by a predetermined voltage), and a high-resistance circuit connected to an output terminal based on the reference potential. Substrate resistance 96a,
Feedback control is performed on the potential at point C, which is the connection point of 96b. As a result, the potential at the point A of the semiconductor substrate is controlled so that the substrate noise in the analog circuit 92 is reduced. It should be noted that a circuit similar to the substrate noise elimination circuit 58 shown in FIG. 9 may be used instead of the substrate noise elimination circuit 98.

FIG. 18 is a sectional view showing a device structure of a first embodiment of a semiconductor integrated circuit using a high resistance substrate.
In the figure, as the high resistance substrate 100, for example, a P having a resistivity of 100 [Ω · cm] or more is obtained by reducing doping.
Type semiconductor substrate is used. N-type wells 102A and 102B are formed on the high resistance substrate, and N-type wells 102A and 102B are formed.
P-type wells 104A and 104B are formed in 102B to form a triple well structure. Then, an analog circuit 92 is formed in the N-type well 102A and the P-type well 104A, and the N-type well 102B and the P-type well 1 are formed.
A digital circuit 94 is formed in 04B.

If the high-resistance substrate 100 is used as a bulk of a MOS transistor, the bulk potential is likely to fluctuate and latch-up is likely to occur. Therefore, the triple well structure is used to form the N-type wells 102A and 102B and the P-type wells 104A and 104B. Is stabilized.

FIG. 19 is a sectional view showing a device structure of a second embodiment of a semiconductor integrated circuit using a high resistance substrate.
In the figure, an insulator film 112 is formed on a high-resistance substrate 110, P-type wells 114A and 114B are formed thereon, and an N-type well 11 is formed in the P-type wells 114A and 114B.
6A and 116B are formed and SOI (Silicon
on Insulator) structure. Then, an analog circuit 92 is formed in the P-type well 114A and the N-type well 116A, and the P-type wells 114B and N
A digital circuit 94 is formed in the mold well 116B. In this embodiment, in addition to the high isolation characteristics of the SOI structure, a reduction in crosstalk via the high resistance substrate 110 can be expected.

FIG. 20 is a sectional view showing a device structure of a third embodiment of a semiconductor integrated circuit using a high resistance substrate.
In the figure, an insulator film 122 is formed on a high resistance substrate 120, and a P-type well 124A and an N-type well 126 are formed thereon.
A and P-type wells 124B and N-type wells 126B are formed to have an SOI structure. Then, the P-type well 124
An analog circuit 92 is formed in the A and N wells 126A, and a digital circuit 94 is formed in the P well 124B and the N well 126B. In this embodiment, a fully depleted MOS transistor can be realized by thinning the semiconductor layer, and ideal characteristics can be realized as a MOS transistor having an SOI structure.

FIG. 21 is a sectional view showing a device structure of a fourth embodiment of a semiconductor integrated circuit using a high-resistance substrate.
In the figure, an N-type well 132A is formed on a high-resistance substrate 130, and a P-type well 134A is formed in the N-type well 132A to form a triple well structure. At the same time, an insulator film 136 is formed on the high-resistance substrate 130,
A P-type well 138B and an N-type well 140B are formed thereon to form an SOI structure. And P-type well 1
The analog circuit 92 is formed in the 32A and N-type well 134A, and the digital circuit 94 is formed in the P-type well 138B and the N-type well 140B.

In this embodiment, only the digital circuit 94 has an SOI structure, and the analog circuit 92 is formed on a high resistance substrate 130 as a triple well structure. Such a partial SOI structure is, for example, a SIMOX (Sepa)
ratio by Implanted Oxyge
n) by applying the target technique. The MOS transistor on the SOI structure has a large variation in characteristics and a complicated model, so that it is difficult to use the MOS transistor in the high-sensitivity analog circuit 92.
Since a normal MOS transistor can be formed in a triple-well structure, characteristics can be improved.

In the above embodiment, a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixed has been described. However, only the crosstalk between the digital circuit and the analog circuit has the greatest effect. It is needless to say that the same effect can be obtained with only the semiconductor integrated circuit of the present embodiment, and it is not limited to the above embodiment.

The digital circuit 34 corresponds to the first circuit block described in the claims, and the analog circuit 32 corresponds to the second circuit block.
Circuit block.

(Supplementary Note 1) In a semiconductor integrated circuit in which a plurality of circuit blocks are formed in common on a single semiconductor substrate, noise of the ground or power supply of the first circuit block that generates noise is reduced by noise of another second circuit block. A semiconductor integrated circuit having a substrate noise elimination circuit that actively controls a potential of a semiconductor substrate so as to cancel leakage into a block. (1) (Supplementary note 2) In the semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit, wherein the substrate noise removing circuit feedback-controls a potential of the semiconductor substrate based on a reference potential from the second circuit block.
(2) (Supplementary Note 3) In the semiconductor integrated circuit according to claim 1,
The substrate noise elimination circuit includes a first reference potential from the first circuit block and a second reference potential from the second circuit block.
A feed-forward control of the potential of the semiconductor substrate based on an error with respect to a reference potential of the semiconductor integrated circuit. (3) (Supplementary Note 4) In the semiconductor integrated circuit according to claim 3,
A semiconductor integrated circuit, comprising: a coupling degree control circuit for controlling a coupling degree for supplying an output of the substrate noise elimination circuit to the semiconductor substrate. (4) (Supplementary Note 5) The semiconductor integrated circuit according to any one of claims 1 to 4, wherein the semiconductor substrate is a high-resistance substrate. (5) (Supplementary note 6) In the semiconductor integrated circuit according to claim 4,
The semiconductor integrated circuit according to claim 1, wherein the coupling degree control circuit has a temperature sensor, and controls the coupling degree according to a temperature detected by the temperature sensor.

(Supplementary Note 7) The semiconductor integrated circuit according to claim 4, wherein the coupling degree control circuit has a noise detection circuit for detecting noise included in an output of the second circuit block, and the noise detection circuit Wherein the degree of coupling is controlled in accordance with a detection value of (i).

(Supplementary Note 8) In the semiconductor integrated circuit according to supplementary note 5, the semiconductor substrate has a resistivity of 100 [Ω · c].
m] or more.

(Supplementary Note 9) The semiconductor integrated circuit according to supplementary note 5, wherein the first and second circuit blocks have a triple-well structure on the semiconductor substrate.

(Supplementary Note 10) The semiconductor integrated circuit according to supplementary note 5, wherein the first and second circuit blocks have an SOI structure on the semiconductor substrate.

(Supplementary Note 11) The semiconductor integrated circuit according to any one of claims 1 to 10, wherein the first circuit block is a digital circuit, and the second circuit block is an analog circuit. Characteristic semiconductor integrated circuit.

[0066]

As described above, the first aspect of the present invention provides
A substrate noise elimination circuit that actively controls the potential of the semiconductor substrate so as to cancel the noise of the ground or power supply of the first circuit block that generates noise from leaking into the other second circuit block. Thereby, crosstalk via the semiconductor substrate can be reduced. That is, noise generated in the ground or the power supply of the first circuit block is detected, and the potential of the semiconductor substrate is actively stabilized with a component that cancels the noise, thereby suppressing crosstalk to the second circuit block. Therefore, there is no need to increase the distance between circuit blocks, and there is no increase in chip area and cost.

According to the second aspect of the present invention, the substrate noise elimination circuit controls the electric potential of the semiconductor substrate based on a reference electric potential from the second circuit block, thereby generating the first noise. It is possible to actively control the potential of the semiconductor substrate so as to cancel the noise of the ground or the power supply of the circuit block from leaking into another second circuit block.

According to a third aspect of the present invention, the substrate noise elimination circuit is based on an error between a first reference potential from the first circuit block and a second reference potential from the second circuit block. By controlling the potential of the semiconductor substrate in a feedforward manner, the noise of the ground or power supply of the first circuit block, which generates noise, is offset from the leakage of the semiconductor substrate to the other second circuit block. The potential can be actively controlled.

According to a fourth aspect of the present invention, there is provided a coupling degree control circuit for controlling the coupling degree for supplying the output of the substrate noise elimination circuit to the semiconductor substrate. Active control can reduce crosstalk.

According to the fifth aspect of the present invention, the semiconductor substrate is a high-resistance substrate, so that the crosstalk can be further reduced.

According to the invention described in Supplementary Note 6, the coupling degree control circuit has a temperature sensor, and controls the coupling degree in accordance with the temperature detected by the temperature sensor to cope with a change in the coupling degree due to a temperature change. Thus, the degree of coupling can be actively controlled.

In the invention described in Supplementary Note 7, the coupling degree control circuit has a noise detection circuit that detects noise included in an output of the second circuit block, and the coupling control circuit includes a noise detection circuit that detects a noise included in an output of the second circuit block. By controlling the degree of coupling, a change in the degree of coupling can be detected by noise, and the degree of coupling can be actively controlled correspondingly.

In the invention described in Supplementary Note 11, since the first circuit block is a digital circuit and the second circuit block is an analog circuit, it is necessary to increase the distance between the analog circuit and the digital circuit. Thus, a semiconductor integrated circuit in which analog circuits and digital circuits are mixed can be easily realized without increasing the chip area and cost.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an example of a conventional analog / digital mixed semiconductor integrated circuit.

FIG. 2 is a signal waveform diagram of each section of the circuit of FIG.

FIG. 3 is a sectional view illustrating a device structure of a CMOS semiconductor integrated circuit.

FIG. 4 is an equivalent circuit diagram of FIG.

FIG. 5 is a circuit configuration diagram of a first embodiment of a semiconductor integrated circuit in which an analog circuit and a digital circuit are mixed according to the present invention.

FIG. 6 is a circuit configuration diagram of a first embodiment of a substrate noise elimination circuit 38;

FIG. 7 is a circuit configuration diagram of a second embodiment of the substrate noise elimination circuit 38;

8 is a signal waveform diagram of each part of the circuit of FIG.

FIG. 9 is a circuit configuration diagram of a second embodiment of the semiconductor integrated circuit according to the present invention in which analog circuits and digital circuits are mixed.

FIG. 10 is a circuit configuration diagram of a first embodiment of the substrate noise elimination circuit 58;

FIG. 11 is a circuit configuration diagram of a second embodiment of the substrate noise elimination circuit 58;

FIG. 12 is a signal waveform diagram of each section of the circuit of FIG. 9;

FIG. 13 is a circuit configuration diagram of a third embodiment of a semiconductor integrated circuit in which an analog circuit and a digital circuit are mixed according to the present invention.

FIG. 14 is a diagram illustrating a substrate noise elimination circuit 58 and a coupling degree control circuit 6;
8 is a circuit configuration diagram of the first embodiment of FIG.

FIG. 15 shows a substrate noise elimination circuit 58 and a coupling degree control circuit 6;
FIG. 8 is a circuit configuration diagram of a second example 8;

FIG. 16 shows a substrate noise elimination circuit 58 and a coupling degree control circuit 6;
8 is a circuit configuration diagram of a third example of FIG.

FIG. 17 is a circuit configuration diagram of a fourth embodiment of the semiconductor integrated circuit according to the present invention in which analog circuits and digital circuits are mixed.

FIG. 18 is a sectional view illustrating a device structure of a first embodiment of a semiconductor integrated circuit using a high-resistance substrate.

FIG. 19 is a sectional view illustrating a device structure of a second embodiment of a semiconductor integrated circuit using a high-resistance substrate.

FIG. 20 is a sectional view illustrating a device structure of a third embodiment of the semiconductor integrated circuit using the high-resistance substrate.

FIG. 21 is a cross-sectional view illustrating a device structure of a fourth embodiment of a semiconductor integrated circuit using a high-resistance substrate.

[Explanation of symbols]

 Reference Signs List 30 semiconductor integrated circuit 32 analog circuit 32a, 34a power supply terminal 32b, 34b ground terminal 34 digital circuit 36a, 36b substrate resistance 38 substrate noise elimination circuit 40 bias circuit 42 operational amplifier 44, 64 capacitor 58 substrate noise elimination circuit 62 differential amplifier 65 Resistance 68 Coupling degree control circuit 74 Noise detection circuit

Claims (5)

[Claims] In a semiconductor integrated circuit in which a plurality of circuit blocks are formed in common on one semiconductor substrate, noise of a ground or a power supply of a first circuit block generating noise is transmitted to another second circuit block. A semiconductor integrated circuit having a substrate noise elimination circuit that actively controls a potential of a semiconductor substrate so as to cancel leakage. 2. The semiconductor integrated circuit according to claim 1, wherein said substrate noise elimination circuit feedback-controls a potential of said semiconductor substrate based on a reference potential from said second circuit block. Integrated circuit. 3. The semiconductor integrated circuit according to claim 1, wherein said substrate noise elimination circuit includes a first reference potential from said first circuit block and a second reference potential from said second circuit block.
A feed-forward control of the potential of the semiconductor substrate based on an error with respect to a reference potential of the semiconductor integrated circuit. 4. The semiconductor integrated circuit according to claim 3, further comprising a coupling degree control circuit for controlling a coupling degree for supplying an output of said substrate noise removing circuit to said semiconductor substrate. 5. The semiconductor integrated circuit according to claim 1, wherein said semiconductor substrate is a high-resistance substrate.