JP2002064099A - Manufacturing method of embedded wiring structure body - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem where a recessed part of 200-400 Å is formed around the central part of the wiring when an embedded wiring is formed in the substrate. SOLUTION: An embedded wiring structure body is manufactured by burying wiring material whose thermal expansion factor is different from that of a substrate in a groove formed at the substrate. Here, a manufacturing method of the embedded wiring structure body comprises a process where a groove is formed on the substrate, a process where the surface of the substrate comprising the groove is covered with the wiring material, and a process where the substrate covered with the wiring material is polished at a low temperature to remove the wiring material except for that remaining in the groove.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, thin-film magnetic heads, and other structures requiring a fine wiring structure, and more particularly to a buried wiring structure embedded in a substrate. The present invention relates to a method for manufacturing a wiring structure in which a step between a portion and a substrate can be extremely reduced or intentionally increased.

2. Description of the Related Art In a fine wiring structure such as a semiconductor device and a thin film magnetic head, it is sometimes necessary to form a buried wiring in a substrate for various reasons. "Embedded wiring"
Means that a wiring formed by filling a groove formed in a substrate with a wiring material. The feature is that the substrate on which the wiring is formed can be flattened. As a method of forming wiring on a substrate, there is also a method of forming wiring in a convex shape on a flat substrate,
In this method, irregularities are formed on the substrate by the thickness of the wiring, so that a plurality of wiring layers are piled up, so that the level difference becomes larger, and the wiring in the upper layer is more likely to be disconnected.

Therefore, in the case of a fine wiring structure and a structure having a plurality of wiring layers, embedded wiring is often used. In a conventional method of manufacturing an embedded wiring, a wiring is formed in a convex shape on a substrate, the wiring is covered with an insulating material, and the unevenness of the insulating material reflecting the unevenness of the wiring is polished with a polishing device to flatten the surface of the insulating material. It was a method of becoming. However, when wiring becomes finer, it is more likely that a wiring structure defect will not occur in the manufacturing process if a groove is first formed in the substrate and a wiring material is buried in the groove, rather than forming the wiring on the substrate in a convex shape. I understand. Therefore, when multi-level wiring of the submicron rule is required at present, a groove is first formed on the surface of the substrate on which the wiring is to be formed, and the entire surface of the substrate including the groove is covered with the wiring material. The embedded wiring structure is manufactured by removing the unnecessary wiring material formed in the portion described above.

Specifically, a surface of a silicon substrate is oxidized to form an insulating material layer, and a groove is formed in the insulating material layer by using a technique such as ion etching or reactive ion etching. The width of the groove is submicron and the depth is at most about 1 micron. Next, a wiring material is formed on the surface of the substrate having the grooves formed thereon by a thin film forming technique such as sputtering or vapor deposition. At this time, the groove is completely filled with the wiring material. Since the wiring material is necessary only for the groove portion and the wiring material formed in the other portions is unnecessary, these unnecessary wiring materials are removed. For this removal, reverse sputtering, RIE, plasma etching or the like is used.

However, complete flattening is difficult if unnecessary materials are removed by these methods. Therefore, recently, chemical mechanical polishing (hereinafter referred to as "CMP") is used. According to this method, even if the diameter of the substrate is 10 inches or more, the entire surface of the substrate can be flattened, and the flatness can be compared with the conventional one. When an unnecessary wiring material is removed by these methods, a buried wiring can be formed in the substrate, and when another wiring structure is formed on this wiring, there is no unevenness of the base, thereby facilitating the manufacture. Although the above description has been made with a semiconductor device in mind, the same applies to a manufacturing process of a thin-film magnetic head employing a similar manufacturing process.

As described above, in the manufacture of a buried wiring structure using fine wiring, a polishing step by CMP is basically employed. But,
CMP uses free abrasive grains, and when a plurality of materials are exposed on the polished surface, a difference in polishing rate occurs depending on the materials. For example, when the wiring material is a metal material such as a semiconductor device and a thin-film magnetic head, and the surrounding substrate material is an insulating material, the metal material tends to be polished faster under CMP under the same conditions. , The surface of the embedded wiring is slightly uneven.

More specifically, in the case of wiring of a general semiconductor device, a concave portion of about 200 to 400 angstroms is formed substantially at the center of the wiring. Such a phenomenon is called dishing because the dent resembles the dent of a dish plate. Although it is difficult to completely eliminate the dishing, it is important to reduce the dishing to 50 Å or less in order to ensure the ease of manufacturing the semiconductor device.
In addition, although the phenomenon is similar to dishing, dents may occur entirely in a portion where structures having a high polishing rate such as metal wiring are densely formed, and this phenomenon is called thinning. this is,
Basically, it is a phenomenon caused by the same cause as dishing.

An object of the present invention is to provide a method of manufacturing a buried wiring structure which minimizes dishing and thinning and ensures high flatness of the surface of a substrate on which a buried wiring is formed. It is a further object of the present invention to provide a method of manufacturing a buried wiring structure in which a buried wiring portion has a sufficiently large recess on a substrate, contrary to the above object. In the prior art, naturally formed recesses are 20
This is in order to cope with a case where a concave portion having a depth of about 0 Å but larger than this is desired.

In order to solve these problems, a wiring material having a thermal expansion coefficient different from that of the substrate is buried in a groove formed in the substrate to form a buried wiring structure. A method of manufacturing, wherein a step of forming a groove in the substrate, a step of coating the surface of the substrate including the groove with the wiring material, and polishing the substrate coated with the wiring material at a low temperature, Removing the other wiring material while leaving the wiring material in the groove. Here, the name of the present invention is "embedded wiring", but it is needless to say that this wiring is not necessarily limited to a conductive one and is not limited to a so-called linear one.

If the substrate material and the material embedded in the substrate have different coefficients of thermal expansion, the material of the wiring to be applied may be an insulating material, and the "groove" formed in the substrate may be a mere hole, for example. A via hole and a through hole may be formed, and the shape may be a circular shape, or may be a concave portion or a concave portion for forming a spread and planar bonding land. Further, the “substrate” is not limited to a plate. For example, a shape having a large thickness such as a cubic shape or a rectangular parallelepiped shape may be used. Further, the substrate does not need to be made of a single material. For example,
A plurality of layers of different materials may be stacked. For example, an insulating layer is formed on a silicon substrate, and a buried wiring is formed in the insulating layer.
The present invention is also applied to a case where a transistor, a capacitor, and a wiring are formed on a silicon substrate, and an insulating layer is formed so as to cover them, and then a buried wiring is formed in the insulating layer, that is, a multilayer wiring structure. can do.

The term "embedded wiring" as used in the present invention means that the wiring material embedded in the groove of the substrate and the wiring material embedded in the surface of the substrate is exposed. It is used for the purpose of including any one completely embedded in a concept including an insulating layer or the like to be subsequently coated). Also, as a more concrete example of this,
The method for manufacturing a buried wiring structure according to claim 1, wherein the substrate is a semiconductor substrate, and the step of forming the groove is a step of forming a groove in an insulating layer of the semiconductor substrate. ). The wiring material is aluminum,
3. The method for manufacturing an embedded wiring structure according to claim 1, wherein the substrate is a material made of any one of copper, tungsten, and gold or a combination thereof. 4. The method for manufacturing a buried wiring structure according to claim 1, wherein the step of removing the wiring material while leaving the wiring material in the groove is performed at a room temperature or lower. 5. The method according to claim 1, wherein the step of polishing the substrate at a low temperature and removing the other wiring material while leaving the wiring material in the groove is performed by water-cooling the substrate holding surface of the polishing apparatus. The method of manufacturing a buried wiring structure according to claim 5, wherein the step of polishing the substrate at a low temperature and removing the other wiring material while leaving the wiring material in the groove includes removing the cooled abrasive. Claim 1 by using 5. The method for manufacturing a buried wiring structure according to any one of claims 5 to 5, wherein the substrate is polished at a low temperature to remove a wiring material while leaving a wiring material in the groove. The method according to any one of claims 1 to 6, wherein the method is performed by cooling a surface plate of a polishing apparatus (claim 7).
8. The step of polishing the substrate at a low temperature and removing other wiring material while leaving the wiring material in the groove is performed by chemical mechanical polishing (CMP).
The method of manufacturing a buried wiring structure according to any one of (1) to (4), wherein the step of polishing the substrate at a low temperature and removing the other wiring material while leaving the wiring material in the groove includes: The method for manufacturing a buried wiring structure according to any one of claims 1 to 8, which is performed at a temperature equal to or lower than 0 degree Celsius, which is different from a thermal expansion coefficient of the substrate in a groove formed in the substrate. A method of manufacturing a buried wiring structure by embedding a wiring material having a coefficient of thermal expansion, a step of forming a groove in a substrate, and a step of coating a surface of the substrate including the groove with the wiring material. A step of annealing the substrate covered with the wiring material, and a step of polishing the annealed substrate at a low temperature to remove the other wiring material while leaving the wiring material in the groove. Body manufacturing method (Claim 10 And the step of polishing the substrate at a low temperature and removing the other wiring material while leaving the wiring material in the groove is performed by fixing polishing abrasive grains on a surface plate and dripping lubricating oil. A method of manufacturing a buried wiring structure according to claim 1 or 10 (the method according to claim 11) is provided.

While the above-mentioned components require polishing the substrate at a low temperature, on the other hand, polishing the substrate at a high temperature is one of the components.
The following can be mentioned. That is, a method for manufacturing a buried wiring structure by burying a wiring material having a thermal expansion coefficient different from the thermal expansion coefficient of the substrate in a groove formed in the substrate, the step of forming a groove in the substrate,
A step of coating the surface of the substrate including the groove with the wiring material, followed by annealing, and polishing the annealed substrate at a high temperature to remove the other wiring material while leaving the wiring material in the groove. And a method of manufacturing a buried wiring structure including the steps of:

A method of manufacturing a buried wiring structure by embedding a wiring material in an insulating layer, wherein forming a groove as a buried wiring is not an essential component, the method comprises forming a wiring on a substrate. And a step of coating the surface of the substrate including the wiring with the insulating material, and a step of polishing the substrate coated with the insulating material at a low temperature to remove the insulating material on the wiring. A method of manufacturing a buried wiring structure by embedding a wiring material in an insulating layer, the method including forming a wiring on a substrate, and a method of manufacturing the buried wiring structure. Covering the surface of the substrate with the insulating material, annealing the substrate coated with the insulating material, polishing the annealed substrate at a low temperature to remove the insulating material on the wiring And a method of manufacturing a buried wiring structure by embedding a wiring material in an insulating layer, wherein a wiring is formed on a substrate. And a step of coating the surface of the substrate including the wiring with the insulating material,
Polishing the substrate coated with the insulating material at a high temperature to remove the insulating material on the wiring (claim 15). A method of manufacturing an embedded wiring structure by embedding in a layer, a step of forming a wiring on a substrate, a step of coating a surface of the substrate including the wiring with the insulating material, and a step of coating the surface with the insulating material. A method of manufacturing a buried wiring structure including the step of annealing a substrate that has been annealed, and the step of polishing the annealed substrate at a high temperature to remove an insulating material on the wiring. provide. Furthermore, in order to polish the wafer evenly, it is necessary to prevent any dripping from occurring at the end face of the wafer, that is, at the outer peripheral portion of the wafer. From this viewpoint, the wafer holder is arranged so as to elastically press the polishing pad surface. A CMP polishing apparatus having a structure to be polished, wherein the wafer holder comprises a wafer chuck portion for holding a back surface of a wafer to be polished, and a retainer ring surrounding an outer peripheral portion of the wafer,
The wafer chuck section and the retainer ring provide a CMP polishing apparatus having a structure in which a polishing pad surface is elastically pressed independently of each other. More specifically, the CMP polishing apparatus according to claim 17, wherein the pressing force of the wafer chuck portion can be made larger than the pressing force of the retainer ring portion. Is good. In other words,
As a solution, there is provided a CMP polishing apparatus having a structure in which a wafer holder is arranged so as to elastically press a polishing pad surface, wherein the wafer holder comprises a wafer chuck portion for holding a back surface of a wafer to be polished, and a wafer chuck. And a retainer ring surrounding the outer peripheral portion of the polishing pad. The CMP polishing apparatus is capable of sinking a polishing pad into a contact surface of the retainer ring with the polishing pad more deeply than a polishing target surface of the wafer during wafer polishing. 19) can be provided. Further, the inventions according to claims 17 to 19 are shown from the viewpoint of a method.
A method of manufacturing a wafer using a CMP polishing method, wherein a polishing target surface of a wafer is pressed against a polishing pad, and a part of the polishing pad on the outer periphery of the wafer is sunk into the polishing pad deeper than the polishing target surface to perform the CMP polishing. A method of manufacturing a wafer (as recited in claim 20) is provided. Further, from the viewpoint of an optimum wafer shape for the solution means of claims 17 to 20, the outer shape of the wafer is circular, and the wafer manufacturing method of claim 20 is provided. I do. Further, there is provided a CMP polishing apparatus capable of separately measuring the pressure of the wafer chuck and the pressure of the retainer ring (claim 22).

Embodiments of the present invention will be described below in the order of the claims.

First, regarding the invention according to claim 1, the invention according to claim 1 is, as described above, a wiring having a thermal expansion coefficient different from that of the substrate in the groove formed in the substrate. A method of manufacturing a buried wiring structure by embedding a material for use, the step of forming a groove in the substrate,
Covering the surface of the substrate including the groove with the wiring material, and polishing the substrate coated with the wiring material at a low temperature to remove the wiring material while leaving the wiring material in the groove; And a method for manufacturing a buried wiring structure.

FIGS. 1 to 5 are conceptual diagrams showing the present invention simply by taking a method of manufacturing a semiconductor device as an example. First, as shown in FIG. 1, when a silicon substrate is prepared and an oxide layer 2 is formed on the surface thereof, the oxide layer 2 is laminated on the silicon layer 3. A groove 1 for wiring is formed in the oxide layer 2. The groove 1 is formed to have a line width of about 0.1 μm and a groove depth of about 0.3 μm using a photolithography technique. Next, as shown in FIG. 2, a wiring material 4 is formed so as to cover the surface of the substrate on which the groove is formed. This wiring material 4 is copper, aluminum or the like. The formation of these wiring materials 4 is performed by sputtering, vapor deposition, or other various film forming techniques. At this time, the groove must be formed so that the inside of the groove is completely filled with the wiring material 4. For example, the film thickness is about 0.5 μm. Next, FIG.
The substrate covered with the wiring material is polished at a low temperature as shown in FIG. The low temperature state refers to a temperature equal to or lower than room temperature as described above, but is not necessarily limited to this. In this embodiment, the photolithography process for forming the groove is performed at room temperature, that is, about 20 to 25 degrees Celsius in the next step of forming the wiring in the upper layer, so that the polishing in this step is performed at 10 degrees Celsius. . The polishing method employs CMP polishing.

This polishing method is not a method of accelerating the polishing step only by physical cutting, but utilizes a chemical reaction generated between the workpiece and the abrasive due to the pressure applied microscopically by the abrasive grains. And promote
This is the most suitable polishing method for a structure that is unlikely to cause unnecessary damage to a work and is easily affected by a change in physical properties of a substrate such as a semiconductor device. FIG. 6 is a conceptual diagram of a substrate holding structure of an apparatus for holding a substrate in a low temperature state.
It is. As shown in this figure, a low-temperature liquid or gas 12
Is poured 13 toward the substrate holding surface, the temperature is increased by circulating the substrate holding surface, and then discharged 14 to the outside. Therefore, the substrate 11 can be kept at a low temperature by this liquid or gas.

As described above, since the chemical reaction acts to promote the polishing, in order to ensure the necessary polishing rate in the process at the time of low-noise polishing, the number of components which promote the chemical reaction should be larger than that at room temperature. You may need to. Immediately after the completion of the polishing, the temperature is still low, so a slight dent 5 is formed at the center of the cross section of the wiring as shown in the figure. This may be smaller at low temperatures than at room temperature, but it is still difficult to reduce it to 200 angstroms or less. Next, as shown in FIG. 4, when the entire substrate is returned to room temperature, copper as the wiring material has a larger coefficient of thermal expansion than the silicon oxide layer 2, so that the copper as the wiring material becomes The buried wiring 6 which expands more than the surrounding silicon oxide film and has a small dent seen immediately after the polishing is completed is formed.

For example, the depth of the dent can be set to about 20 angstroms. With this degree of depression, it becomes easy to form an oxide layer on top of this and to form a buried wiring in the oxide layer. If this dent is large, the wiring formed on it must be formed over the unevenness, and the resistance value will vary in some places, and the amount of dents of the unevenness will accumulate as the upper layer becomes a multilayer wiring. Therefore, for example, around the fifth layer, even if the wiring is not thickened, there is even a risk of disconnection.
FIG. 5 shows that it is easy to form a multilayer when manufactured by applying the present invention. In this embodiment, the case where the buried wiring of the first layer is a conductive wiring has been described. However, as described above, the present invention is not limited to this. It can also be used when the groove is formed of silicon oxide. In the figure, a second layer further formed on the first layer has a buried wiring 8 disposed in a layer 7 of an insulating material similarly to the first layer. Although the temperature largely depends on the temperature in other steps, it is generally 15 ° C. or less, preferably 10 ° C. or less.
These are appropriately determined by the difference in thermal expansion coefficient between the wafer and the wiring material. Generally, since the wiring material is a metal material and the wafer is a non-metallic material, the difference in thermal expansion coefficient is large, and
In many cases, it is better to perform the reaction at a temperature of not more than ℃.

Next, according to a second aspect of the present invention, as described above, a wiring material having a thermal expansion coefficient different from the thermal expansion coefficient of the substrate is embedded in a groove formed in the substrate. A method of manufacturing a buried wiring structure, comprising the steps of forming a groove in a substrate, covering the surface of the substrate including the groove with the wiring material, and forming the substrate covered with the wiring material. Polishing at a low temperature to remove the other wiring material while leaving the wiring material in the groove, and assuming a method of manufacturing a buried wiring structure, wherein the substrate is a semiconductor substrate and the groove is formed. 2. The method according to claim 1, wherein the step is a step of forming a groove in the insulating layer of the semiconductor substrate.

Although this embodiment has already been described in the description of the embodiment of the present invention, it will not be described in detail, but at present, multilayer wiring is an indispensable technology as semiconductor devices become more and more highly integrated. This is a manufacturing method that is indispensable for the manufacture of semiconductor devices.

Next, according to a third aspect of the present invention, as described above, the wiring material is aluminum,
3. The method for manufacturing a buried wiring structure according to claim 1, wherein the material is one of copper, tungsten, and gold. This is because a highly integrated circuit can be formed by using a conductive material as a wiring material. Of course, high integration of this wiring is not only a technology useful for semiconductor devices, but also thin film magnetic heads, thin film transformers, various sensors,
It is useful for liquid crystal display panels and the like. Although not claimed in claim 3, it is already described that the inventions described in claims 1 and 2 do not aim at only high integration of the conductive wiring.

According to a fourth aspect of the present invention, the step of polishing the substrate at a low temperature and removing the other wiring material while leaving the wiring material in the groove is performed at room temperature or lower. Item 4. A method for manufacturing a buried wiring structure according to any one of Items 1 to 3. The present invention is a more specific example of how low a temperature should be polished. Generally, such electronic components and semiconductor devices are manufactured at room temperature, that is, at room temperature. Therefore, if only the polishing step of the wiring material is performed at room temperature or lower, the temperature of the entire substrate is increased in the other manufacturing steps as compared to immediately after the polishing is completed. Can be.
In the case of copper wiring buried in silicon oxide, the difference between the thermal expansion systems of silicon oxide and copper as described above in the description of the first embodiment of the present invention ensures that the deformation is secured. Cause.

Next, in the invention according to claim 5, the step of polishing the substrate at a low temperature to remove the other wiring material while leaving the wiring material in the groove is performed by removing the substrate holding surface of the polishing apparatus. The method for producing a buried wiring structure according to any one of claims 1 to 4, which is performed by water cooling. The present invention specifically clarifies how to ensure a low temperature during polishing.

Similarly, in the invention according to claim 6, the step of polishing the substrate at a low temperature to remove the wiring material while leaving the wiring material in the groove is performed by using a cooled abrasive. A method for manufacturing a buried wiring structure according to any one of items 1 to 5, wherein the invention according to claim 7 is
7. The method according to claim 1, wherein the step of polishing the substrate at a low temperature and removing the other wiring material while leaving the wiring material in the groove is performed by cooling a surface plate of a polishing apparatus. This is a method for manufacturing an embedded wiring structure. These two inventions are also embodiments of lowering the temperature during polishing, as in the invention described in claim 5.

Next, according to an eighth aspect of the present invention, the step of polishing the substrate at a low temperature and removing the other wiring material while leaving the wiring material in the groove is performed by a chemical mechanical method. The method of manufacturing an embedded wiring structure according to any one of claims 1 to 7, wherein the method is performed by polishing (CMP). As described above, this polishing method is a polishing method suitable for a case where a change due to a processing strain of physical properties of a substrate is likely to cause a product defect, such as in the manufacture of a semiconductor device.
In addition, a semiconductor device can be used because a polishing apparatus that can secure a mirror surface and can process a large substrate can be used.
Suitable for manufacturing other electronic components.

Next, according to a ninth aspect of the present invention, as described above, the step of polishing the substrate at a low temperature and removing the other wiring material while leaving the wiring material in the groove is performed at 0 degree Celsius. 9. The method for manufacturing a buried wiring structure according to claim 1, wherein the method is performed at a temperature of not more than 10 degrees. In the invention according to claim 4, it has been clarified that the temperature lower than room temperature is suitable as a polishing condition at a low temperature. In addition, since the brittleness of the material changes and the material becomes relatively hard, there is an advantage that the dripping of the wiring material at the boundary between the wiring and the substrate is reduced, and a so-called sharp wiring shape can be obtained.

Next, according to the tenth aspect of the present invention, a buried wiring structure is manufactured by burying a wiring material having a thermal expansion coefficient different from that of the substrate into a groove formed in the substrate. Forming a groove in the substrate, coating the surface of the substrate including the groove with the wiring material, annealing the substrate coated with the wiring material, Polishing the substrate at a low temperature to remove the other wiring material while leaving the wiring material in the groove. A feature of the present invention is that an annealing step is provided as a pre-process for polishing at a low temperature. As described above, the wiring material is generally formed into a thin film by a vacuum device. However, the gas is mixed in the formed thin film rather than in a completely vacuum state. That is, it is not a completely pure metal. Further, since the content of the gas and the like cannot be easily controlled, the characteristics of the wiring material slightly differ from one production batch to another. This affects the expansion behavior of the material when returning to room temperature after polishing at low temperatures,
Despite apparently manufactured under the same conditions, some have completely lost the recess in the cross section of the wiring, and some have yet to show that the recess has not been sufficiently removed. Therefore, the whole substrate is annealed before polishing at a low temperature in order to improve the reproducibility of the form when the temperature is returned to the normal temperature. This is because, by annealing, the gas contained in the wiring material is released to the outside to make it less affected by the gas. For example, annealing may be performed at 200 degrees Celsius for about 2 to 3 hours. However, when the strength of the wiring structure is not sufficient, structural destruction occurs due to thermal stress due to this thermal expansion, or residual stress occurs even when mechanical strength is sufficient. Therefore, annealing was performed at about 100 degrees Celsius for about 10 hours. Sometimes it is better.

Next, an eleventh aspect of the present invention will be described. As described above, in the present invention, the step of polishing the substrate at a low temperature and removing the other wiring material while leaving the wiring material in the groove is performed by fixing polishing abrasive grains on a surface plate and dropping lubricating oil. The method for manufacturing a buried wiring structure according to claim 1, wherein the method is performed while performing the method. In the case of CMP polishing, when free abrasive grains are used, there is a problem that the abrasive grains are concentrated on a relatively soft portion of the material and the polishing speed of that portion is relatively high. This mechanism is one of the reasons why the cross section of the metal wiring film is formed in a concave shape. FIG. 7 shows this state. As shown in this figure, loose abrasive particles are retained on the surface plate.
There are also 1 and 32, but they accumulate in soft parts of the material embedded in the grooves formed in the substrate. As shown in FIG. 8, the present invention solves the above-mentioned problem by converting the abrasive grains into fixed abrasive grains 22 on a surface plate 21 while being in the category of loose abrasive grains. This is called slurry charging. The polishing is performed while dropping the lubricating oil and the lubricating liquid 23, and the microscopic polishing operation is exactly the same as in the case of polishing using free abrasive grains. By combining this slurry charging with low-temperature polishing, the recesses in the cross section of the wiring can be made smaller and shallower.

Next, a twelfth aspect of the present invention will be described. A method of manufacturing an embedded wiring structure by embedding a wiring material having a thermal expansion coefficient different from the thermal expansion coefficient of the substrate into a groove formed in the substrate, the method comprising: forming a groove in the substrate; A step of coating the surface of the substrate including the wiring material, and a step of polishing the substrate covered with the wiring material at a high temperature and removing the other wiring material while leaving the wiring material in the groove, This is a method for manufacturing a buried wiring structure including: The present invention is characterized in that polishing is performed at a high temperature. Polishing is performed at a high temperature, and when the temperature is returned to normal temperature, a material shrinks, so that when the wiring made of a metal material embedded in an insulating material is manufactured by polishing, the buried wiring is formed immediately after the polishing is completed. Even if the surface is finished with some recesses in the wiring portion, the metal material shrinks as the temperature returns to normal temperature, and the wiring portion can be formed into a relatively large concave shape at normal temperature. For example, a material having a dent of about 200 angstroms immediately after polishing can be reduced to about 400 angstroms when the temperature is returned to normal temperature. Although it is possible to form such a dent by ordinary polishing, the present invention is characterized in that reproducibility is better.

Next, according to a thirteenth aspect of the present invention, there is provided a method of manufacturing a buried wiring structure by embedding a wiring material in an insulating layer, comprising the steps of forming a wiring on a substrate and including the wiring. A method of manufacturing an embedded wiring structure, comprising: a step of coating a surface of a substrate with the insulating material; and a step of polishing the substrate coated with the insulating material at a low temperature to remove the insulating material on the wiring. It is. The method of manufacturing the wiring structure described so far is a method of forming a groove in a substrate and embedding a wiring material in the groove to form a wiring.
In the present invention, wiring is formed first without forming a groove,
This wiring is buried with an insulating material and then polished to flatten the upper surface of the wiring. Its operation is basically the same as that described above.

Next, the invention according to claim 14 will be described. The present invention is a method of manufacturing a buried wiring structure by embedding a wiring material in an insulating layer, wherein a step of forming wiring on a substrate and a surface of the substrate including the wiring are covered with the insulating material. A step of annealing the substrate covered with the insulating material, and a step of polishing the annealed substrate at a low temperature to remove the insulating material on the wiring, the method comprising the steps of: is there. This invention is basically the same as the thirteenth invention, except that an annealing step is performed before polishing. The effect of this annealing is as described above.

Next, the invention according to claim 15 will be described. The present invention is a method of manufacturing a buried wiring structure by embedding a wiring material in an insulating layer, wherein a step of forming wiring on a substrate and a surface of the substrate including the wiring are covered with the insulating material. A method of manufacturing a buried wiring structure, comprising the steps of: polishing a substrate covered with the insulating material at a high temperature to remove the insulating material on the wiring; In the present invention, the temperature at the time of polishing according to the invention of claim 13 is changed from a low temperature to a high temperature.

Next, according to a sixteenth aspect of the present invention, there is provided a method of manufacturing a buried wiring structure by embedding a wiring material in an insulating layer, comprising the steps of forming a wiring on a substrate; Coating the surface of the substrate including the wiring with the insulating material, annealing the substrate coated with the insulating material, polishing the annealed substrate at a high temperature to remove the insulating material on the wiring And a step of manufacturing the embedded wiring structure. It is characterized in that the wiring is formed in a convex shape on the substrate in advance, that it is polished at high temperature, and that annealing is performed before it is polished at high temperature. Next, there is provided an invention according to claim 17, which is a CMP polishing apparatus having a structure in which a wafer holder is arranged to elastically press a polishing pad surface, wherein the wafer holder is a wafer to be polished. And a retainer ring surrounding the outer periphery of the wafer. Each of the wafer chuck and the retainer ring has a structure in which a polishing pad surface is independently elastically pressed. It is a polishing device. The present invention has been made in view of the fact that it is important to reduce the droop at the outer peripheral portion of the wafer in order to polish the polishing surface flat. The drooping of the outer peripheral portion gradually progresses toward the central portion of the polished surface as the polishing time elapses, and complicated factors due to unevenness of the polished surface due to the progress of the dripping overlap and hinder flat polishing of the wafer.

The invention described in this claim is focused on preventing the occurrence of drooping at the outer peripheral portion of the wafer, which is the first cause of the non-uniformity. As a result of investigations by the inventors, it has been found that the occurrence of this droop is caused by a polishing pad used for CMP polishing sliding to lick the outer peripheral portion of the wafer. This is because, as shown in FIG. 9, since the polishing pad 42 is formed of an elastic material instead of a rigid material, the portion pressed by the wafer 41 sinks, and the other portion is left as it is. This is due to the fact that the polishing pad is just wavy at the outer peripheral portion of the wafer at the boundary between the two. If this polishing pad is made of a highly rigid material, this problem can be solved.
In P polishing, it is essential to use a polishing pad having a certain softness, so that a high-rigidity material cannot be selected.

The inventor of the present invention believes that eliminating the sliding of the polishing pad at least at the outer peripheral portion of the wafer will prevent the occurrence of drooping and, consequently, the uniformity of the polished surface. We have provided the solution described in this claim. This is shown in FIG.
And the retainer rings 43, 43 are pressurized at a pressure W1,
The wafer chuck 44 is pressurized at the pressure W2, and each pressure can be controlled independently. Next, according to an eighteenth aspect of the present invention, there is provided the CMP polishing apparatus according to the seventeenth aspect, wherein the pressing force of the wafer chuck portion can be made larger than the pressing force of the retainer ring portion. Device. As shown in FIG. 11 and FIG.
Since the pressing force of 43 is made larger than the pressing force of the wafer chuck portion 41, the polishing pad in the retainer ring portion can be sunk into the polishing pad more deeply than the polishing surface of the wafer. In FIG. 12, the gap 46 between the retainer ring and the outer periphery of the wafer is larger than the gap 45 in FIG. This gap is optimized by the trade-off between the outer peripheral portion and the remaining polishing.

Next, the invention according to claim 19 is a CMP polishing apparatus having a structure in which a wafer holder is arranged so as to elastically press a polishing pad surface,
The wafer holder includes a wafer chuck portion that holds a back surface of a wafer to be polished, and a retainer ring that surrounds an outer peripheral portion of the wafer. When the wafer is polished, the wafer holder contacts the polishing pad of the retainer ring more than the polishing target surface of the wafer. CM that allows the surface to sink deeply into the polishing pad
It is a P polishing apparatus.

Next, according to a twentieth aspect of the present invention,
A method of manufacturing a wafer using an MP polishing method, wherein a polishing target surface of a wafer is pressed against a polishing pad, and a part of the polishing pad on the outer periphery of the wafer is sunk deeper into the polishing pad than the polishing target surface to perform CMP polishing. This is a method of manufacturing a wafer. The present invention is a polishing method that does not cause drooping on the outer peripheral portion of the wafer. Since the drooping of the outer peripheral portion is caused by the polishing pad sliding to lick the outer peripheral portion of the wafer, at least a part of the polishing pad on the outer peripheral portion is This sliding was prevented by sinking deeper into the polishing pad than the polished surface of the wafer. As means for achieving this, there is the invention described in claims 17 to 19 described above. Next, a twenty-first aspect of the present invention clarifies the most optimal wafer shape for the above-described invention. When the shape of the wafer is circular, any part of the outer periphery of the wafer is in uniform contact with the polishing pad, so that the sink amount of the polishing pad in the outer periphery can be made the same over the entire outer periphery. , Which makes it easy to design. Conversely, when the outer shape of the wafer is a square or the like, the outer peripheral corners have a higher contact pressure between the polishing pad and the wafer than the other portions, and therefore those portions are more likely than the other outer peripheral portions. It is necessary to set a larger sinking amount.

Furthermore, in the invention according to claim 22, since the respective pressures of the wafer chuck and the retainer ring can be measured, information for optimizing the pressure can be easily collected and the actual polishing can be performed. Sometimes, the pressing force can be observed on the spot, so that a highly accurate polishing can be performed.

As described above, according to the present invention, the dent of the wiring can be reduced to 50 angstroms or less in the step of manufacturing the buried wiring, so that it is easy to further form the wiring and the like thereon. In addition, the wiring structure can be easily multilayered. In a method of manufacturing a wafer using a CMP polishing method, a polishing target surface of the wafer is pressed against a polishing pad, and a part of the polishing pad on the outer periphery of the wafer is sunk deeper into the polishing pad than the polishing target surface.
Since the polishing is performed, there is an effect that it is possible to eliminate the drooping of the outer peripheral portion of the wafer, and it is possible to polish the wafer with high flatness.

Also, a wiring structure having a relatively large dent with good reproducibility can be produced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first step of the manufacturing steps according to the first embodiment.

FIG. 2 is a sectional view showing a second step of the manufacturing steps according to the first embodiment.

FIG. 3 is a sectional view showing a third step of the manufacturing steps according to the first embodiment.

FIG. 4 is a sectional view showing a fourth step of the manufacturing steps according to the first embodiment;

FIG. 5 is a sectional view showing a fifth step in the manufacturing steps according to the first embodiment.

FIG. 6 is a cross-sectional view showing a structure for lowering the substrate holding surface of the apparatus for polishing a substrate at a low temperature in the manufacturing process of the invention according to claim 1.

FIG. 7 is a cross-sectional view showing how grooves are dented when the embedded wiring structure is polished using free abrasive grains.

FIG. 8 is a conceptual diagram showing a part of the manufacturing process according to the invention described in claim 11;

FIG. 9 is an essential part cross-sectional conceptual diagram showing a state where a polishing pad slides around the outer periphery of a wafer so as to lick it.

FIG. 10 is a conceptual cross-sectional view of a main part showing a state in which a wafer chuck portion and a retainer ring can be individually pressed.

FIG. 11 is a conceptual cross-sectional view of a main part showing a state where a polishing pad on an outer peripheral portion of a wafer is deeply sunk by retainer ring.

FIG. 12 is an essential part cross-sectional conceptual diagram showing a state in which a polishing pad on an outer peripheral portion of a wafer is deeply sunk by retainer ring.

[Explanation of symbols]

 Reference Signs List 1 groove 2 silicon oxide layer 3 silicon 4 wiring material 5 dent 6 wiring 41 wafer 42 polishing pad 43 retainer ring 44 wafer chuck part 45 gap 46 gap

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/306 H01L 21/306 M

Claims (22)

[Claims] 1. A method of manufacturing a buried wiring structure by burying a wiring material having a thermal expansion coefficient different from a thermal expansion coefficient of a substrate in a groove formed in the substrate, wherein the groove is formed in the substrate. Process and the surface of the substrate including this groove,
A step of coating with the wiring material; and a step of polishing the substrate coated with the wiring material at a low temperature to remove the other wiring material while leaving the wiring material in the groove. Manufacturing method. 2. The method according to claim 1, wherein the substrate is a semiconductor substrate, and the step of forming the groove is a step of forming a groove in an insulating layer of the semiconductor substrate. 3. The method according to claim 1, wherein the wiring material is one of aluminum, copper, tungsten, and gold, or a combination thereof. 4. The buried wiring according to claim 1, wherein the step of polishing the substrate at a low temperature and removing the other wiring material while leaving the wiring material in the groove is performed at room temperature or lower. The method of manufacturing the structure. 5. The step of polishing the substrate at a low temperature to remove the other wiring material while leaving the wiring material in the groove by cooling the substrate holding surface of the polishing apparatus with water.
5. The method for manufacturing a buried wiring structure according to any one of the above. 6. The method according to claim 1, wherein the step of polishing the substrate at a low temperature and removing the other wiring material while leaving the wiring material in the groove is performed by using a cooled abrasive. 5. The method for manufacturing an embedded wiring structure according to item 1. 7. The method according to claim 1, wherein the step of polishing the substrate at a low temperature and removing the other wiring material while leaving the wiring material in the groove is performed by cooling a surface plate of a polishing apparatus. 13. The method for manufacturing an embedded wiring structure according to claim 1. 8. The method according to claim 1, wherein the step of polishing the substrate at a low temperature and removing the other wiring material while leaving the wiring material in the groove is performed by chemical mechanical polishing (CMP). A method for manufacturing a buried wiring structure according to claim 1. 9. The method according to claim 1, wherein the step of polishing the substrate at a low temperature and removing the other wiring material while leaving the wiring material in the groove is performed at a temperature of 0 ° C. or less. A method for manufacturing an embedded wiring structure. 10. A method of manufacturing a buried wiring structure by burying a wiring material having a thermal expansion coefficient different from that of the substrate into a groove formed in the substrate,
Forming a groove in the substrate, coating the surface of the substrate including the groove with the wiring material, annealing the substrate coated with the wiring material, and annealing the annealed substrate at a low temperature. Polishing to remove the wiring material while leaving the wiring material in the groove, and a method of manufacturing an embedded wiring structure. 11. The step of polishing the substrate at a low temperature and removing other wiring material while leaving the wiring material in the groove is performed while fixing abrasive grains on a surface plate and dropping lubricating oil. Item 1
Or the method of manufacturing an embedded wiring structure according to item 10. 12. A method of manufacturing a buried wiring structure by burying a wiring material having a thermal expansion coefficient different from a thermal expansion coefficient of the substrate into a groove formed in the substrate,
Forming a groove in the substrate, covering the surface of the substrate including the groove with the wiring material, polishing the annealed substrate at a high temperature, and leaving the wiring material in the groove to form another wiring. A method of manufacturing a buried wiring structure including a step of removing a material. 13. A method of manufacturing a buried wiring structure by embedding a wiring material in an insulating layer, comprising: forming a wiring on a substrate; and covering a surface of the substrate including the wiring with the insulating material. And removing the insulating material on the wiring by polishing the substrate coated with the insulating material at a low temperature, and removing the insulating material on the wiring. 14. A method of manufacturing a buried wiring structure by embedding a wiring material in an insulating layer, comprising: forming a wiring on a substrate; and covering a surface of the substrate including the wiring with the insulating material. And a step of annealing the substrate coated with the insulating material, and a step of polishing the annealed substrate at a low temperature to remove the insulating material on the wiring,
A method for manufacturing a buried wiring structure including: 15. A method for manufacturing a buried wiring structure by embedding a wiring material in an insulating layer, comprising: forming a wiring on a substrate; and covering a surface of the substrate including the wiring with the insulating material. And removing the insulating material on the wiring by polishing the substrate coated with the insulating material at a high temperature, and removing the insulating material from the wiring. 16. A method for manufacturing a buried wiring structure by embedding a wiring material in an insulating layer, comprising: forming a wiring on a substrate; and covering a surface of the substrate including the wiring with the insulating material. And a step of annealing the substrate coated with the insulating material, and a step of polishing the annealed substrate at a high temperature to remove the insulating material on the wiring,
A method for manufacturing a buried wiring structure including: 17. A CMP polishing apparatus having a structure in which a wafer holder is arranged to elastically press a polishing pad surface, wherein the wafer holder holds a back surface of a wafer to be polished, A CMP polishing apparatus, comprising: a retainer ring surrounding an outer peripheral portion of a wafer, wherein the wafer chuck portion and the retainer ring each independently presses a polishing pad surface elastically. 18. The CMP polishing apparatus according to claim 17, wherein the pressure applied to the wafer chuck is greater than the pressure applied to the retainer ring. 19. A CMP polishing apparatus having a structure in which a wafer holder is arranged to elastically press a polishing pad surface, wherein the wafer holder holds a back surface of a wafer to be polished, A CMP polishing apparatus, comprising: a retainer ring surrounding an outer peripheral portion of a wafer, wherein a contact surface of the retainer ring with the polishing pad can sink deeper into the polishing pad than a surface to be polished of the wafer during wafer polishing. 20. A method of manufacturing a wafer using a CMP polishing method, wherein a polishing target surface of a wafer is pressed against a polishing pad, and a part of the polishing pad on the outer periphery of the wafer is sunk into the polishing pad deeper than the polishing target surface. And then perform CMP polishing.
Wafer manufacturing method. 21. The method according to claim 20, wherein the outer shape of the wafer is circular. 22. The CM according to claim 17, wherein the pressure can be measured separately from the wafer chuck portion and the retainer ring.
P polishing equipment.