JP2002063787A - Semiconductor integrated device, and its refreshing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the DRAM access processing efficiency appropriate and to reduce the power consumption corresponding to the frequency of DRAM access. SOLUTION: An LSI 1 in which at least a built-in DRAM 2 and a logic circuit are mixed, is provided with a register 11 changing and setting the number of word lines to be selected at the time of refreshing for the built-in DRAM 2, and a built-in DRAM control circuit 10 performing refreshing operation for the built-in DRAM 2 for each number of word lines to be selected set by the register 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated device capable of efficiently refreshing a DRAM in an LSI in which a dynamic random access memory (DRAM) and a logic circuit are mixed, and a refresh method thereof. is there.

[0002]

2. Description of the Related Art With the recent miniaturization of semiconductor integrated circuits, many semiconductor integrated devices have a DRAM and a logic circuit mixedly mounted on one chip. FIG. 5 shows a DRAM
FIG. 2 is a block diagram showing an outline internal configuration of a conventional LSI in which a conventional LSI and a logic circuit are mixed. In FIG. 5, the LSI 10
0 has a built-in DRAM 102. Built-in DRAM 10
2 is controlled in access by a built-in DRAM control circuit 101. The built-in DRAM control circuit 101 receives a DRAM access request from the outside or from an internal circuit such as the CPU 121, generates a control signal for the built-in DRAM 102, and outputs the control signal to the built-in DRAM 102.

A built-in DRAM 102 has a RAS (Row Address Store) output from a built-in DRAM control circuit 101.
be), CAS (Column Adress Strobe), WE (Write
In response to a control signal such as Enable, a row signal and a column address signal, processing such as read, write, and refresh for the DRAM is performed. The read data is output from the cache memory 122 or the external bus I / F unit 123 or the like. The LSI 100 includes a debug module 124, a general-purpose input / output port 125, and a PLL clock generation circuit 12.
6 is also built in.

First, normal random access to the built-in DRAM 102 (normal read, normal write)
Will be described. FIG. 6 shows the built-in D shown in FIG.
FIG. 4 is an explanatory diagram illustrating a random access operation to a RAM 102. The built-in DRAM 102 includes the peripheral control circuit 1
04, row decoder 105, memory cell array 106,
It has a sense amplifier 107, a column decoder 108, and a word line boosted potential generation circuit 109. The built-in DRAM 102 includes a preamplifier, a write driver, an output buffer, and the like (not shown).

When a random access request signal and an address are input from an external or internal circuit, a built-in DRAM control circuit 101 outputs a row-related control signal such as RAS and a row address to a peripheral control circuit 104 of the built-in DRAM 102. . The peripheral control circuit 104 outputs the row address of the memory cell to be selected to the row decoder 105. The row decoder 105 selects the word line 111 corresponding to the input row address, turns on the gate of the memory cell 112 connected to the selected word line 111, and is connected to the bit line. As a result, data is exchanged.

In this case, the number of selected word lines 111 is fixed to one or a plurality of numbers determined in advance according to the specification of the built-in DRAM 102. For example, if the setting is such that n word lines are selected by one access, n word lines are selected in one access, whether reading or writing. Here, when a plurality of word lines are set so as not to be selected by one access, a plurality of memory cells 112 are not connected to the same sense amplifier 107.

On the other hand, in the built-in DRAM 102, since the charge stored in the memory capacitor is gradually lost due to various leaks, a refresh operation for once reading and writing data before the stored data is lost. I do. 7, the built-in DRAM control circuit 101 includes:
In order to refresh all the memory cells 112 within a preset refresh time, the CBR (CAS-
A refresh control signal such as Before-RAS) is output to the peripheral control circuit 104. The peripheral control circuit 104 receives the refresh control signal, generates a row address, and outputs the row address to the row decoder 105. The row decoder 105
The word line 111 is selected based on the row address.
All of the memory cells 112 connected to the selected word line 111 are refreshed. Here, the row address at the time of refresh is determined by the refresh address counter 103 built in the peripheral control circuit 104. Refresh address counter 103
Is incremented by one each time the refresh control signal is input once. Refresh address counter 1
When the number 03 turns once, all the word lines 111 are selected once, and all the memory cells are refreshed.

In the case of a general-purpose DRAM, the number of selected word lines at the time of refresh is the same as the number of selected word lines at the time of random access. Further, even in the LSI 100 having the built-in DRAM control circuit 101, the number of word lines selected at the time of refresh was the same as the number of word lines selected at the time of random access. Therefore, when the number of word lines selected at the time of random access is n, the number of word lines selected at the time of refresh is also n.

In the DRAM, since all memory cells must be refreshed within a refresh time, it is necessary to interrupt the normal access to perform the refresh. During this refresh operation, normal access cannot be performed. Therefore, if the frequency of refresh is high, the normal access time is shortened, and there is a problem that the processing efficiency is reduced.

In order to solve this problem, for example, in a dynamic RAM described in Japanese Patent Application Laid-Open No. Sho 62-241198, at the time of random access, one word line in one memory array mat corresponding to an address is selected. However, at the time of refresh, the word lines are selected one by one in the four memory array mats,
The refresh operation time is reduced.

[0011]

However, in the above-mentioned dynamic RAM, the number of word lines selected at the time of refresh is fixed at four, and even if the frequency of accessing the DRAM is not so high, it is always constant. At the time of refreshing, four word lines are selected, and simultaneously activating or selecting many word lines improves the time efficiency of refreshing, but the capacity of the word line selected at refreshing is improved. Therefore, there is a problem that power consumption increases.

[0012] The present invention has been made in view of the above,
It is an object of the present invention to provide a semiconductor integrated device and a refresh method for the same that can achieve DRAM access processing efficiency and reduce power consumption in response to DRAM access frequency.

[0013]

In order to achieve the above object, a semiconductor integrated device according to the present invention is provided in a semiconductor integrated device in which at least a dynamic random access memory and a logic circuit are mixedly mounted. Setting means for changing and setting the number of selected word lines, and control means for performing a refresh operation on the dynamic random access memory for each word line selection number set by the setting means.

According to the present invention, when the setting means changes and sets the number of word lines to be selected at the time of refreshing the dynamic random access memory using, for example, software of an external or internal circuit, the control means causes the setting means to The refresh operation for the dynamic random access memory is performed every set number of selected word lines.

In the semiconductor integrated device according to the next invention, in the above-mentioned invention, the setting means is 2 m (natural number).
The control means divides the dynamic random access memory into 2 m power values using an upper address of the dynamic random access memory;
It is characterized in that a refresh operation of the number of selected word lines at the time of random access is performed for each block of the 2 m value of the divided blocks.

According to the present invention, the setting means sets the number of word lines to be selected at the time of refreshing by a value of 2 to the power of m (natural number), and the control means uses an upper address of the dynamic random access memory. And divides the dynamic random access memory into 2 m power values, and performs a refresh operation of the selected number of word lines at random access for each of the 2 m power blocks among the divided blocks. I have to.

The semiconductor integrated device according to the next invention is characterized in that, in the above-described invention, the semiconductor integrated device further comprises a boosting means for changing the charging capacity to the number of word lines selected by the setting means.

According to the present invention, the boosting means changes the charging capacity to the number of word lines selected by the setting means.

In the semiconductor integrated device according to the next invention, in the above-mentioned invention, the boosting means includes a plurality of word line boosting means having a plurality of charging capacities and the plurality of word line boosting means, and Changing means for changing to a charging capacity corresponding to the selected number of word lines set by the means.

According to the present invention, the changing means combines the plurality of word line boosting means to change the charging capacity to the number of word lines selected by the setting means.

A refresh method for a semiconductor integrated device according to the next invention is a refresh method for a semiconductor integrated device in which at least a dynamic random access memory and a logic circuit are mixed, wherein the number of word lines selected for refreshing the dynamic random access memory is reduced. The method includes a setting step of changing and setting, and a refresh step of performing a refresh operation on the dynamic random access memory for each word line selection number set in the setting step.

According to the present invention, the setting step changes and sets the number of selected word lines in the dynamic random access memory at the time of refreshing, and the refresh step sets the dynamic random access number for each of the word line selection numbers set in the setting step. The refresh operation for the access memory is performed.

In the refreshing method for a semiconductor integrated device according to the next invention, in the above-mentioned invention, the setting step changes and sets the number of word line selections at the time of refreshing using a power of 2 (natural number). The refreshing step divides the dynamic random access memory into 2 m -values using an upper address of the dynamic random access memory, and for each of the divided blocks, It is characterized in that a refresh operation is performed for a selected number of word lines at the time of random access.

According to the present invention, the setting step changes and sets the number of word line selections at the time of refreshing by using a 2 (m) (natural number) power value. The dynamic random access memory is divided into 2 m values using the address, and the 2
The refresh operation of the selected number of word lines at the time of random access is performed for each block of the m-th power.

A refresh method for a semiconductor integrated device according to the next invention is characterized in that, in the above-mentioned invention, the method further comprises a boosting step of changing to a charging capacity corresponding to the selected number of word lines set in the setting step. .

According to this invention, the charge capacity is changed to the charge capacity corresponding to the selected number of word lines set in the setting step in the boosting step.

In a refreshing method for a semiconductor integrated device according to the next invention, in the above-mentioned invention, the boosting step combines a plurality of word line boosting means, and charges corresponding to the number of selected word lines set in the setting step. It is characterized in that the capacity is changed.

According to the invention, in the boosting step, a plurality of word line boosting means are combined to change the charging capacity to the number of selected word lines set in the setting step.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor integrated device and a refresh method thereof according to the present invention will be described below in detail with reference to the accompanying drawings.

Embodiment 1 FIG. 1 is a block diagram showing a configuration of an LSI according to the first embodiment of the present invention. The LSI 1 shown in FIG.
2 has a built-in DRAM control circuit 10 for controlling the internal DRAM 2 and a register 11, and shows only a configuration related to a refresh operation for the built-in DRAM. The LSI 1 has other configurations, for example, the CPU 121, the cache memory 122, the external bus I / F unit 123, the debug module 124, the general-purpose input / output port 125, and the PLL clock generation circuit 126 shown in FIG. Built-in DRA
M2 includes a peripheral control circuit 4 having a refresh address counter 3, a row decoder 5, a memory cell array 6, a sense amplifier 7, a column decoder 8, and a word line boosted potential generation circuit 9.

In the register 11, the number of selected word lines at the time of refresh is set by an external or internal circuit. In this LSI 1, at random access, one access (of one row address) causes n
It is assumed that one word line is selected. It is assumed that the register 11 is set to select a word line that is m times the word line selected at the time of random access.

The refresh operation is started when the built-in DRAM control circuit 10 outputs a refresh control signal such as CBR to the peripheral control circuit 4. On the other hand, at this time, the built-in DRAM control circuit 10 supplies the row decoder 5 with the word line m-times selection enable signal EN indicating that the word line is to be selected m times during the refresh operation in accordance with the value set in the register 11. Output to

Upon receiving the word line m-times select enable signal EN, the row decoder 5 activates all the sub-blocks of the memory cells 12 corresponding to the upper m bits of the row address. That is, at the time of normal random access and refresh, only one sub-block is activated.
M, the m sub-blocks become active. When the row address generated by the refresh address counter 3 in the peripheral control circuit 4 is output to the row decoder 5, the row decoder 5 reads the word corresponding to the address of the lower bits excluding the upper several bits corresponding to "m". Lines are selected in m sub-blocks. For example, when “m” is “2”, the word line corresponding to the address of the lower bit excluding the upper 1 bit is
Selected in two sub-blocks, "m" is "4"
In the case of, the word line corresponding to the address of the lower bit excluding the upper two bits is selected in the four sub-blocks. Therefore, in one refresh operation, n
× m word lines will be refreshed.

FIG. 2 is a circuit diagram showing a configuration of the row decoder 5 relating to refresh. FIG. 2 shows a configuration of the row decoder 5 when “m” set in the register 11 is 2, 4. In FIG.
The memory cell array 6 stores the upper two bits RA of the row address.
D <x>, RAD <x-1>, four sub-blocks 6A
~ 6D. At the time of random access, one of the four sub-blocks 6A to 6D
It is assumed that n word lines in one sub-block are selected. The word line m-times select enable signal EN is expressed as m =
It consists of enable signals REF2_EN and REF4_EN corresponding to 2 and 4. The enable signals REF2_EN and REF4_EN are both “L” during random access.

The bit RAD <x> is input to one end of the OR circuit 21 and is also input to one end of the OR circuit 22 via the inverter 25. The bit RAD <x−1> is input to one end of the OR circuit 23 and
6 to one end of an OR circuit 24. On the other hand, an enable signal output from the built-in DRAM control circuit 10
REF2_EN is input to the other ends of the OR circuits 21 and 22, respectively. The enable signal REF4_EN is output to the OR circuit 2
The signals are input to the other ends of 3 and 24, respectively. The output of the OR circuit 21 is input to one ends of AND circuits 31 and 32, and the output of the OR circuit 22 is input to one ends of AND circuits 33 and 34. The output of the OR circuit 23 is
The outputs of the OR circuit 24 are input to the other ends of the AND circuits 32 and 34. AND circuit 3
Outputs of 1 to 34 are connected to sub-blocks 6A to 6D, respectively.

If the register 11 is set to select twice as many word lines at the time of refreshing,
The built-in DRAM control circuit 10 sets the enable signal REF2_EN for selecting word line doubling to “H” and outputs it. As a result, the two sub-blocks 6A and 6C or the sub-blocks 6B and 6D determined by only the bit RAD <x-1> become active, regardless of the bit RAD <x>. In this case, since n word lines are selected in each of the sub-blocks 6A to 6D, 2n word lines are selected as a whole by activating two sub-blocks.

On the other hand, if the register 11 is set to select a quadruple word line at the time of refreshing, the built-in DRAM control circuit 10 also sets the enable signal REF4_EN for selecting the quadruple word line to "H", Enable signal
Both REF2_EN and REF4_EN are output as “H”.
As a result, the four sub-blocks 6A to 6D are activated irrespective of the bit RAD <x> and the bit RAD <x-1>, and 4n word lines are selected. After the refresh operation, both the enable signals REF2_EN and REF4_EN return to “L”. As a result, the number of word lines to be selected at the time of refreshing is reduced to n, which is the same as that at the time of random access, and 2 times that at the time of double word line selection.
The number can be changed to three, that is, n and 4n when the word line is quadrupled.

According to the first embodiment, the number of word lines selected at the time of refresh can be changed at any time by setting the number of word lines selected at the time of refreshing in the register 11 from an external or internal circuit. As a result, when DRAM access is frequently performed, the set value of the number of word lines selected at the time of refresh is increased, and
When the number of RAM accesses is small, the power consumption at the time of refresh can be suppressed by software of an external or internal circuit by reducing the set value of the number of word lines selected at the time of refresh.

Embodiment 2 Next, a second embodiment of the present invention will be described. In the first embodiment described above,
By setting the number of word lines to be selected in the register 11, the number of selected word lines at the time of refresh is flexibly changed. In the second embodiment, the number of selected word lines at the time of refresh can be changed. Thus, the charge capacity of the word line boosted potential generation circuit 9 is increased or decreased. This is because, when the number of selected word lines is increased, there is a possibility that the capability of the word line boosted potential generating circuit 9 is insufficient, and a case where a desired voltage cannot be applied to the word line occurs. Because.

FIG. 3 shows a second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an SI. In FIG. 3, the built-in DRAM control circuit 10 also inputs the word line m-fold select enable signal EN to the word line boosted potential generation circuit 9. Further, the word line boosted potential generating circuit 9 is provided in FIG.
As shown in the figure, it has a plurality of boosting pumps 51 to 54,
The plurality of boosting pumps 51 to 54 are switched according to the word line m-times selection enable signal EN. Other configurations are the same as those of the first embodiment, and the same components are denoted by the same reference numerals.

In FIG. 4, the word line boosted potential generating circuit 9 comprises four boosting pumps 51 to 5 having the same capacitance C.
4 This capacity C is a capacity required at the time of random access. The boost operation enable signal PUMP_EN instructing the boost operation from the peripheral control circuit 4 is input to the word line boost potential generation circuit 9, and is input to one end of the boost pump 51 and one end of the AND circuits 41 and 42.

On the other hand, the enable signal REF2_EN input from the built-in DRAM control circuit 10 is input to the other end of the AND circuit 41, and the enable signal REF4_EN is input to the other end of the AND circuit 42. The output of the AND circuit 41 is input to a boosting pump 52, and the output of the AND circuit 42 is input to boosting pumps 53 and 54. Note that, as described above, the enable signals REF2_EN and REF4_EN are both “L” at the time of random access.

Therefore, at the time of random access, only the boosting pump 51 to which the boosting operation enable signal PUMP_EN is directly input becomes active, and the boosting pump 51
The boost voltage is generated only by this. Also, register 1
1, when the setting to select twice the word line at the time of refresh is made, the enable signal REF2_EN is set to “H”.
As a result, in addition to the boosting pump 51, the boosting pump 52 also becomes active, and the boosting pump 5
A boosted voltage is generated from 1,52. On the other hand, register 11
In the case where the setting is made such that a word line four times as large is selected at the time of refreshing, the enable signal REF4_EN also becomes “H”, whereby all the boosting pumps 51 to 54 become active and all the boosting pumps 51 to 54 become active. To 54 generate a boosted voltage. After the refresh operation is completed,
The enable signals REF2_EN and REF4_EN are both “L”.
To return to. In this manner, the boosting operation of the boosting pumps 51 to 54 is increased or decreased in response to the increase in the number of selected word lines. Therefore, even if the number of selected word lines is increased, the capacity is insufficient during the refresh operation. Is gone.

In the second embodiment, the boosting capacity is increased or decreased in response to the increase or decrease in the number of word line selections during the refresh operation. Therefore, even when the number of word line selections is increased. There is no shortage of capacity.

[0045]

As described above, according to the present invention, when the setting means changes and sets the number of word lines selected for refreshing the dynamic random access memory using, for example, software of an external or internal circuit, Since the control means causes the refresh operation to be performed on the dynamic random access memory for each word line selection number set by the setting means, it is possible to easily and flexibly change the word line selection number at the time of refreshing. In addition to this, there is an effect that the power consumption during refresh can be suppressed by this change.

According to the next invention, the setting means sets the number of selected word lines at the time of refresh to 2 m (natural number).
The control means divides the dynamic random access memory into 2 m values using the upper address of the dynamic random access memory, and the 2 m power of each of the divided blocks. Since the refresh operation of the selected number of word lines at the time of random access is performed for each block of the value, the effect that the number of selected word lines at the time of refresh can be changed with a simple configuration is achieved.

According to the next invention, the boosting means changes the charging capacity corresponding to the number of selected word lines set by the setting means, so that the charging capacity increases with the number of selected word lines. This has the effect that shortage can be eliminated.

According to the next invention, the changing means combines a plurality of word line boosting means to change the charging capacity to the number of word line selections set by the setting means. With such a configuration, it is possible to eliminate the shortage of the charge capacity due to the increase in the number of selected word lines.

According to the next invention, by the setting step,
The number of word line selections at the time of refreshing the dynamic random access memory is changed and set, and the refresh operation is performed on the dynamic random access memory for each word line selection number set by the setting step. In addition, it is possible to easily and flexibly change the number of word lines to be selected at the time of refresh, and it is possible to suppress power consumption at the time of refresh by this change.

According to the next invention, the setting step includes the following steps:
The number of word line selections at the time of the refresh is changed and set using the m (natural number) power of
The dynamic random access memory is stored in 2 using the upper address of the dynamic random access memory.
, And the refresh operation of the number of selected word lines at the time of random access is performed for each of the blocks of the 2 m value among the divided blocks. There is an effect that the number of selected word lines can be easily changed.

According to the next invention, the pressure increasing step
Since the charging capacity is changed to the number of word lines selected in the setting step, the shortage of the charging capacity due to the increase in the number of selected word lines can be eliminated.

According to the next invention, in the boosting step, a plurality of word line boosting means are combined to change the charging capacity corresponding to the selected number of word lines set in the setting step. This brings about an effect that shortage of charging capacity due to an increase in the number of selections can be easily eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an LSI according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of the configuration of the row decoder shown in FIG.

FIG. 3 is a block diagram illustrating a configuration of an LSI according to a second embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration of a word line boosted potential generation circuit shown in FIG. 3;

FIG. 5 is a block diagram showing a configuration of a conventional LSI in which a built-in DRAM and a logic circuit are mixed.

FIG. 6 is an explanatory diagram illustrating an operation at the time of random access to a built-in DRAM of the LSI illustrated in FIG. 5;

FIG. 7 is an explanatory diagram illustrating an operation at the time of refreshing the built-in DRAM of the LSI illustrated in FIG. 5;

[Explanation of symbols]

1 LSI, 2 built-in DRAM, 3 refresh address counter, 4 peripheral control circuit, 5 row decoder,
6 memory cell array, 6A to 6D sub-block, 7
Sense amplifier, 8 column decoder, 9 boosted potential generation circuit for word line, 10 built-in DRAM control circuit, 11
Register, 21-24 OR circuit, 31-34, 4
1,42 AND circuit, 51-54 Boost pump.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masato Nakajima 2-6-1, Otemachi, Chiyoda-ku, Tokyo Within Mitsubishi Electric Engineering Co., Ltd. (72) Naoto Okumura 2-3-2, Marunouchi, Chiyoda-ku, Tokyo No. Mitsubishi Electric Corporation F-term (reference) 5B024 AA01 AA15 BA13 BA20 BA27 BA29 CA16 DA18

Claims (8)

[Claims] 1. A semiconductor integrated device in which at least a dynamic random access memory and a logic circuit are mounted, wherein setting means for changing and setting the number of word lines selected for refreshing the dynamic random access memory is set by the setting means. Control means for performing a refresh operation on the dynamic random access memory for each selected number of word lines. 2. The method according to claim 1, wherein the setting unit sets the dynamic random access memory to a 2 m power value using an upper address of the dynamic random access memory. 2. The semiconductor integrated device according to claim 1, wherein a refresh operation of a selected number of word lines at the time of random access is performed for each of the divided blocks having the m-th power of the divided blocks. . 3. The semiconductor integrated device according to claim 1, further comprising a booster for changing the charging capacity to the number of word lines selected by the setting unit. 4. The boosting means, comprising: a plurality of word line boosting means having a plurality of charging capacities; and a plurality of word line boosting means in combination, the charging corresponding to the number of selected word lines set by the setting means. 4. The semiconductor integrated device according to claim 3, further comprising: changing means for changing the capacity. 5. A refresh method for a semiconductor integrated device in which at least a dynamic random access memory and a logic circuit are mixed, wherein a setting step of changing and setting the number of word lines selected for refreshing the dynamic random access memory; A refresh step of performing a refresh operation on the dynamic random access memory for each set number of selected word lines. 6. The setting step changes and sets the number of selected word lines at the time of refreshing using a power of 2 (natural number), and the refreshing step uses an upper address of the dynamic random access memory. The dynamic random access memory is divided into 2 m -th power values, and each of the divided blocks having the 2 m -th power value is
6. The method according to claim 5, wherein a refresh operation is performed for a selected number of word lines during random access. 7. The method for refreshing a semiconductor integrated device according to claim 5, further comprising a boosting step of changing to a charging capacity corresponding to the selected number of word lines set in said setting step. 8. The semiconductor according to claim 7, wherein in the boosting step, a plurality of word line boosting means are combined to change the charging capacity to the number of selected word lines set in the setting step. A method for refreshing an integrated device.