JP2002057261A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same

Info

Publication number
JP2002057261A
JP2002057261A JP2000241114A JP2000241114A JP2002057261A JP 2002057261 A JP2002057261 A JP 2002057261A JP 2000241114 A JP2000241114 A JP 2000241114A JP 2000241114 A JP2000241114 A JP 2000241114A JP 2002057261 A JP2002057261 A JP 2002057261A
Authority
JP
Japan
Prior art keywords
solder
metal base
base plate
copper
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000241114A
Other languages
Japanese (ja)
Inventor
Hiroshi Nishibori
弘 西堀
Hironobu Nagata
広信 永田
Haruo Takao
治雄 高尾
Hideaki Chuma
秀明 中馬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2000241114A priority Critical patent/JP2002057261A/en
Publication of JP2002057261A publication Critical patent/JP2002057261A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has a reliable solder bonding with no solder cracks, without having to conduct surface treatment, such as Ni plating on the metal base plate. SOLUTION: In the semiconductor device, a metal base board 6 formed of copper or copper-based alloy, and an insulating substrate 5 having a rear face pattern 4 formed of copper or copper-shaped alloy on a face opposite to the metal base board 6 are bonded by soldering. The rear face pattern 4 is surface- treated, while a solder bonding face 11 of the metal base board 6 is not surface- treated. A ten-point surface roughness (Rz) of the solder bonding face 11 is 4 μm or smaller. The rear face pattern 4 and the solder bonding face 11 are bonded by solder 8 with flux mixed in.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、絶縁基板とヒー
トシンクである金属ベース板とを半田で接合した半導体
装置およびその製造方法に関するものである。
[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device in which an insulating substrate and a metal base plate as a heat sink are joined by solder, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】従来、金属ベース板と絶縁基板を半田接
合する際に、半田付け性を向上させ、半田接合強度を確
保する為に、Niめっき等の表面処理が金属ベース板に
施されていた。表1は、半田接合を行う金属ベース板と
絶縁基板の各表面処理の組合わせを示すものである。
2. Description of the Related Art Conventionally, when soldering a metal base plate and an insulating substrate, a surface treatment such as Ni plating is applied to the metal base plate in order to improve solderability and secure solder joint strength. Was. Table 1 shows combinations of the respective surface treatments of the metal base plate and the insulating substrate for performing the solder joining.

【0003】[0003]

【表1】 [Table 1]

【0004】表1に示されているように、従来は、表面
にNiめっき等が施された銅もしくは銅基合金を基材と
する金属ベース板と、同じく表面にNiめっき等が施さ
れた銅もしくは銅基合金を基材とする回路パターンおよ
び裏面パターンを有する絶縁基板との組合わせ、または
上記金属ベース板と、回路パターンおよび裏面パターン
の表面にNiめっき等が施されていない絶縁基板との組
合わせであった。上記2つの組み合わせにおける接合方
法は、フラックス入半田を用いて空気中で接合するか
(フラックス入半田+大気リフロー)、ノンフラックス
半田を用いて還元性ガス中、または還元性ガスと不活性
ガスの混合ガス中で接合するか(ノンフラックス半田+
雰囲気リフロー)のいずれかであった。
[0004] As shown in Table 1, conventionally, a metal base plate made of copper or a copper-based alloy as a base material with a Ni plating or the like on the surface, and a Ni plating or the like with the same surface. A combination of an insulating substrate having a circuit pattern and a back surface pattern based on copper or a copper-based alloy, or an insulating substrate on which the surface of the circuit pattern and the back surface pattern is not subjected to Ni plating or the like; Was a combination of The joining method in the above two combinations is to join in air using flux-filled solder (flux-filled solder + atmospheric reflow), or in reducing gas using non-flux solder, or in reducing gas and inert gas. Joining in mixed gas (Non-flux solder +
Atmosphere reflow).

【0005】また、関連する半田接合の技術について、
例えば特開平11−12714号公報は、ノンフラック
ス半田を用いる接合を開示している。表2は、特開平1
1−12714号公報における表面粗さと酸化皮膜の効
果概念を示すものである。
[0005] Further, regarding a related solder joining technique,
For example, Japanese Patent Application Laid-Open No. 11-12714 discloses joining using non-flux solder. Table 2 shows that of
1 shows the concept of the effect of the surface roughness and the oxide film in JP-A No. 1-2714.

【0006】[0006]

【表2】 [Table 2]

【0007】特開平11−12714号公報は、リード
フレーム材の表面粗さと酸化皮膜厚さとを制御すること
により、表2に示すように、ダイレクトワイヤボンディ
ング性と半田付け性の向上を図ることについて開示して
いる。しかしながら、ダイレクトワイヤボンディング性
が表面粗さに左右されることと、半田付け性が酸化皮膜
に左右されることを開示しているものの、表面粗さと半
田クラックとの関係について開示していない。
Japanese Patent Application Laid-Open No. H11-12714 discloses that the surface roughness of a lead frame material and the thickness of an oxide film are controlled to improve the direct wire bonding property and the solderability as shown in Table 2. Has been disclosed. However, although it discloses that the direct wire bonding property depends on the surface roughness and that the solderability depends on the oxide film, it does not disclose the relationship between the surface roughness and the solder crack.

【0008】[0008]

【発明が解決しようとする課題】従来の金属ベース板
は、Niめっき等の表面処理が施されており、めっき処
理にかかるコストのために部材コストが高いという問題
があった。本発明は、上記問題を解決するためになされ
たものであり、金属ベース板の表面処理を省略して上記
コスト上の問題を緩和させると共に、半田クラックを妨
げる信頼性の高い半田接合をした半導体装置および半導
体装置の製造方法を提供する。
The conventional metal base plate has been subjected to a surface treatment such as Ni plating, and has a problem that the cost of the member is high due to the cost of the plating process. The present invention has been made in order to solve the above-mentioned problems, and a surface treatment of a metal base plate is omitted to alleviate the above-mentioned cost problem, and a semiconductor having a highly reliable solder joint that prevents solder cracks. A device and a method for manufacturing a semiconductor device are provided.

【0009】[0009]

【課題を解決するための手段】上記問題を解決するため
に、本願の第1の発明に係る半導体装置は、銅もしくは
銅基合金で形成された金属ベース板と、前記金属ベース
板と対向する面に銅もしくは銅基合金で形成された裏面
パターンを有する絶縁基板とを半田で接合している半導
体装置において、前記裏面パターンには表面処理が施さ
れており、前記金属ベース板の半田接合面には表面処理
が施されておらず、前記半田接合面の十点表面粗さ(R
z)が4μm以下であり、前記裏面パターンと前記半田
接合面がフラックス入半田で接合していることを特徴と
するものである。
In order to solve the above problems, a semiconductor device according to a first aspect of the present invention includes a metal base plate formed of copper or a copper-based alloy, and a metal base plate facing the metal base plate. In a semiconductor device in which an insulating substrate having a back surface pattern formed of copper or a copper-based alloy on a surface is bonded by solder, the back surface pattern is subjected to a surface treatment, and a solder bonding surface of the metal base plate is provided. Has not been subjected to a surface treatment, and has a ten-point surface roughness (R
z) is 4 μm or less, and the back surface pattern and the solder joint surface are joined by flux-filled solder.

【0010】次に、本願の第2の発明に係る半導体装置
は、本願の第1の発明に係る半導体装置において、前記
裏面パターンにも表面処理が施されておらず、前記裏面
パターンは十点表面粗さ(Rz)が4μm以下であるこ
とを特徴とするものである。
Next, a semiconductor device according to a second invention of the present application is the semiconductor device according to the first invention of the present application, wherein the back surface pattern is not subjected to surface treatment, and the back surface pattern has ten points. The surface roughness (Rz) is 4 μm or less.

【0011】次に、本願の第3の発明に係る半導体装置
の製造方法は、銅もしくは銅基合金で形成された金属ベ
ース板と、前記金属ベース板と対向する面に銅もしくは
銅基合金で形成された裏面パターンを有する絶縁基板と
を半田で接合する半導体装置の製造方法において、前記
金属ベース板の半田接合面を十点表面粗さ(Rz)が4
μm以下になるように加工し、前記裏面パターンに表面
処理を施し、前記半田接合面に表面処理を施さず、ノン
フラックス半田を用いて、還元性ガス中、または還元性
ガスと不活性ガスの混合ガス中で、前記裏面パターンと
前記半田接合面を半田接合することを特徴とするもので
ある。
Next, a method for manufacturing a semiconductor device according to a third aspect of the present invention is a method for manufacturing a semiconductor device, comprising: a metal base plate formed of copper or a copper base alloy; and a copper or copper base alloy formed on a surface facing the metal base plate. In a method of manufacturing a semiconductor device in which an insulating substrate having a formed back surface pattern is joined by soldering, the solder joint surface of the metal base plate has a ten-point surface roughness (Rz) of 4
μm or less, subjected to a surface treatment on the back surface pattern, without surface treatment on the solder joint surface, using a non-flux solder, in a reducing gas, or in a reducing gas and an inert gas The method is characterized in that the back surface pattern and the solder joint surface are soldered in a mixed gas.

【0012】次に、本願の第4の発明に係る半導体装置
の製造方法は、本願の第3の発明に係る半導体装置の製
造方法において、前記裏面パターンに表面処理を施さな
いで、前記裏面パターンを十点表面粗さ(Rz)が4μ
m以下になるように加工することを特徴とするものであ
る。
Next, a method for manufacturing a semiconductor device according to a fourth invention of the present application is the method for manufacturing a semiconductor device according to the third invention of the present application, wherein the back surface pattern is not subjected to a surface treatment. With a ten-point surface roughness (Rz) of 4μ
m or less.

【0013】[0013]

【発明の実施の形態】実施の形態1.図面を用いて本発
明の実施の形態1を説明する。図1は、実施の形態1に
おける半導体装置の側面断面図である。図1において、
半導体装置は、半導体素子1と、絶縁基板5と、銅もし
くは銅基合金で形成された金属ベース板6と、アルミワ
イヤ10とで構成されている。絶縁基板5は、回路パタ
ーン3と、絶縁基材2と、裏面パターン4とで構成され
ている。回路パターン3および裏面パターン4は、銅も
しくは銅基合金で形成され、Niめっき等の表面処理が
施されている。Niめっき等の表面処理が施されていな
い金属ベース板6の半田接合面11と、裏面パターン4
は、フラックス入りの半田材8を用いて接合されてい
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a side sectional view of the semiconductor device according to the first embodiment. In FIG.
The semiconductor device includes a semiconductor element 1, an insulating substrate 5, a metal base plate 6 made of copper or a copper-based alloy, and an aluminum wire 10. The insulating substrate 5 includes the circuit pattern 3, the insulating base 2, and the back pattern 4. The circuit pattern 3 and the back surface pattern 4 are formed of copper or a copper-based alloy, and have been subjected to a surface treatment such as Ni plating. Solder joint surface 11 of metal base plate 6 not subjected to surface treatment such as Ni plating, and back surface pattern 4
Are joined using a solder material 8 containing a flux.

【0014】さらに、半導体素子1は、Niめっき等の
表面処理が施されている回路パターン3に半田材7で搭
載されている。アルミワイヤ10は、一端が半導体素子
1に、他端が回路パターン3に超音波法によりワイヤボ
ンディングが行われる。この結果、アルミワイヤ10
は、半導体素子1と回路パターン3を電気的に接続す
る。また、図1、2に示されているように、通常、金属
ベース板6の表面は、半田が濡れやすい半田接合面11
と、半田が濡れにくいレジスト塗布面9とで構成されて
いる。このレジスト塗布面9は、半田が濡れにくいため
に、半田接合面11から半田材8が流出することを防止
できる。
Further, the semiconductor element 1 is mounted on a circuit pattern 3 which has been subjected to a surface treatment such as Ni plating with a solder material 7. The aluminum wire 10 has one end bonded to the semiconductor element 1 and the other end bonded to the circuit pattern 3 by an ultrasonic method. As a result, the aluminum wire 10
Electrically connects the semiconductor element 1 and the circuit pattern 3. Also, as shown in FIGS. 1 and 2, the surface of the metal base plate 6 usually has a solder joint surface 11 where solder is easily wetted.
And a resist-coated surface 9 to which solder is hardly wetted. The resist coating surface 9 can prevent the solder material 8 from flowing out from the solder joint surface 11 because the solder is hard to wet.

【0015】以下、半導体装置の製造方法について説明
する。まず、半田接合面11の十点表面粗さ(Rz)が
4μm以下になるように金属ベース板6を圧延加工す
る。次に、Niめっき等の表面処理を裏面パターン4に
施す。
Hereinafter, a method for manufacturing a semiconductor device will be described. First, the metal base plate 6 is rolled so that the ten-point surface roughness (Rz) of the solder joint surface 11 becomes 4 μm or less. Next, a surface treatment such as Ni plating is performed on the back surface pattern 4.

【0016】次に、絶縁基板5の裏面パターン4を金属
ベース板6に固定するために、フラックス入クリーム半
田を絶縁基板5が搭載される場所に塗る。クリーム半田
塗布の後に、絶縁基板5を金属ベース板6に実装する。
Next, in order to fix the back surface pattern 4 of the insulating substrate 5 to the metal base plate 6, a flux-containing cream solder is applied to a place where the insulating substrate 5 is to be mounted. After applying the cream solder, the insulating substrate 5 is mounted on the metal base plate 6.

【0017】次に、塗布されたクリーム半田を例えば大
気リフロー炉を用いて空気中で溶融する。溶融した半田
が冷えると、絶縁基板5の裏面パターン4が金属ベース
板6にしっかりと半田付けされる。半田付けする際に、
半田付けする部分(実施の形態1では、半田接合面1
1)が酸化されると、半田付け性が低下することが一般
に知られている。空気中で半田付けすると、空気に含ま
れる酸素により半田付けする部分は酸化しやすい状態に
あるが、半田に含まれているフラックスが、金属ベース
板6の半田接合面11の酸化を防ぎ、さらに半田接合面
11の酸化膜を除去することができる。
Next, the applied cream solder is melted in the air using, for example, an atmospheric reflow furnace. When the molten solder cools, the back surface pattern 4 of the insulating substrate 5 is securely soldered to the metal base plate 6. When soldering,
The part to be soldered (in the first embodiment, the solder joint surface 1
It is generally known that when 1) is oxidized, the solderability deteriorates. When soldering in air, the portion to be soldered by oxygen contained in air is easily oxidized, but the flux contained in the solder prevents the solder joint surface 11 of the metal base plate 6 from being oxidized. The oxide film on the solder joint surface 11 can be removed.

【0018】なお、絶縁基板5と金属ベース板6とを半
田付けすると同時に、上記と同様の方法または従来の方
法で、半導体素子1を回路パターン3に半田付けする。
その後、アルミワイヤ10を回路パターン3と半導体素
子1に超音波法によりワイヤボンディングする。
At the same time that the insulating substrate 5 and the metal base plate 6 are soldered, the semiconductor element 1 is soldered to the circuit pattern 3 by the same method as described above or a conventional method.
Thereafter, the aluminum wire 10 is wire-bonded to the circuit pattern 3 and the semiconductor element 1 by an ultrasonic method.

【0019】以下、Niめっき等の処理が施されていな
い表面(金属ベース板6の半田接合面11と絶縁基板の
表面3、4)の十点表面粗さ(Rz)を4μm以下にす
る理由について説明する。図3は、表面にNiめっき等
が施されていない金属ベース板(または絶縁基板の表
面)の十点表面粗さ(Rz)に対するヒートサイクルに
おける基板下の半田クラックの進展度を示す実験データ
を表すグラフである。この図3は、十点表面粗さ(R
z)が4μmを超えると半田クラックの進展度が急速に
高まることを示している。
The reason why the ten-point surface roughness (Rz) of the surface not subjected to the treatment such as Ni plating (the solder joint surface 11 of the metal base plate 6 and the surfaces 3 and 4 of the insulating substrate) is set to 4 μm or less. Will be described. FIG. 3 shows experimental data showing the degree of development of solder cracks under a substrate in a heat cycle with respect to the ten-point surface roughness (Rz) of a metal base plate (or the surface of an insulating substrate) whose surface is not subjected to Ni plating or the like. FIG. FIG. 3 shows the ten-point surface roughness (R
When z) exceeds 4 μm, the degree of development of solder cracks is rapidly increased.

【0020】また、図4は、十点表面粗さ(Rz)が4
μmより大きい場合の半田接合部の拡大模式図であり、
図5は、逆に十点表面粗さ(Rz)が4μmより小さい
場合の半田接合部の拡大模式図である。十点表面粗さ
(Rz)が4μmより小さい場合は、金属間化合物層1
2が安定しているのに対して、十点表面粗さ(Rz)が
4μmより大きい場合は、金属間化合物層12が安定せ
ず、一部金属間化合物不形成層13を呈しており、さら
に半田フィレット先端14に生じる応力集中と合まって
半田クラックが早期に進展する可能性がある。以上のこ
とから、Niめっき等の処理が施されていない表面(金
属ベース板6の半田接合面11と絶縁基板の表面3、
4)の十点表面粗さ(Rz)は、4μm以下であること
が好ましい。
FIG. 4 shows that the ten-point surface roughness (Rz) is 4
FIG. 4 is an enlarged schematic view of a solder joint when the diameter is larger than μm;
FIG. 5 is an enlarged schematic view of the solder joint when the ten-point surface roughness (Rz) is smaller than 4 μm. When the ten-point surface roughness (Rz) is smaller than 4 μm, the intermetallic compound layer 1
When the ten-point surface roughness (Rz) is larger than 4 μm while the surface of No. 2 is stable, the intermetallic compound layer 12 is not stable, and a part of the intermetallic compound non-forming layer 13 is exhibited. Furthermore, there is a possibility that solder cracks may develop early due to the concentration of stress generated at the solder fillet tip 14. From the above, the surface not subjected to the treatment such as Ni plating (the solder joint surface 11 of the metal base plate 6 and the surface 3 of the insulating substrate,
The ten-point surface roughness (Rz) of 4) is preferably 4 μm or less.

【0021】なお、この実施の形態1では、半田材8
(および/または半田材7)としてクリーム半田を使用
したが、クリーム半田に限定されるわけではなく、裏面
パターン4と金属ベース板6を接合することができるも
のであれば、どんな半田でも使用可能である。さらに、
Niめっきは、半田付け性を向上させ、半田接合強度を
確保するために施されるものであり、同様の効果を得る
ものであれば、例えばAgめっきでもよい。これらのこ
とは、以下の実施の形態2から4においても同様であ
る。
In the first embodiment, the solder material 8
Although cream solder was used as (and / or solder material 7), it is not limited to cream solder, and any solder can be used as long as it can join back pattern 4 and metal base plate 6. It is. further,
Ni plating is applied to improve solderability and secure solder joint strength. For example, Ag plating may be used as long as a similar effect is obtained. The same applies to the following Embodiments 2 to 4.

【0022】上記のような構成の半導体装置において、
Niめっき等の表面処理が施されていない銅もしくは銅
基合金を基材とする金属ベース板6の十点表面粗さ(R
z)は、Rz≦4μmに圧延加工されていることから、
信頼性の高い半田接合を行うことができ、ヒートサイク
ルにおける基板下の半田クラックの進展度もNiめっき
等の表面処理が施されている金属ベース板と変わらな
い。
In the semiconductor device having the above configuration,
Ten-point surface roughness (R) of a metal base plate 6 based on copper or a copper-based alloy not subjected to surface treatment such as Ni plating
z) is rolled to Rz ≦ 4 μm,
A highly reliable solder joint can be performed, and the degree of development of a solder crack under the substrate in a heat cycle is not different from that of a metal base plate subjected to a surface treatment such as Ni plating.

【0023】実施の形態2.本発明の実施の形態2につ
いて説明する。ここでは、実施の形態1と同一であるこ
とについては重複を避けるために説明を省略する。ま
ず、実施の形態2における半導体装置について説明す
る。実施の形態2における半導体装置は、半田材8(図
1)がフラックス入半田ではなく、ノンフラックス半田
であることを除いて実施の形態1における半導体装置と
同一である。つまり、半導体素子1と、絶縁基板5と、
金属ベース板6と、半田材7と、アルミワイヤ10は、
実施の形態1における半導体装置のものと同一である。
Embodiment 2 FIG. Embodiment 2 of the present invention will be described. Here, the description of what is the same as the first embodiment is omitted to avoid duplication. First, a semiconductor device according to the second embodiment will be described. The semiconductor device according to the second embodiment is the same as the semiconductor device according to the first embodiment except that the solder material 8 (FIG. 1) is not flux-filled solder but non-flux solder. That is, the semiconductor element 1, the insulating substrate 5,
The metal base plate 6, the solder material 7, and the aluminum wire 10
This is the same as that of the semiconductor device in the first embodiment.

【0024】次に、実施の形態2における半導体装置の
製造方法について説明する。まず、半田接合面11の十
点表面粗さ(Rz)が4μm以下になるように金属ベー
ス板6を圧延加工する。次に、Niめっき等の表面処理
を裏面パターン4に施す。
Next, a method of manufacturing a semiconductor device according to the second embodiment will be described. First, the metal base plate 6 is rolled so that the ten-point surface roughness (Rz) of the solder joint surface 11 becomes 4 μm or less. Next, a surface treatment such as Ni plating is performed on the back surface pattern 4.

【0025】次に、絶縁基板5の裏面パターン4を金属
ベース板6に固定するために、ノンフラックスクリーム
半田を絶縁基板5が搭載される場所に塗る。クリーム半
田塗布の後に、絶縁基板5を金属ベース板6に実装す
る。
Next, in order to fix the back surface pattern 4 of the insulating substrate 5 to the metal base plate 6, a non-flux cream solder is applied to a place where the insulating substrate 5 is mounted. After applying the cream solder, the insulating substrate 5 is mounted on the metal base plate 6.

【0026】次に、塗布されたクリーム半田を例えばリ
フロー炉を用いて、還元性ガス(例えば水素)中、また
は還元性ガスと不活性ガスの混合ガス中で溶融する。溶
融した半田が冷えると、絶縁基板5の裏面パターン4が
金属ベース板6にしっかりと半田付けされる。半田付け
する際に、半田付けする部分(実施の形態2では、半田
接合面11)が酸化されると、半田付け性が低下するこ
とが一般に知られている。実施の形態2では、還元性ガ
ス中、または還元性ガスと不活性ガスの混合ガス中で半
田付けを行うため、金属ベース板6の半田接合面11の
酸化を防ぐことができる。さらに還元性ガスは半田接合
面11の酸化膜を除去することができる。
Next, the applied cream solder is melted in a reducing gas (for example, hydrogen) or a mixed gas of a reducing gas and an inert gas by using, for example, a reflow furnace. When the molten solder cools, the back surface pattern 4 of the insulating substrate 5 is securely soldered to the metal base plate 6. It is generally known that at the time of soldering, when a portion to be soldered (the solder joint surface 11 in the second embodiment) is oxidized, the solderability deteriorates. In the second embodiment, since soldering is performed in a reducing gas or a mixed gas of a reducing gas and an inert gas, oxidation of the solder joint surface 11 of the metal base plate 6 can be prevented. Further, the reducing gas can remove the oxide film on the solder joint surface 11.

【0027】なお、絶縁基板5と金属ベース板6とを半
田付けすると同時に、上記と同様の方法または従来の方
法で、半導体素子1を回路パターン3に半田付けする。
その後、アルミワイヤ10を回路パターン3と半導体素
子1に超音波法によりワイヤボンディングする。
At the same time that the insulating substrate 5 and the metal base plate 6 are soldered, the semiconductor element 1 is soldered to the circuit pattern 3 by the same method as described above or a conventional method.
Thereafter, the aluminum wire 10 is wire-bonded to the circuit pattern 3 and the semiconductor element 1 by an ultrasonic method.

【0028】上記のような構成の半導体装置において、
Niめっき等の表面処理が施されていない銅もしくは銅
基合金を基材とする金属ベース板6の十点表面粗さ(R
z)は、Rz≦4μmに圧延加工されていることから、
信頼性の高い半田接合を行うことができ、ヒートサイク
ルにおける基板下の半田クラックの進展度もNiめっき
等の表面処理が施されている金属ベース板と変わらな
い。
In the semiconductor device having the above configuration,
Ten-point surface roughness (R) of a metal base plate 6 based on copper or a copper-based alloy not subjected to surface treatment such as Ni plating
z) is rolled to Rz ≦ 4 μm,
A highly reliable solder joint can be performed, and the degree of development of a solder crack under the substrate in a heat cycle is not different from that of a metal base plate subjected to a surface treatment such as Ni plating.

【0029】実施の形態3.本発明の実施の形態3につ
いて説明する。ここでは、実施の形態1と同一であるこ
とについては重複を避けるために説明を省略する。ま
ず、実施の形態3における半導体装置について説明す
る。裏面パターン4(図1)にはNiめっき等の表面処
理が施されておらず、裏面パターン4の十点表面粗さ
(Rz)が4μm以下であることが、実施の形態3にお
ける半導体装置と実施の形態1における半導体装置との
違いである。
Embodiment 3 Embodiment 3 of the present invention will be described. Here, the description of what is the same as the first embodiment is omitted to avoid duplication. First, a semiconductor device according to the third embodiment will be described. The back surface pattern 4 (FIG. 1) is not subjected to a surface treatment such as Ni plating, and the ten-point surface roughness (Rz) of the back surface pattern 4 is 4 μm or less. This is a difference from the semiconductor device according to the first embodiment.

【0030】次に、実施の形態3における半導体装置の
製造方法について説明する。まず、裏面パターン4と半
田接合面11の十点表面粗さ(Rz)が4μm以下にな
るように、裏面パターン4と金属ベース板6を圧延加工
する。半導体装置の製造方法のその他の工程について
は、実施の形態1における半導体装置の製造方法と同一
である。
Next, a method of manufacturing the semiconductor device according to the third embodiment will be described. First, the back surface pattern 4 and the metal base plate 6 are rolled so that the ten-point surface roughness (Rz) of the back surface pattern 4 and the solder joint surface 11 is 4 μm or less. Other steps in the method for manufacturing a semiconductor device are the same as those in the method for manufacturing a semiconductor device in the first embodiment.

【0031】上記のような構成の半導体装置において、
Niめっき等の表面処理が施されていない銅もしくは銅
基合金を基材とする裏面パターン4および金属ベース板
6の十点表面粗さ(Rz)は、Rz≦4μmに圧延加工
されていることから、信頼性の高い半田接合を行うこと
ができ、ヒートサイクルにおける基板下の半田クラック
の進展度もNiめっき等の表面処理が施されている裏面
パターンおよびNiめっき等の表面処理が施されている
金属ベース板と変わらない。
In the semiconductor device having the above configuration,
The ten-point surface roughness (Rz) of the back surface pattern 4 and the metal base plate 6 based on copper or a copper-based alloy not subjected to surface treatment such as Ni plating is rolled to Rz ≦ 4 μm. Therefore, a highly reliable solder joint can be performed, and the degree of development of solder cracks under the substrate in a heat cycle is also subjected to a surface pattern such as Ni plating and a surface treatment such as Ni plating. It is no different from a metal base plate.

【0032】実施の形態4.本発明の実施の形態4につ
いて説明する。ここでは、実施の形態2と同一であるこ
とについては重複を避けるために説明を省略する。ま
ず、実施の形態4における半導体装置について説明す
る。実施の形態4における半導体装置は、裏面パターン
4(図1)にはNiめっき等の表面処理が施されておら
ず、裏面パターン4の十点表面粗さが4μm以下である
点で実施の形態2における半導体装置と異なる。
Embodiment 4 FIG. Embodiment 4 of the present invention will be described. Here, the description of what is the same as the second embodiment is omitted to avoid duplication. First, a semiconductor device according to the fourth embodiment will be described. The semiconductor device according to the fourth embodiment is different from the first embodiment in that surface treatment such as Ni plating is not performed on rear surface pattern 4 (FIG. 1) and ten-point surface roughness of rear surface pattern 4 is 4 μm or less. 2 is different from the semiconductor device of FIG.

【0033】次に、実施の形態4における半導体装置の
製造方法について説明する。まず、裏面パターン4と半
田接合面11の十点表面粗さ(Rz)が4μm以下にな
るように、裏面パターン4と金属ベース板6を圧延加工
する。半導体装置の製造方法のその他の工程について
は、実施の形態2における半導体装置の製造方法と同一
である。
Next, a method of manufacturing a semiconductor device according to the fourth embodiment will be described. First, the back surface pattern 4 and the metal base plate 6 are rolled so that the ten-point surface roughness (Rz) of the back surface pattern 4 and the solder joint surface 11 is 4 μm or less. Other steps in the method for manufacturing a semiconductor device are the same as those in the method for manufacturing a semiconductor device in the second embodiment.

【0034】上記のような構成の半導体装置において、
Niめっき等の表面処理が施されていない銅もしくは銅
基合金を基材とする裏面パターン4および金属ベース板
6の十点表面粗さ(Rz)は、Rz≦4μmに圧延加工
されていることから、信頼性の高い半田接合を行うこと
ができ、ヒートサイクルにおける基板下の半田クラック
の進展度もNiめっき等の表面処理が施されている裏面
パターンおよびNiめっき等の表面処理が施されている
金属ベース板と変わらない。
In the semiconductor device having the above configuration,
The ten-point surface roughness (Rz) of the back surface pattern 4 and the metal base plate 6 based on copper or a copper-based alloy not subjected to surface treatment such as Ni plating is rolled to Rz ≦ 4 μm. Therefore, a highly reliable solder joint can be performed, and the degree of development of solder cracks under the substrate in the heat cycle is also subjected to a surface treatment such as Ni plating and a back surface pattern subjected to surface treatment such as Ni plating. It is no different from a metal base plate.

【0035】なお、裏面パターン4と半田接合面11の
十点表面粗さ(Rz)を4μm以下にするために、金属
ベース板6および裏面パターン4を圧延加工する代わり
に研磨してもよい。
In order to reduce the ten-point surface roughness (Rz) of the back surface pattern 4 and the solder joint surface 11 to 4 μm or less, the metal base plate 6 and the back surface pattern 4 may be polished instead of rolling.

【0036】[0036]

【発明の効果】本願の第1の発明に係る半導体装置によ
れば、金属ベース板の半田接合面に表面処理を施さなく
ても信頼性の高い半田接合を行うことができるので、生
産性に優れ、安価な金属ベース板を用いることができる
という効果を奏する。
According to the semiconductor device according to the first aspect of the present invention, highly reliable solder bonding can be performed without performing surface treatment on the solder bonding surface of the metal base plate. The effect is that an excellent and inexpensive metal base plate can be used.

【0037】本願の第2の発明に係る半導体装置によれ
ば、金属ベース板の半田接合面に表面処理を施さないだ
けでなく裏面パターンに表面処理を施さなくても信頼性
の高い半田接合を行うことができるので、生産性に極め
て優れ、極めて安価な半導体装置を提供できるという効
果を奏する。
According to the semiconductor device of the second aspect of the present invention, not only the surface treatment is not performed on the solder joint surface of the metal base plate, but also the highly reliable solder joint can be performed without performing the surface treatment on the back surface pattern. Since it can be performed, there is an effect that an extremely inexpensive semiconductor device with excellent productivity can be provided.

【0038】本願の第3の発明に係る半導体装置の製造
方法によれば、還元性ガス中、または還元性ガスと不活
性ガスの混合ガス中でノンフラックス半田を用いて半田
接合するので、金属ベース板の半田接合面に表面処理を
施さなくても信頼性の高い半田接合を行うことができ、
生産性に優れ、安価な金属ベース板を用いることができ
るという効果を奏する。また、ノンフラックス半田を用
いることで半田接合後の洗浄が不要となり生産性が向上
し製造コストを低減できるという効果を奏する。
According to the method of manufacturing a semiconductor device according to the third aspect of the present invention, since the non-flux solder is used for soldering in a reducing gas or a mixed gas of a reducing gas and an inert gas, metal Highly reliable solder bonding can be performed without performing surface treatment on the solder bonding surface of the base plate.
This has the effect of being able to use an inexpensive metal base plate with excellent productivity. In addition, the use of non-flux solder eliminates the need for cleaning after solder joining, thereby improving productivity and reducing manufacturing costs.

【0039】本願の第4の発明に係る半導体装置の製造
方法によれば、金属ベース板の半田接合面にだけでなく
裏面パターンに表面処理を施さなくても信頼性の高い半
田接合を行うことができるので、生産性に極めて優れ、
極めて安価な半導体装置を提供できるという効果を奏す
る。また、ノンフラックス半田を用いることで半田接合
後の洗浄が不要となり生産性が向上し製造コストを低減
できるという効果を奏する。
According to the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, highly reliable solder bonding can be performed without performing surface treatment not only on the solder bonding surface of the metal base plate but also on the back surface pattern. , So it is extremely productive,
This has the effect of providing an extremely inexpensive semiconductor device. In addition, the use of non-flux solder eliminates the need for cleaning after solder joining, thereby improving productivity and reducing manufacturing costs.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 実施の形態1における半導体装置の側面断面
FIG. 1 is a side sectional view of a semiconductor device according to a first embodiment;

【図2】 実施の形態1における金属ベース板の平面図FIG. 2 is a plan view of a metal base plate according to the first embodiment.

【図3】 表面にNiめっき等が施されていない金属ベ
ース板の十点表面粗さ(Rz)に対するヒートサイクル
における基板下の半田クラックの進展度を示す実験デー
タを表すグラフ
FIG. 3 is a graph showing experimental data showing the degree of development of solder cracks under a substrate in a heat cycle with respect to ten-point surface roughness (Rz) of a metal base plate whose surface is not subjected to Ni plating or the like.

【図4】 十点表面粗さ(Rz)が4μmより大きい場
合の基板下の半田接合部を示す拡大模式図
FIG. 4 is an enlarged schematic view showing a solder joint under a substrate when ten-point surface roughness (Rz) is larger than 4 μm;

【図5】 十点表面粗さ(Rz)が4μmより小さい場
合の基板下の半田接合部を示す拡大模式図
FIG. 5 is an enlarged schematic view showing a solder joint under the substrate when the ten-point surface roughness (Rz) is smaller than 4 μm.

【符号の説明】[Explanation of symbols]

1 半導体素子、 2 絶縁基材、 3 回路パター
ン、 4 裏面パターン、 5 絶縁基板、 6 ベー
ス板、 7 半田材、 8 半田材、 9 レジスト塗
布面、 10 アルミワイヤ、 11 半田接合面、
12 金属間化合物層、 13 金属間化合物不形成
層、 14 半田フィレット先端。
DESCRIPTION OF SYMBOLS 1 Semiconductor element, 2 Insulating base material, 3 Circuit pattern, 4 Back pattern, 5 Insulating substrate, 6 Base plate, 7 Solder material, 8 Solder material, 9 Resist application surface, 10 Aluminum wire, 11 Solder joint surface,
12 intermetallic compound layer, 13 intermetallic compound non-forming layer, 14 solder fillet tip.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 高尾 治雄 福岡県福岡市西区今宿東一丁目1番1号 福菱セミコンエンジニアリング株式会社内 (72)発明者 中馬 秀明 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 Fターム(参考) 5F036 AA01 BB01 BC06 BC22 BD01 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Haruo Takao 1-1-1 Imajuku Higashi, Nishi-ku, Fukuoka City, Fukuoka Prefecture Inside Fukuryo Semicon Engineering Co., Ltd. (72) Hideaki Nakama 2-2-2 Marunouchi, Chiyoda-ku, Tokyo No. 3 Mitsubishi Electric Corporation F-term (reference) 5F036 AA01 BB01 BC06 BC22 BD01

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 銅もしくは銅基合金で形成された金属ベ
ース板と、前記金属ベース板と対向する面に銅もしくは
銅基合金で形成された裏面パターンを有する絶縁基板と
を半田で接合している半導体装置において、 前記裏面パターンには表面処理が施されており、前記金
属ベース板の半田接合面には表面処理が施されておら
ず、前記半田接合面の十点表面粗さ(Rz)が4μm以
下であり、前記裏面パターンと前記半田接合面がフラッ
クス入半田で接合していることを特徴とする半導体装
置。
1. A metal base plate formed of copper or a copper-based alloy and an insulating substrate having a back surface pattern formed of copper or a copper-based alloy on a surface facing the metal base plate by soldering. In the semiconductor device, a surface treatment is applied to the back surface pattern, a surface treatment is not applied to a solder joint surface of the metal base plate, and a ten-point surface roughness (Rz) of the solder joint surface is provided. Is 4 μm or less, and the back surface pattern and the solder joint surface are joined by flux-filled solder.
【請求項2】 前記裏面パターンにも表面処理が施され
ておらず、前記裏面パターンは十点表面粗さ(Rz)が
4μm以下であることを特徴とする請求項1に記載の半
導体装置。
2. The semiconductor device according to claim 1, wherein no surface treatment is performed on the back surface pattern, and the back surface pattern has a ten-point surface roughness (Rz) of 4 μm or less.
【請求項3】 銅もしくは銅基合金で形成された金属ベ
ース板と、前記金属ベース板と対向する面に銅もしくは
銅基合金で形成された裏面パターンを有する絶縁基板と
を半田で接合する半導体装置の製造方法において、 前記金属ベース板の半田接合面を十点表面粗さ(Rz)
が4μm以下になるように加工し、前記裏面パターンに
表面処理を施し、前記半田接合面に表面処理を施さず、
ノンフラックス半田を用いて、還元性ガス中、または還
元性ガスと不活性ガスの混合ガス中で、前記裏面パター
ンと前記半田接合面を半田接合することを特徴とする半
導体装置の製造方法。
3. A semiconductor in which a metal base plate made of copper or a copper-based alloy is joined to an insulating substrate having a back surface pattern made of copper or a copper-based alloy on a surface facing the metal base plate by soldering. In the method for manufacturing a device, a solder joint surface of the metal base plate may have a ten-point surface roughness (Rz).
Is processed so as to be 4 μm or less, a surface treatment is performed on the back surface pattern, and a surface treatment is not performed on the solder joint surface.
A method of manufacturing a semiconductor device, comprising: using a non-flux solder to solder-bond the back surface pattern and the solder bonding surface in a reducing gas or a mixed gas of a reducing gas and an inert gas.
【請求項4】 前記裏面パターンに表面処理を施さない
で、前記裏面パターンを十点表面粗さ(Rz)が4μm
以下になるように加工することを特徴とする請求項3に
記載の半導体装置の製造方法。
4. The back surface pattern having a ten-point surface roughness (Rz) of 4 μm without subjecting the back surface pattern to a surface treatment.
4. The method according to claim 3, wherein the processing is performed as follows.
JP2000241114A 2000-08-09 2000-08-09 Semiconductor device and method of manufacturing the same Pending JP2002057261A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000241114A JP2002057261A (en) 2000-08-09 2000-08-09 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000241114A JP2002057261A (en) 2000-08-09 2000-08-09 Semiconductor device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
JP2002057261A true JP2002057261A (en) 2002-02-22

Family

ID=18732352

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000241114A Pending JP2002057261A (en) 2000-08-09 2000-08-09 Semiconductor device and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP2002057261A (en)

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