JP2002057204A - Wafer-mapping method for wafer-loading port device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate evaluation of sidelong problem or overlap problems, to avoid the conventionally developed intricate calculation of wafer mapping. SOLUTION: A signal, having a pattern as the basis, is used as a substitution of intrinsic calculation procedures to accelerate an evaluation process. An absolute coordinate system is introduced to generate the signal, having the pattern as the basis and two optical sensor signals, and a feature extracting method is conducted. The feature extraction method generates characteristic signals of the sidelong problem and the overlap problem. Moreover, by converting the signals, the characteristic signal can be treated by a digital data processor. Thus, three major objects of the wafer mapping can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of operating a wafer load port system, and more particularly, to a method of mapping a wafer in a wafer load port apparatus.

[0002]

2. Description of the Related Art All types of process equipment are specifically designed to meet the needs of all types of the semiconductor industry. Various parameters are set for various conditions to be compatible with the process method and to further satisfy the process requirements. Nevertheless, the requirements for process stability, uniformity and accuracy are the same. Therefore, in various types of process equipment, the semiconductor wafer must be firmly fixed to the support, placed in a specific process chamber to carry out all semiconductor processes, and Considering the process parameters of a given design, the requirements of uniformity and accuracy must be met.

FIG. 1 shows a wafer carrier in a wafer load port device. Conventionally, the wafer load port device 20 is used to support the wafer carrier 22. Therefore, the wafer carrier is opened or closed. Conventionally, wafer load port device 2
0, to connect the wafer carrier 22 and to move the carrier to the fixed position of the load port device,
A support 26 is provided. The support 26 includes a partition 24. The structure of this partition is shown in FIGS. Plywood 4
Numeral 2 is at the top of the partition 24, and the plate 42 is movable. Further, the movable mating plate 42 has a latch key 54. When the wafer carrier 22 leans against the partition 24, the door of the carrier faces the direction of the partition 24, and the latch key 54 is inserted into two holes in the door of the carrier 22. After the latch key 54 is inserted into the hole, the latch key 54 is turned 90 ° to lock the door of the wafer carrier 22.
Rotate. Further, the plate moves backward, and the wafer carrier 22 is opened. Then, the mating plate 42 moves downward to a specific position. The above procedure describes how the wafer load port device releases the wafer carrier. When the above procedure is reversed, the opened carrier can be closed.

[0004] There are some design differences between wafer carriers manufactured by various manufacturers. Therefore, when carriers from different manufacturers are used together, a correction procedure is required. Thereafter, the load port device records the corrected value until the next operation of the same procedure. That is, during the correction process, the load port device re-records a new value. In addition, it should be noted that the above procedure is not only necessary when utilizing different carriers from different manufacturers, but also after the assembly of the load port device.

In performing the above technique, the side long problem and the overlap problem can be evaluated by considering the measurement of the recorded wafer position, coordinates and uncertain volume. As long as the side long problem or the overlap problem does not occur, the data obtained by the above technique can be used to decode the wafer position by a digital processor. However, the presence or absence of the side long problem or the overlap problem can be obtained by a complicated calculation method of the above technique.

[0006]

Accordingly, there is a need to accelerate the evaluation of these two problems in order to avoid the complicated calculations of wafer mapping developed in the past.

[0007]

SUMMARY OF THE INVENTION The present invention uses pattern-based signals as an alternative to complex computational procedures to accelerate the evaluation method. The present invention is constructed by further performing the feature extraction method by introducing absolute coordinates to generate a pattern based signal and two optical sensor signals by position. This feature extraction method generates feature signals for the side long problem and the overlap problem. Further, by converting the signal, the feature signal can be handled by a digital data processor. Thus, the present invention can achieve three main objectives of wafer mapping.

In summary, an advantage of the proposed wafer mapping method according to the present invention is that it utilizes a digital signaling method to detect wafer position, side long problems and overlap problems.

Furthermore, an advantage of the present invention is that it simultaneously detects wafer position, side long problems and overlap problems quickly.

The use of two sensors and position signals in wafer mapping is another advantage of the present invention.

In addition, the present invention is useful in performing the feature extraction method by executing an electric circuit for performing the feature extraction method.

Yet another advantage of the present invention is that it utilizes an integrated microcontroller coupled with a software program for performing the feature extraction method.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing aspects and many advantages of the present invention will be more readily understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: FIG.

Usually, 13 or 25 wafers are placed on the carrier at the current stage of development, so the mapping between each wafer and the load port device is very important. The position of the wafer located on the wafer carrier is transmitted to the process machine. Poor wafer mapping, as well as side-long and overlap problems, have severe consequences on wafer processing.

Generally, wafer mapping is accomplished by employing absolute coordinate and wafer thickness measurements.
The mapping method was developed by setting the original mechanical point to record the absolute coordinates of each wafer on the carrier.

Observation of the cross cut of the wafer reveals that each wafer has two coordinates consisting of upper and lower positions. Ideally, the distance between the two is equivalent to the wafer thickness. The coordinates are derived from a pattern-based signal by position. This signal is generated by a motor characterized by up and down movement. For example, pulse control signals of a stepper motor or a position sensor of a drive system (either an encoder or an optical meter) are used herein.

The three purposes of wafer mapping are as follows: to detect wafer position, side long problems and overlap problems.

The present invention utilizes pattern-based signals as an alternative to complex computational procedures to accelerate the evaluation method. The invention is constructed by introducing absolute coordinates and performing a feature extraction method to generate a pattern based signal and two optical sensor signals by position. This feature extraction method generates feature signals for the side long problem and the overlap problem. Further, by converting the signal, the feature signal is handled by a digital data processor. Thus, the present invention can achieve three main objectives of wafer mapping.

Details of the solution provided by the present invention are:
It is as follows.

The present invention utilizes a reflective type of optical sensor system, such as a reflective type of laser sensor. FIG. 4 shows the sensor structure. This reflection type optical sensor 86
Beam reaches the edge of the wafer 120. Thus, a mapping electronic signal is generated by determining whether the beam reflects off the optical sensor.

FIGS. 3 and 4 illustrate the implementation of the present invention. The wafer carrier 122 is provided in the wafer load port device 100. The door of this carrier is a partition 142
Facing the direction. For ease of explanation, the wafer 120 is shown in FIG. Behind the partition 142 is a mating plate 150. Furthermore, for example, there are two fixed optical sensors 86 on the mating plate. The data collection process of wafer mapping starts, and the collected data is input to a digital processor (not shown). The data processor is a central processing unit. In addition, a servomotor is used to move the mating plate 150 downward.

The mapping method constructed according to the present invention is as follows: the beam of the optical sensor strikes a reflector (not shown), the ply 150 moves down, and the beam is no longer reflected And the point at the bottom of the reflector is the initial reference position. Thereafter, the absolute coordinates of the wafer at the carrier can be recorded using the index and pulse signals of an encoder (not shown). For example, (Xi, Xp) indicates (pulse count of the index signal, pulse count). Each wafer has an upper limit (Xti, Xtp) and a lower limit (X
bi, Xbp) and record two coordinates. Thus, with the aid of the coordinates, the digital data processor generates a signal based on the mapping pattern by position. Since thirteen or twenty-five wafers are simultaneously placed in a normal wafer carrier, thirteen or twenty-five pulse signals are generated when the slot is completely inserted.

When the wafer carrier is mounted on its support, the support moves forward and the plywood latch key 132 locks the door of the carrier. In addition, the ply moves slightly backwards. Ready to retreat, but wafer mapping still works. After the ply retreats to the fixed position, three types of signals are generated. By reading the above signals, three main purposes of wafer mapping are achieved. How to reach the above goals will be discussed separately in the following sections.

Regarding wafer position: First, when no side long problem or overlap problem has occurred, a particular wafer position on the carrier is determined by the position based pattern based signal and the signal of one of the optical sensors. Can be determined by FIG. 8 shows the situation when all the slots have been inserted by the wafer, ie there is no vacancy in the carrier. FIG. 8 shows the case of a wafer in three slots. Signals based on patterns by position occur on a regular basis. This signal is generated by the motor of the ply plate, and this motor moves up and down. For example, the signals and motors are either pulse control signals or stepper motor position sensors. That is, any pulse signal of the pattern-based signal by position maps all slots. That is, FIG. 8 shows that the three pulse signals map three slots separately. Since there is a wafer in the slot, the waveforms and locations of the optical sensors 1 and 2 are the same as the waveforms and locations of the pattern-based signals by location. In addition, when there is no side long problem or overlap problem under normal conditions, the features of the side long problem and the overlap problem in FIG. 8 do not generate a pulse.

FIG. 9 shows a state where there is no wafer in the carrier. Three slots are utilized in this application. From this figure, it can be seen that a signal based on a pattern by position generates three pulses regularly. When a signal based on the second pattern by position occurs,
Interrogation of both or one of the optical sensors to determine if there is a pulse in the sensor signal. The presence of the pulse indicates that there is a wafer in the slot. The absence of a pulse indicates that there is no wafer in the slot. For example, when a second pulse of the pattern-based signal by position occurs, there is no wafer in the second slot and the two optical sensors do not generate a corresponding pulse signal (see FIG. 9). The side long feature signal or the overlap feature signal does not occur after performing the feature extraction method of FIG. 6 for the signal based on the two optical sensor signals and the position-based pattern. FIG. 6 shows a circuit diagram of feature extraction.

Thereafter, the signal is converted by the circuit shown in FIG. FIG. 7 shows a signal conversion circuit of the present invention. Since the values of both the side long signal and the overlap signal are 0, it can be evaluated that the first and third slots have no side long problem and no overlap problem. Only the second slot is empty with no wafer. As a result, the present invention can detect whether there is a wafer in the slot.

Detection of the side long problem: When the side long problem occurs, a time-based diagram of the three signals is obtained. The three signals map the three slot wafers independently (see FIG. 10). Further, the feature signal of the side long problem can be received by the feature extraction method shown in FIG.

FIG. 10 illustrates the occurrence of the side long problem of the wafer in the second slot. This figure shows that even if the signal based on the pattern by position is fixed,
When mapping the second slot, a slanting phenomenon occurs in the signals obtained by the optical sensors 1 and 2. As long as the signal obtained by the pattern-based signal by the two sensors and the position is processed by the feature extraction method shown in FIG. 6, both the side long feature signal and the overlap feature signal are generated.

Since only the side-elong problem occurs on the wafer in the second slot in the preset state, the overlap feature signal is filtered using the signal conversion circuit shown in FIG. Therefore, the value of the side long signal is 1 and that of the overlap signal is 0. The present invention can detect whether or not a side long problem has occurred in a wafer in a slot.

Detection of overlap problem: When the overlap problem occurs, a further time-based diagram of the three signals is obtained (see FIG. 11). The feature extraction method shown in FIG. 6 makes it possible to obtain the feature signal of the overlap problem.

FIG. 11 shows how the wafer in the second slot overlaps with the wafer in the third slot as a result of the misalignment. further,
This figure shows that there is an overlap between the pulse signals of the optical sensors 1 and 2 mapping the second and third slots, even if the pattern based signal by position is fixed. In theory, when an overlap problem occurs, the signal detected by the optical sensor does not indicate overlap, but may indicate a small distance between the wafers.

After processing the two optical sensor signals and the pattern based signal by position by performing the feature extraction method of FIG. 6, a feature signal of the overlap problem can be obtained. Thereafter, the value of the overlap signal is 1 and that of the side long signal is 0 by the signal conversion circuit shown in FIG.

The above feature extraction method can be executed by using a hardware circuit as shown in the circuit diagram of FIG.
Nevertheless, the invention is not limited by the extraction method. Computer software can also perform the same job and reach the same goal.

By converting the signal, the feature signal becomes a digital signal that can be used by a digital data processor.

It is clear that even if the overlap feature signal also occurs in FIG. 10, it occurs after the side long feature signal. In addition, there is no present overlap feature signal. This is because detecting the side long problem instead of the overlap problem is the main purpose. Thus, via FIG. 7 (signal conversion circuit plot), the overlap signal can be filtered to obtain the actual side long signal.

In summary, an advantage of the wafer mapping method proposed by the present invention is that it utilizes a digital signal method to detect wafer position, side long problems and overlap problems.

Further, an advantage of the present invention is that it simultaneously detects wafer position, side long problems and overlap problems quickly.

The use of two sensors and position signals in wafer mapping is another advantage of the present invention.

Finally, the present invention is beneficial in performing a feature extraction method by executing an electronic circuit or software program.

As will be appreciated by those skilled in the art, the foregoing preferred embodiments of the present invention are illustrative of the invention rather than limiting the invention. The present invention covers various modifications and similar arrangements included within the spirit of the invention and the appended claims, and the appended claims are to be accorded the widest construed scope and include all such modifications and similar It also includes the structure.

[Brief description of the drawings]

FIG. 1 is a side view of a prior art wafer load port device.

FIG. 2 is a rear view of a prior art wafer load port device.

FIG. 3 is a perspective view of a wafer load port device of the present invention.

FIG. 4 is a side view of the wafer load port device of the present invention.

FIG. 5 is a schematic view showing an optical sensor of the present invention.

FIG. 6 is a feature extraction circuit diagram of the present invention.

FIG. 7 is a signal conversion circuit diagram of the present invention.

FIG. 8 is a time-based diagram of a normal state without a wafer racking problem, a side long problem and an overlap problem.

FIG. 9 is a time-based diagram of a state with a wafer racking problem.

FIG. 10 is a time-based diagram of a state with a side long problem.

FIG. 11 is a diagram based on time of a state having an overlapping problem.

[Explanation of symbols]

 20, 100 Wafer load port device 22, 122 Wafer carrier 24, 142 Partition wall 26 Support body 42, 150 Laying plate 54, 132 Latch key 86 Optical sensor 120 Wafer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Wu Zongming 1st floor, Keelung Road, Taipei City, Taiwan No. 127, 7 Tower 2 F Term (Reference) 5F031 CA02 DA01 JA06 JA17 JA32 JA51 KA11

Claims (1)

[Claims] 1. A wafer mapping method for a wafer load port apparatus for mapping a plurality of wafers, comprising: a signal based on a pattern based on a position corresponding to a plurality of slots of a carrier; Generating a signal of an optical sensor type using two optical sensors, and using a signal based on a position-based pattern and an optical sensor type signal using two optical sensors. Performing a feature extraction method for separately generating a side long feature signal and an overlap feature signal using a feature extraction circuit.