JP2002056042A - Method for automatically arranging semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To arrange cells and to set the driving force of each cell so as to optimize the delay of an input-output network in the automatic arrangement processing of a semiconductor integrated circuit. SOLUTION: A cell arrangement area is divided, cells are allocated to and arranged in respective divided areas (steps 201 and 202), the calculation of micro path delay in the input-output network of each cell and the temporary shift and exchange of each cell position are attempted as much as possible while the calculation of micro path delay is performed in each arrangement, cell arrangement that brings about minimum delay is decided (steps 203 to 207), the micro path delay is further performed (step 210) while the temporary switching of driving force is attempted within an arrangeable range (steps 208 and 209), and the cell is automatically arranged so as to find the driving force setting of the cell which brings about the minimum delay.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technology for automatically arranging semiconductor integrated circuits.

[0002]

2. Description of the Related Art As a conventional technique relating to an automatic placement technique of a semiconductor integrated circuit, for example, a technique described in Japanese Patent Application Laid-Open No. 8-274177 is known. In this conventional technique, a logical group is logically divided into units called logical blocks, and cells that are hierarchically logically designed are placed on a substrate of a semiconductor integrated circuit.
While arranging cells belonging to the same block together,
It is intended to suppress the variation in the wiring length of the inter-block net to only the equivalent of the wiring length of the intra-block net.

[0003]

SUMMARY OF THE INVENTION It is an object of the prior art to reduce the wiring length in a block or between blocks and to reduce variations. However, since the delay is not considered, there is a technical problem that it is difficult to consider the delay shortening and the variation of the delay. In addition, when the driving force of the cell is switched, it is difficult to switch the driving force after the arrangement because the size of the cell changes.

An object of the present invention is to provide a technique for automatically arranging semiconductor integrated circuits, which can automatically arrange cells in consideration of delay.

Another object of the present invention is to provide a technique for automatically arranging semiconductor integrated circuits, which can realize cell arrangement for reducing delay.

Another object of the present invention is to provide a technique for automatically arranging semiconductor integrated circuits which can reduce a delay by switching a driving force in an automatic cell arrangement.

Another object of the present invention is to provide a technique for automatically arranging a semiconductor integrated circuit capable of shortening a delay by optimizing both cell arrangement and driving force.

Another object of the present invention is to improve the performance of a semiconductor integrated circuit obtained by automatic cell arrangement.

[0009]

SUMMARY OF THE INVENTION The present invention relates to a method for automatically arranging a semiconductor integrated circuit including a plurality of cells connected to each other. The delay is calculated for each net, and the cells are arranged so that the total result of the delays on the input side and the output side is reduced.

More specifically, as an example, connection information between cells and load driving force of cells are input from a design file, delay constants for individual cells and delay calculation constants are input, and the input data is input. When determining the cell placement position based on the cell, the cell is temporarily placed, and the virtual wiring length is calculated based on the connection relationship of the temporarily placed cell each time, and the delay of the input / output net of the temporarily placed cell is calculated. Is determined so that is minimized.

In addition, the delay of the input / output net is recalculated while simultaneously switching the cell driving force, and the driving force of the cell is switched when the delay is further reduced.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a conceptual diagram showing an example of a method of calculating a delay in an automatic placement method of a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is an example of an operation of the automatic placement method of the embodiment. , FIG. 3, FIG. 4, FIG.
FIG. 6 and FIG. 6 are conceptual diagrams showing an example of the operation of the automatic arrangement method according to the present embodiment.

First, an example of a formula for calculating a delay in the present embodiment will be described with reference to FIG. Delay (tp
d) is the sum of the basic delay (tpd0) and the load delay, and the load delay is obtained by multiplying the sum of the wiring capacitance (Cw) and the input pin capacitance (Cin) by the on resistance (tpdc). That is, the delay is tpd = tpd0 +
tpdc (ΣCw + ΣCin). The condition here is that the basic delay is constant, and the wiring capacitance (Cw)
Increase is proportional.

FIG. 2 shows an automatic placement method according to this embodiment.
9 shows an example of an automatic arrangement processing flow when applied to SA (Simulated Annealing).
In the SA method, first, the arrangement area is divided (step 20).
1) The cells are arbitrarily allocated to the divided placement areas (step 202), the micropath delay of the input / output net in the initial state is calculated (step 203), and the cells are moved to another placement area (step 202). 204), it is determined whether the cell can be placed at the destination (step 205). If the cell can be placed, the micropath delay of the input / output net after the cell is moved is recalculated (step 206), and the effect of shortening the micropath delay is determined. It is determined whether or not there is an effect (step 207). If there is an effect, the result of the cell movement in step 204 is determined.

Further, in order to optimize the delay from the viewpoint of the driving force of the individual cells, it is determined whether or not the cells can be arranged in the destination arrangement area after switching the driving force (step 20).
8 to 209), and if possible, recalculate the micropath delay of the input / output net after switching (step 21).
0) If the total value of the micropath delay after the switching is further reduced (step 211), the driving force of the cell is switched (step 212), and the arrangement position and the driving force are determined.

FIG. 3 shows an arrangement area 301 in a semiconductor integrated circuit according to the present embodiment and a cell 302 arranged therein.
1 to 304 are shown. Here, the driving force of the cell is a cell size as a condition, and the cell 302 is 1 ×, the cell 303 is 2 ×, and the cell 304 is 4 ×. Also,
As for the input pin capacitance (Cin), the cell 302 is a single booster.
Is set to 1, and the cells 303 and 304 of the double power and the four power are set to 2 and 4, respectively. The on resistance (tpdc) is 1
The booster cell 302 is set to 1 and the booster cell 302 is set to 1.
3. The on resistance of the cell 304 is １ ／, １ ／.

Each cell is composed of, for example, one or a plurality of logic elements and the like, and the cells are connected to each other to realize a semiconductor integrated circuit having a desired function.

FIG. 4 shows a case where a dividing line 401 is determined in the arrangement area 301 and a plurality of arrangement areas 4 defined by the dividing line 401 are defined.
A state where cells are arbitrarily allocated to each of the cells 01a is illustrated. In addition, one allocable capacity of one of the divided arrangement areas 401a is four cells 302 each having a single boost and two cells 30 each having a double power.
3 is a capacity capable of arranging two cells and one quadruple cell 304, and the wiring length is one division of the divided arrangement area 401a.
And

Next, when attention is paid to the cell 402 in the cell moving process, one cell is connected to the input side and three cells are connected to the output side. Here, the micropath delay in the initial state is shown in FIG.
, The micropath delay of the input net 403 is (1/4) × (3Cw + 1), and the output net 4
The micropath delay of 04 is 1 × (5Cw + 12).

FIG. 5 shows a state in which the cell 501 (cell 402 in FIG. 4) has been moved. Here, the destination placement area 401b
Since the cell 501 can be placed in the cell, comparing the total wiring length of the input / output nets of the cell 501 (402) before and after the movement, the wiring length on the input side before the movement is 3 and that on the output side before the movement is 5 and the total is 8, after the movement, the input side becomes 5, the output side becomes 4, and the wiring length becomes 9, and the wiring length after the movement is +1 wiring length longer than that before the movement. However, when compared with the micropath delay, the micropath delay of the input net 502 after the movement is (1/4) × (5Cw + 1) and the output net 5
The micropath delay of 03 is 1 × (4Cw + 12), and the wiring capacitance before and after moving on the input side becomes 3Cw / 4 to 5Cw / 4 when comparing the changing wiring capacitance, and + Cw.
/ 2, the wiring capacitance before and after movement on the output side is 5 Cw = 4
Cw becomes -1Cw, and the effect after the movement is that the wiring capacity of Cw / 2 is reduced. Since the wiring capacitance is reduced, the total micropath delay of the input net 502 and the output net 503 is reduced, and the cell 501 is allocated to the destination placement area 401b.

When the delay is reduced by switching the driving force during the moving process, the driving force is switched at the same time.

FIG. 6 shows a cell 601 (cell 402 in FIG. 4).
In the case where the capacity capable of arranging a double booster cell remains in the arrangement area 401b to which the (cell 501 in FIG. 5) has moved, and the cell 501 is switched from the single booster cell 501 to the double booster cell 601 after the movement. , The micropath delay of the input net 602 is (1
/ 4) × (5Cw + 2), the output net 603 is (1 /
2) × (4Cw + 12), and comparing the total micropath delay of the input / output net before switching with the micropath delay of the input / output net after switching, the total wiring capacitance before switching is 21 Cw / 4, and the switching is 21 Cw / 4. The subsequent wiring capacitance is 13 Cw / 4, the effect after switching is -2 Cw,
In the input pin capacitance, the input pin capacitance before switching is 49/4,
The input pin capacitance after switching becomes 13/2, the effect after switching becomes -23/4, and the delay is shortened by reducing the load capacitance.

By repeating the above processing for each cell, it is possible to consider the delay in the placement processing.

As described above, according to the method for automatically arranging semiconductor integrated circuits according to the present embodiment, when automatically arranging cells, delay calculation is performed for nets on the input side and the output side, thereby taking into account the delay. The arrangement can be optimized, and the driving force of the cell is switched in the middle of determining the arrangement position of the cell, so that the cell can be easily arranged even if the cell size changes.

As a result, the speed of the semiconductor integrated circuit obtained by the automatic cell arrangement can be increased by shortening the delay and the like, and the performance of the semiconductor integrated circuit is improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof. Needless to say, there is.

[0028]

According to the method for automatically arranging semiconductor integrated circuits of the present invention, an effect is obtained that cells can be automatically arranged in consideration of delay.

According to the method for automatically arranging semiconductor integrated circuits of the present invention, an effect is obtained that cell arrangement for reducing delay can be realized.

According to the method for automatically arranging semiconductor integrated circuits of the present invention, there is an effect that the delay can be reduced by switching the driving force in the automatic cell arrangement.

According to the method for automatically arranging semiconductor integrated circuits of the present invention, there is an effect that the delay can be reduced by optimizing both the cell arrangement and the driving force.

According to the method for automatically arranging semiconductor integrated circuits of the present invention, the effect is obtained that the performance of the semiconductor integrated circuit obtained by the automatic cell arrangement is improved.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing an example of a delay calculation method in an automatic semiconductor integrated circuit placement method according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an example of the operation of the method for automatically arranging semiconductor integrated circuits according to one embodiment of the present invention;

FIG. 3 is a conceptual diagram showing an example of the operation of the method for automatically arranging semiconductor integrated circuits according to an embodiment of the present invention.

FIG. 4 is a conceptual diagram showing an example of the operation of the method for automatically arranging semiconductor integrated circuits according to an embodiment of the present invention.

FIG. 5 is a conceptual diagram showing an example of the operation of the method for automatically arranging semiconductor integrated circuits according to one embodiment of the present invention.

FIG. 6 is a conceptual diagram showing an example of the operation of the method for automatically arranging semiconductor integrated circuits according to one embodiment of the present invention.

[Explanation of symbols]

301 ... arrangement area, 302 ... cell (1 boost), 303 ...
Cell (double boost), 304 ... cell (4 boost), 401 ... partition line, 401a ... placement area, 401b ... placement area, 40
2 ... cell, 403 ... input net, 404 ... output net,
501 ... cell, 502 ... input net, 503 ... output net, 601 ... cell, 602 ... input net, 603 ... output net.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Masato Mogaki 1st Horiyamashita, Hadano-shi, Kanagawa Prefecture, Hitachi, Ltd. Enterprise Server Division (72) Inventor Tetsuo Sasaki 1st Horiyamashita, Hadano-shi, Kanagawa, Hitachi, Ltd. (72) Inventor Yuki Mimura 6-81 Onoecho, Naka-ku, Yokohama-shi, Kanagawa Pref. Hitachi Software Engineering Co., Ltd. In-house F-term (reference) 5B046 AA08 BA05 JA01 5F038 CA04 CA17 CD09 EZ09 EZ20 5F064 DD02 DD03 DD24 EE08 EE47 FF04 FF52 HH06 HH09 HH12

Claims (3)

[Claims] 1. A method for automatically arranging a semiconductor integrated circuit including a plurality of cells connected to each other, the method comprising: determining an arrangement position of a plurality of cells; A method for automatically arranging semiconductor integrated circuits, comprising calculating a delay and arranging the cells such that the total result of the delays on the input side and the output side is reduced. 2. A method for automatically arranging a semiconductor integrated circuit according to claim 1, wherein when arranging the cell, the driving force of the cell is switched while deciding the arrangement position, and the delay calculation result after the switching is determined. A method for automatically arranging semiconductor integrated circuits, wherein the driving force of the cell is switched when the delay is shorter than the result of calculation of the delay before switching. 3. A method for automatically arranging a semiconductor integrated circuit including a plurality of cells connected to each other, comprising: a first step of dividing an arrangement area of the plurality of cells into a plurality of unit areas; A second step of temporarily arranging the cell in each of the above; calculating delays in nets on each of an input side and an output side of the cell; moving and exchanging the arrangement position of the cell within a possible range; A third step of finding an arrangement of the cells in which the delay is reduced; a provisional switching and switching of the driving force of each of the cells within a possible range with respect to the arrangement of the cells in which the delay is found in the third step; Later calculating the delay in each net on the input and output sides of the cell,
And 4. finding a setting of the driving force for each cell such that the delay is reduced by repeating the above steps.