JP2002055849A - Debugging method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To normally apply debugging processing using a hardware braking function to a program driven in a CPU using a virtual storage and an operating system. SOLUTION: When hardware brake occurs during the debugging processing of an application program 43 and a state that a current address is a virtual address which can not be converted by a CPU 41 is detected, the debugger 22a temporarily releases the hardware braking function and executes an address error processing routine in the operating system 42 to perform address error processing. Then the hardware braking function is set again and the application program 43 is executed again. When the hardware brake occurs, the CPU 41 can access the address, so that the debugger 22a can perform code analysis operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention controls a debugging mechanism based on boundary scan, which is mounted on a CPU that operates an operating system having a virtual memory control function and an application program that operates on the operating system. In particular, the present invention relates to a debugging method for debugging an application program, and particularly to a debugging method for performing debugging using a hardware break function when the operating system does not have a debugging auxiliary function for the application program and when the operating system has the debugging auxiliary function. About.

[0002]

2. Description of the Related Art In recent years, as a method of debugging a CPU or a program in embedded development of a microprocessor system, a JTAG (Joint Test Action Group) has been developed.
A debugging method called boundary scan using p) is known. JTAG is an IEEE (Institute of Electrical and Electronics) that is a boundary scan test standard.
dElectronic Engineers) is a work group name of 1149.1, which is commonly used as a boundary scan test standard. In this debugging method, a JTAG debugging mechanism is mounted on a CPU of a test target (target) system, a test signal is input, and a signal output as a result is analyzed to determine whether components on the CPU and the motherboard are correctly mounted. Check whether the program executed by the CPU is correctly executed.
For example, a CPU with a JTAG debug module
And debugging of a target system constituted by an operating system and an application is performed by connecting a host computer such as a personal computer to a CPU via a JTAG-ICE (Incircuit Emulator) unit and allowing a user to operate on the host computer. It is realized by operating the JTAG-ICE unit using a processing program (hereinafter, referred to as a debugger). As described above, the remote debugger using the JTAG debugging mechanism and the JTAG-ICE provided in the CPU has a high communication speed, a single step function, a forced stop function, a hardware break function, and the like. It has become a powerful tool.

[0003]

Among the above functions of the debugger, the hardware break function is a function that stops execution of a program when a specific address is referenced or an instruction at this address is executed. It gives the debugger user an opportunity to analyze the program, and is an essential function for debugging programs. However, when the operating system of the target system handles the virtual space, a problem may occur in the JTAG debugging process as described above. For example, if an address in the virtual space hits a hardware break and the address cannot be translated using the address translation function of the CPU, the user using the debugger may add A problem such as inaccessibility occurs, and the code analysis work by the user becomes impossible. Further, when the debugger refers to a virtual address that is not translated by the CPU, a fatal error occurs, and a situation is caused in which the debugging process becomes impossible.

The present invention has been made in view of such a problem, and normally performs a debugging process using a hardware break function on a CPU using virtual storage and a program operating on an operating system. The purpose of the present invention is to provide a debugging method capable of performing the following.

[0005]

According to the present invention, in order to solve the above-mentioned problem, an operating system having a virtual memory control function and an application program operating on the operating system are provided.
A hardware break function is set in a debugging method when the operating system does not have a debugging assistance function for the application program by controlling a debugging mechanism by a boundary scan implemented in the PU and performing debugging of the application program. Then, the application program is executed on the CPU, a hardware break occurs, and when it is detected that the address at this time is a virtual address that cannot be converted by the CPU, the hardware break function is released, The address error handling routine provided in the operating system
A debugging method characterized by causing a PU to execute a process of converting the virtual address to a physical address, setting the hardware break function again, and causing the CPU to re-execute the application program. Is provided.

In such a debugging method, a hardware break occurs during the debugging process, and when the address at this time is detected by the CPU as a virtual address that cannot be converted, the hardware break function is temporarily released. Since the address error processing routine provided in the operating system is executed by the CPU and the inaccessible virtual address is converted into the physical address, the hardware break processing is set again thereafter, and the debugging processing is continued. Then, when a hardware break occurs at this address, the conversion to the physical address is correctly performed and the target instruction code or data can be accessed, so that a normal program analysis operation can be performed.

Further, according to the present invention, a debugging mechanism based on a boundary scan, which is mounted on a CPU that operates an operating system having a virtual memory control function and an application program that operates on the operating system, is controlled. In the debugging method in which the application program is debugged and the operating system has a debugging auxiliary function for the application program,
A hardware break function is set and the application program is executed on the CPU, and a hardware break occurs.
When it is detected that the virtual address cannot be converted by the CPU, the hardware break function is released, and when an error is detected in the execution of the instruction at the address by the debug assist function, the CPU executes the instruction again. Causing an instruction exception, and when the error is not detected, causes the CPU to execute an address error processing routine provided in the operating system, and causes the virtual address to be converted to a physical address, A debugging method is provided, wherein the hardware break function is set again and the CPU is caused to re-execute the application program.

In such a debugging method, when a hardware break occurs during the debugging process and the CPU detects that the address at this time is a virtual address that cannot be converted, the hardware break function is temporarily released. First, an error in an instruction executed at this address is detected by a debugging auxiliary function provided in the operating system. If an error is detected, the CPU causes the CPU to execute the instruction again to generate an instruction exception. Can perform debugging work. If no error is detected, an address error processing routine provided in the operating system is executed by the CPU, and the inaccessible virtual address is converted into a physical address. As a result, the hardware break processing is set again thereafter and the debugging processing is continued, and when a hardware break occurs at this address, the conversion to the physical address is correctly performed and the target instruction code or data is accessed. It becomes possible, and normal program analysis work can be performed.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration example of a debugging system in which the debugging method of the present invention is realized.

The debugging system 1 comprises a host computer 2 which is a terminal on which debugging operations are performed by a user such as a programmer, a JTAG-ICE unit 3 controlled by the host computer 2, and a target system 4 to be debugged. You. The host computer 2 includes a processor and a semiconductor ROM (Reed
An information control device 21 composed of Only Memory), a RAM (Random Access Memory) or the like, a storage device 22 such as a hard disk for performing auxiliary storage, an input device 23 such as a keyboard and a mouse, and a display. This is a general computer device such as a personal computer, which includes a display device 24 and an interface 25 including a connector or the like for electrically connecting to the JTAG-ICE unit 3. The target system 4 includes a CPU 41 on which a debug module 41a having a JTAG debugging function is mounted, an operating system 42 executed by the CPU 41, and an application program 43 operating on the operating system 42. Machines, information devices, communication devices, computer devices, etc. that are built-in and developed.

In the debug system 1, a user executes a debugger 22a on the host computer 2 and controls the JTAG-ICE unit 3 by the debugger 22a to perform a debugging process. On the other hand, the debug module 41a mounted on the CPU 41 of the target system 4 includes a TAP (Test Access Por).
A serial interface called t) is provided, which is connected to the JTAG-ICE unit 3 to input / output commands, test data, test result data, and the like to / from the target system 4. JTAG
-The ICE unit 3 controls the debug module 41a in the CPU 41 to access the register and memory in the target system 4, execute and stop the program, and execute the hardware break function and the break point. Provides an interface for debugger functions such as setting and notification of debug events.

Further, the CP in the target system 4
U41 has a virtual address translation function. The operating system 42 has a virtual address control function, and the application program 43 can operate on a virtual address under the support of the operating system 42.

Next, in the debug system 1,
Debug processing when the hardware break function is used will be described. As described above, in the debug system 1, the debugger 22 a
By executing the JTAG-ICE unit 3
The debug module 41a mounted on the CPU 41 of the target system 4 is controlled via the. When the hardware break function is used, the user can use the debugger 22
a to set a hardware break,
When the application program 43 is executed, the execution of the application program 43 is stopped at the time of referring to the set address or the like, and information such as the instruction code and the test data from the debug module 41a at this time is stored in the host computer 2. It is displayed on the display device 24. The user looks at this and analyzes the contents of the application program 43, and corrects the program using the input device 23 as necessary.

Here, the application program 43
When virtual storage is used by the CPU 41 and the operating system 42 in the debugging process described above, the following is performed. FIG. 2 shows a flowchart of a debugging process by executing the debugger 22a in the host computer 2 in this case. FIG. 3 shows a flowchart of the address error processing shown in step S208 in FIG. Here, a case where the debug assist function for the application program 43 is not provided in the operating system 42 or a case where this function is released will be described.

At the start of the debugging process shown in FIG. 2, the user causes the debugger 22a to be executed on the host computer 2, and the JTAG-ICE is input by the input device 23.
By transmitting a control signal to the unit 3, the application program 43 to be debugged is operated on the operating system 42, and the application program 43 can be debugged by the debugger 22a. In step S201, the user inputs an instruction for setting a hardware break function from the host computer 2, and sets an address at which arbitrary data or an instruction is stored as a hardware break point. At this time, the execution of the application program 43 is suspended, and the hardware break function is set. In step S202, the user restarts the execution of the application program 43.

In step S203, in the application program 43 being executed, a hardware break occurs by referring to the set address, and the debugger 22a detects this through the JTAG-ICE unit 3 and Is displayed on the display device 24 to notify the user. In step S204, the debugger 22a detects whether the address causing the hardware break is an address in the virtual space. If this address is not a virtual address, the process proceeds to step S205. In step S205, the information such as the referenced data and the instruction code or the data indicating the state in the target system 4 is displayed by the hardware break function on the display device 2 of the host computer 2.
4, the user sees this and performs a debugging operation such as an analysis operation of the application program 43. If it is determined in step S204 that the address at which the hardware break has occurred is a virtual address, the process proceeds to step S206. In step S206, the debugger 22a detects the state of the virtual address conversion function provided inside the CPU 41. As a result of this detection, if the target virtual address can be converted into a physical address by the CPU 41, the physical address can be accessed to refer to predetermined data or an instruction. Is displayed on the display device 24, and the user can perform a debugging operation. Step S206
If it is detected that the virtual address cannot be converted to a physical address and causes an address exception,
Proceed to step S207.

In step S207, the debugger 22
a temporarily cancels the hardware break function set by the user in step S201,
In step 208, an address error process is performed for the virtual address that could not be accessed. Step S208
3 is shown in FIG. In step S301 in FIG. 3, the debugger 22a sets a temporary hardware break at the start address of the address error processing routine executed in the case of an address exception among the interrupt handlers provided in the operating system 42 of the target system 4. Step S302
, The debugger 22a causes the application program 43 to re-execute from the instruction to access the virtual address. In step S303, the CPU 41 causes an address exception by accessing this virtual address, and the address error processing routine set in step S301 is started. At this time, step S30
1 is set to the temporary hardware break state, and the debugger 22a detects this state and
4 to notify the user. In the CPU 41, an address error processing routine is executed.
The virtual address conversion table in the PU 41 is rewritten, the target virtual address is converted into a physical address, and the physical address becomes accessible by the CPU 41. When the address error processing is completed, the debugger 2
2a detects this end and proceeds to step S304.
The temporary hardware break set in step S301 is released.

When the address error processing in steps S301 to S304 is completed, the process proceeds to step S209 in FIG. 2, and the debugger 22a sets the hardware break released in step S207 again. Step S210
, The debugger 22a causes the CPU 41 to re-execute the application program 43 from the instruction to access the virtual address subjected to the address error processing. Proceeding to step S203, a hardware break occurs at this virtual address and the debugger 22a
Detects this and notifies the user. Step S204
In, the debugger 22a detects that this address is a virtual address, and proceeds to step S206, where C
The state of the virtual address translation function inside the PU 41 is detected. The virtual address is in a state where it can be converted into a physical address by the address error processing in step S208. The CPU 41 accesses this physical address to refer to predetermined data or an instruction, and proceeds to step S205. , The debugger 22a performs display by the hardware break function on the display device 24,
The user can perform a debugging operation.

According to the above-described debugging algorithm, when the virtual address at which a hardware break occurs cannot be converted into a physical address by the CPU 41,
The hardware break is temporarily released and re-executed, and a virtual address conversion process is performed by executing an address error processing routine for processing an address exception provided in the operating system 42. Thereafter, a hardware break is generated again at the same address, and it is assured that this address can be converted into a physical address by the CPU 41. Then, the hardware break function is displayed to enable a debugging operation. The debugger 22a continues processing for the occurrence of a hardware break set by the user until the relevant virtual address can be converted into a physical address by the CPU 41. By such processing, the hardware break function can be used in debugging the application program 43 executed using the virtual memory, and the efficiency of the debugging operation is improved. In such a debugging operation on the host computer 2, the user
It can be operated without considering the virtual address.

The debug assist function for the application program 43 is provided by the operating system 4.
2, and the debugger 22a performs the following process when the error of the program can be detected in each process of the application program 43. FIG. 4 shows a flowchart of the debugging process when the debugging function is provided. In FIG. 4,
The same processing as the step in the debugging processing shown in FIG. 2 is denoted by the same reference numeral.

At the start of the debugging process shown in FIG. 4, the user, through the debugger 22a executed in the host computer 2, executes the debugging process in the same manner as the process shown in FIG. It is assumed that the application program 43 is operating on the operating system 42 and is in a debuggable state at this time. The processing of steps S201 to S206 is the same as the processing shown in FIG. That is, in step S201, the execution of the application program 43 is suspended, and a hardware break is set. In step S202, the execution of the application program is resumed.

In step S203, a hardware break occurs at the set address and the debugger 2
2a detects this and notifies the user, and step S20
At 4, it is detected whether this address is a virtual address. If not a virtual address, step S20
Proceeding to step 5, display is performed by the hardware break function on the display device 24 to enable the user to perform a debugging operation. If it is determined in step S204 that the virtual address is a virtual address, the process advances to step S206 to detect whether the virtual address can be converted to a physical address by the address conversion function of the CPU 41. If the conversion is possible, it is possible to access the physical address to refer to predetermined data or an instruction, etc.
In step 05, the display is performed by the hardware break function, and the debug operation becomes possible. Step S206
If the virtual address cannot be converted to a physical address and cannot be accessed in the detection in step S207, the process proceeds to step S207, where the setting of the hardware break set in step S201 is temporarily released, and step S401 is performed.
Proceed to.

In step S401, the debugger 22
a detects whether or not there is an error in execution of an instruction at a corresponding address by using a program debugging assist function provided in the operating system 42. If an error is detected by this, step S4
In step 02, the application program 43 is re-executed from this instruction. In step S403, the re-executed application program 43 generates an error in the execution of this instruction and becomes an exception.
2a detects this exception and displays it on the display device 24. The user operates the debugger 22a to perform a debugging process on the program error.

If no error is detected in the instruction in step S401, the cause of the inability of the CPU 41 to access the virtual address is an address translation error, and the subsequent steps S208 to S210 are the same as in FIG. Is performed. That is, in step S208, the application program 43
Are re-executed to generate an address exception, and an address error processing routine for the address exception provided in the operating system 42 is activated to perform the address conversion processing, which is the processing of steps S301 to S304 shown in FIG. . As a result, the corresponding virtual address becomes accessible by the CPU 41, the hardware break is set again in step S209, and the application program 43 is re-executed in step S210. Thereafter, in step S203, a hardware break occurs and the debugger 22
a detects this, a virtual address is detected in step S204, it is detected in step S206 that this virtual address can be converted by the CPU 41, and the converted physical address is accessed. The display by the hardware break function is performed on the device 24, and the debugging operation can be performed.

As described above, when the operating system 42 of the target system 4 is provided with a program debugging auxiliary function, a hardware break occurs and this address is an inaccessible virtual address. Is detected, the debug assist function performs error detection for the execution of the instruction at this address. This makes it possible to detect the cause of the error when the corresponding virtual address becomes inaccessible in the debugging process using the hardware break function.

[0026]

As described above, according to the debugging method of the present invention, if the operating system does not have a debugging assistance function for the application program, a hardware break occurs during the debugging process, and the address at this time is the CPU address. When it is detected that the virtual address is an untranslatable virtual address, the hardware break function is temporarily released, and an address error processing routine provided in the operating system is executed by the CPU to convert the inaccessible virtual address to the physical address. After this, the hardware break processing is set again and the debugging processing is continued. When a hardware break occurs at this address, the conversion to the physical address is performed correctly and the target instruction code is executed. Ah There will be possible to access the data, and the like. By such a process, it is possible to perform a debugging process using the hardware break function even for an application program executed using the virtual memory, and it is possible to improve the efficiency of the debugging operation.

According to the debugging method of the present invention, when the operating system has an auxiliary debugging function for an application program, a hardware break occurs during the debugging process, and the address at this time is a virtual address which cannot be converted by the CPU. Is detected, the hardware break function is temporarily released, and first, an error in execution of the instruction at this address is detected by a debugging auxiliary function provided in the operating system. If an error is detected, the CPU is disabled. The instruction can be re-executed to generate an instruction exception, and the instruction can be debugged. This makes it possible to detect the cause of the error when the CPU becomes inaccessible to the virtual address. If no error is detected in the instruction, an address error processing routine provided in the operating system is executed by the CPU to convert the inaccessible virtual address to a physical address. As a result, the hardware break processing is set again thereafter and the debugging processing is continued, and when a hardware break occurs at this address, the conversion to the physical address is correctly performed and the target instruction code or data is accessed. It becomes possible. By such a process, it is possible to perform a debugging process using the hardware break function even for an application program executed using the virtual memory, and it is possible to improve the efficiency of the debugging operation.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a schematic configuration of a debugging system in which a debugging method of the present invention is realized.

FIG. 2 shows a flowchart of a debugging process by execution of a debugger when the operating system does not have a debugging assistance function for an application program.

FIG. 3 shows a flowchart of an address error process shown in step S208 in FIG.

FIG. 4 shows a flowchart of a debugging process when the operating system has a debugging assist function.

[Explanation of symbols]

1 ... Debug system, 2 ... Host computer,
3 ... JTAG-ICE unit, 4 ... target system, 21 ... information control device, 22 ... storage device, 2
2a: debugger, 23: input device, 24: display device, 25: interface, 41: CPU, 41a
…… Debug module, 42 …… Operating system, 43 …… Application program

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) G06F 12/10 541 G06F 12/10 541

Claims (4)

[Claims] 1. An operating system having a virtual memory control function and an application program operating on the operating system.
Controlling a debugging mechanism by a boundary scan implemented in the PU to debug the application program, and setting a hardware break function in a debugging method when the operating system does not have a debugging auxiliary function for the application program. Then, the application program is executed on the CPU, a hardware break occurs, and when it is detected that the address at this time is a virtual address that cannot be converted by the CPU, the hardware break function is released, Causing the CPU to execute an address error processing routine provided in the operating system to convert the virtual address into a physical address, and set the hardware break function again And the CP
U. Re-execute the application program. 2. The debugging mechanism according to the JTAG standard, wherein the debugging mechanism is realized by connecting a JTAG-ICE to the debugging mechanism and controlling the debugging mechanism via the JTAG-ICE. 1. The debugging method according to 1. 3. An operating system having a function of controlling a virtual memory and an application program operating on the operating system.
Controlling a debugging mechanism by a boundary scan implemented in the PU to debug the application program, and setting a hardware break function in a debugging method when the operating system has a debugging auxiliary function for the application program. Executing the application program on the CPU to cause a hardware break, and if it is detected that the address at this time is a virtual address that cannot be converted by the CPU, release the hardware break function; If an error is detected in the execution of the instruction at the address by the debug assist function, the CPU causes the CPU to execute the instruction again to generate an instruction exception. If the error is not detected, the Causing the CPU to execute an address error processing routine provided in the switching system to convert the virtual address to a physical address, set the hardware break function again, and
U. Re-execute the application program. 4. The debugging mechanism according to the JTAG standard, wherein the debugging mechanism is realized by connecting a JTAG-ICE to the debugging mechanism and controlling the debugging mechanism via the JTAG-ICE. 3. The debugging method according to 3.