JP2002055843A - Logic verification device and method for integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently perform highly accurate system verification by making it possible to utilize an individual verification test for system verification. SOLUTION: Plural individual verification test descriptions corresponding to plural peripheral circuits included in an integrated circuit, system verification test description for performing logic verification by simultaneously driving plural peripheral circuits, individual verification utilities for describing the contents of execution when individually verifying a command described in each individual verification test description, and a system verification utilities for describing the contents of execution at the system verification of a command described in each individual verification test description are prepared. In the case of executing an individual verification test, the individual verification test description corresponding to the peripheral circuit to be verified is executed by using its corresponding individual verification utility. In the case of executing a system verification test, plural individual verification test descriptions are executed in accordance with the system verification utilities corresponding to respective individual verification test descriptions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification device and method for an integrated circuit.

[0002]

2. Description of the Related Art Generally, in a logic verification test for an integrated circuit such as a system LSI, a test for individually verifying each of a plurality of peripheral circuits included in the integrated circuit (hereinafter, referred to as an individual verification) and a plurality of tests are performed. A test that verifies peripheral circuits by operating them simultaneously (hereinafter referred to as system verification)
And were described separately.

In the individual verification, (1) a method for describing a test for accessing a peripheral circuit to be verified from a CPU, and (2) an input / output signal or an internal circuit of the peripheral circuit to be verified are directly controlled. Test writing methods are often used.

In the system verification, (1) in a method of describing a test for simultaneously operating a CPU and peripheral circuits, a description of a test for a plurality of peripheral or colors is replaced with a description of the test for the individual verification. Separately prepared methods are often used.

[0005]

However, in the above conventional example, (1) it is necessary to describe the individual verification test and the system verification test separately, which is inefficient. (2) When the individual verification test is diverted to the system verification, the CPU command request from each individual verification test collides, and the shared memory area used in each individual verification test collides.・ There is a problem that some tests cannot be used in system verification.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to enable a test for individual verification to be used for system verification, thereby efficiently performing high-accuracy system verification. Is to make it possible.

[0007]

According to the present invention, there is provided a logic verification apparatus for an integrated circuit having the following configuration. That is, an apparatus for performing a logic verification process on an integrated circuit, comprising: a plurality of individual verification test descriptions corresponding to a plurality of peripheral circuits included in the integrated circuit; A description of a system verification test for verifying, an execution description for individual verification describing an execution content of the command described in the individual verification test description at the time of individual verification for each of the plurality of individual verification tests, Storage means for storing a system verification execution description that describes the execution contents of the command described in the test description at the time of system verification, and individual verification corresponding to a peripheral circuit to be verified when an individual verification test is instructed An individual verification unit that executes a test description in accordance with an individual verification execution description corresponding to the individual verification test description; And a system verification means for executing a plurality of individual verification test description specified by the stem validation test description, according to each individual validation test corresponding system verification run described in the description.

According to another aspect of the present invention, there is provided a logic verification method for an integrated circuit for performing a logic verification process on an integrated circuit, which is included in the integrated circuit. A plurality of individual verification test descriptions corresponding to a plurality of peripheral circuits; a system verification test description for simultaneously operating the plurality of peripheral circuits to perform logic verification; and an individual verification test for each of the plurality of individual verification tests. An execution description for individual verification that describes the execution content of the command described in the description at the time of individual verification, and an execution description for system verification that describes the execution content of the command described in the individual verification test description at the time of system verification When the individual verification test is stored, the individual verification test description corresponding to the peripheral circuit to be verified is stored in the individual verification execution description corresponding to the individual verification test description. Therefore, a system for executing a plurality of individual verification test descriptions specified by the system verification test description in accordance with a system verification execution description corresponding to each individual verification test description in the individual verification step to be executed and the execution of the system verification test. And a verification step.

In this specification, the description is a general term for a program description, a source code, an execution code for a computer, and the like.

[0010]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment] FIG. 1 is a block diagram showing a system configuration for performing logic verification of a system LSI according to an embodiment.

In FIG. 1, 101 is a system verification test, 102 to 104 are individual verification tests of peripheral circuits,
105 is a utility used in each verification test, 1
06 is a system environment setting file.

Reference numeral 107 denotes a system LSI to be subjected to logic verification, which includes a system bus 108, a CPU system bus operation circuit 109, and peripheral circuits 110 to 11
2. Read-only memory 113 for storing programs
(Hereinafter, ROM), a shared memory 114, and a memory controller 115.

Tests for logic verification of the peripheral circuits 110 to 112 are described as individual verification tests 102 to 104, respectively.

The system environment setting file 106 defines the configuration of the entire system, for example, the capacity of the shared memory 114, the frequency of the system bus 108, and the like. In addition, the test environment, for example, the distinction between the system verification and the individual verification and the maximum number of errors for terminating the test are specified.

When the test environment of the system environment setting file 106 is set to the individual verification and the test 102 for the individual verification is started, the system bus operation circuit 109 of the CPU sends the system bus to the peripheral circuit 110 and the shared memory 114. Access through 108 occurs. This is performed by starting a CPU command in the utility 105 from the individual verification test 102. Utility 105 called from individual verification test 102
Controls the system bus operation circuit 109 of the CPU according to a predetermined operation. As a result, a CPU access via the system bus occurs, and when a series of operations is completed,
The control of the program returns to the called individual verification test 102. This series of operations is repeated, and the verification is advanced by comparing the expected operation of the peripheral circuit.

On the other hand, when the test environment of the system environment setting file 106 is set to the system verification and the system verification test 101 is started, the individual verification tests 102 to 1 are started.
04 are activated simultaneously. Individual verification test 102-10
No. 4 tries to activate the system bus operation circuit 109 of the CPU as described above. However, CPU system
Since there is only one bus operation circuit 109, it is necessary to arbitrate the CPU command activation requests from the individual verification tests 102 to 104. In addition, since each individual verification test attempts to access the shared memory 114, it is necessary to distribute the area of the shared memory 114 to be used. Furthermore, if the individual verification test cannot be used for system verification, it must be prevented from being used. The details of this mechanism will be described below with reference to FIG.

FIG. 2 shows a description example of a test. Testing is a hardware description language, Ve
It is assumed to be written in rilog HDL.

Reference numeral 201 denotes a description example of the individual verification test 102. Reference numeral 202 denotes an environment file for distributing a command called by the test 201 to a specific utility. 203 is a description example of the environment setting file 106 for individual verification, and 204 is the environment setting file 1 for system verification.
Description example of 06, 205 is a utility at the time of individual verification,
Reference numeral 206 denotes a utility at the time of system verification, and 207, a program for arbitrating CPU commands at the time of system verification. Utility 206 during system verification
It is assumed that a separate file is prepared for each test (102 to 104).

In the individual verification test 201, 208
Is a link to the environment file 202, 209 is a flag indicating whether or not the individual verification test can be used in the system verification test, 210 is an instruction for assigning an available memory address get_addr, 211 is an instruction for reading data from the memory to the CPU. rdW.

In the environment file 202, reference numeral 212 denotes a conditional branch to system verification, and 213 denotes a conditional branch to individual verification.

In the individual verification utility 205, 214 is an available memory address assignment task, 215 is an operation of an available memory address, 216
Is a read instruction task to the CPU, 217 is a system
4 shows a read request to the bus operation circuit 109.

In the system verification utility 206, reference numeral 218 denotes an available memory address assignment task; 219, an operation of an available memory address;
Is a read instruction task to the CPU, 221 is a system
4 shows a read request to the bus operation circuit 109.
Reference numeral 222 denotes a CPU command arbitration request, 223 denotes acceptance of the CPU command arbitration request 222, 224 denotes cancellation of the CPU command arbitration request 222, and 225 denotes cancellation of the CPU command arbitration request acceptance 223.

When the system environment setting file 203 is selected to perform individual verification, the individual verification utility 205 is used by the conditional branch 213 of the environment file 202. Therefore, when the test 201 for individual verification is activated, the get_addr command 210 activates the get_addr command 214 in the utility 205. Similarly, an rdW command 211 which is a CPU command
Starts the rdW command 216 in the utility 205. The system environment setting file 203 is selected by selecting a file to be used. For example,
Compile the HDL and system.dbg files together for system verification, or HDL and device1.
Compile the dbg files together. Verification is performed on the test bench compiled in this way.

On the other hand, when the system environment setting file 204 is selected for system verification, the environment file 2
By the conditional branch 212 of 02, the system verification utility 206 is used. In this case, a test 201 for individual verification is changed from a test for system verification described later with reference to FIG.
Is started, and system_available 209 is evaluated first. When the value of system_available is 0, the individual verification test is not used in the system verification test.
Details of this mechanism will be described with reference to FIG.

When the content of system_available 209 is 1, the individual verification test 201 is used in the system verification test. In this case, the get_addr command 209 of the individual verification test 201 activates the get_addr command 218 in the utility 206. Similarly, a CPU command of rdW (of 2111) is stored in rdW in the utility 206.
(220) is started.

That is, an instruction for allocating an available memory address which is started from the individual verification test 201
get_addr command 210 and read instruction rd to CPU
The W command 211 has a different program to be started depending on whether the individual verification environment file 203 or the system verification environment file 204 is selected, that is, whether to execute the individual verification or the system verification.

At the time of system verification, the operation 219 of the available memory address of the utility 206 is performed by
By distributing exclusively for each test 102-104,
Even if the tests 102 to 104 are started at the same time as the system verification, the collision of the used memory space is avoided. Also C
The arbitration control 222, 225 of the PU command is
By allocating exclusively for each of 2 to 104, arbitration is performed even when CPU commands of tests 102 to 104 are simultaneously activated during system verification. CP during system verification
In the program 207 for arbitrating U commands, C
After detecting the request of the PU command at 226 and arbitrating the CPU command, the CPU command is accepted at 227. Further, the release of the request for the CPU command is detected at 226, and the accepted CPU command is released at 228.

FIG. 3 shows a description example of a system verification test. 301 is a link to the test for individual verification, 302 is an instance of the test for individual verification, 303
Is a simultaneous start instruction, and 304 is a test task for system verification.

The individual verification tests 304 can be activated by instantiating the individual verification tests linked by the include instruction 301 at 302. 30
In response to the simultaneous activation instruction 3, the individual verification tests are simultaneously activated. However, at the start of the individual verification test 304, the system_availab of the selected individual verification test
By evaluating le, the individual verification test that cannot be used in the system verification is not used.

The above processing will be further described with reference to the flowchart of FIG. FIG. 4 is a flowchart illustrating the procedure of the logic verification process according to the first embodiment.

First, when the individual verification test is selected as the type of the logic verification, step S11 to step S11 are executed.
Proceeding to 12, a test for individual verification of the peripheral circuit to be verified is selected. For example, a test 201 for individual verification
Is selected.

Subsequently, in step 13, the utility 205 for individual verification is selected based on the environment file 202 and the environment setting file 203. As a result, when a command to be executed is specified from the test 201 for individual verification, the processing described in the utility 205 is executed. In step S14, an address assignment command (address assignment for individual verification) is executed, and in step S15, individual verification is executed.

On the other hand, when the system verification is designated, the process proceeds from step S11 to step S16, and a usable individual verification test is selected from a plurality of individual verification tests. Whether each individual verification test can be used for system verification is determined by sy
It can be determined by the value of stem_available209. Then, in step S17, a utility for system verification is linked to each individual verification test. For example, the individual verification test 201 includes a system verification utility 2
06 is selected. As a result, the test 20 for individual verification
When a command to be executed is specified from step 1, the process described in the utility 206 is executed.

In step S18, an address assignment command is executed (address assignment (exclusive assignment) for system verification is performed).
The individual verification is performed while arbitrating the commands according to.

As described above, according to the first embodiment,
The description of the test 201 for individual verification can be directly used for system verification.

That is, according to the above embodiment, since the test described for individual verification is used as a test for system verification, there is no need to write a new individual verification test for system verification, and the efficiency is improved. Is effective.

The present invention can be applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), but can be applied to a single device (for example, a copier, a facsimile). Device).

Further, an object of the present invention is to supply a storage medium (or a recording medium) in which a program code of software for realizing the functions of the above-described embodiments is recorded to a system or an apparatus, and to provide a computer (a computer) of the system or the apparatus. It is needless to say that the present invention can also be achieved by a CPU or an MPU) reading and executing the program code stored in the storage medium. In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. Also,
When the computer executes the readout program code, not only the functions of the above-described embodiments are realized, but also the operating system (OS) running on the computer based on the instructions of the program code.
It goes without saying that a case where the functions of the above-described embodiments are implemented by performing some or all of the actual processing, and the processing performs the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, the program code is read based on the instruction of the program code. Needless to say, the CPU included in the function expansion card or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0041]

As described above, according to the present invention,
Tests for individual verification can be used in system verification, and highly accurate system verification can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration for performing logic verification of a system LSI according to a first embodiment.

FIG. 2 is a diagram illustrating a description example of a test for logic verification of a system LSI according to the first embodiment;

FIG. 3 is a diagram showing a description example of a system verification test according to the first embodiment;

FIG. 4 is a flowchart illustrating a procedure of a logic verification process according to the first embodiment.

Claims (9)

[Claims] 1. An apparatus for performing a logic verification process on an integrated circuit, comprising: a plurality of individual verification test descriptions corresponding to a plurality of peripheral circuits included in the integrated circuit; and simultaneously operating the plurality of peripheral circuits. A system verification test description for performing a logical verification, and for each of the plurality of individual verification tests, an individual verification execution description that describes the execution content of the command described in the individual verification test description at the time of individual verification, Storage means for storing a system verification execution description describing the execution contents of the command described in the individual verification test description at the time of system verification; and individual verification corresponding to a peripheral circuit to be verified in the execution of the individual verification test. An individual verification means for executing a test description in accordance with an execution description for individual verification corresponding to the individual verification test description; A system verification unit for executing a plurality of individual verification test descriptions specified by the system verification test description in accordance with a system verification execution description corresponding to each of the individual verification test descriptions. . 2. The logic verification device for an integrated circuit according to claim 1, wherein the execution description for individual verification and the execution description for system verification include an address assignment command. 3. The execution description for individual verification and the execution description for system verification include a command that requires arbitration of a bus in an integrated circuit, and the execution description for system verification includes a description that requests arbitration of a bus. 3. The method according to claim 1, wherein
3. The logic verification device for an integrated circuit according to claim 1. 4. The logic verification for an integrated circuit according to claim 1, wherein the description of the system verification test includes a description for selectively executing some of the plurality of individual verification tests at the same time. apparatus. 5. A method for performing a logic verification process on an integrated circuit, comprising: a plurality of individual verification test descriptions corresponding to a plurality of peripheral circuits included in the integrated circuit; and simultaneously operating the plurality of peripheral circuits. A system verification test description for performing a logical verification, and for each of the plurality of individual verification tests, an individual verification execution description that describes the execution content of the command described in the individual verification test description at the time of individual verification, A system verification execution description that describes the execution contents of the command described in the individual verification test description at the time of system verification is stored. In the execution of the individual verification test, the individual verification test description corresponding to the peripheral circuit to be verified is stored. An individual verification step executed in accordance with an individual verification execution description corresponding to the individual verification test description; A system verification step of executing a plurality of individual verification test descriptions specified by the test description in accordance with a system verification execution description corresponding to each of the individual verification test descriptions. 6. The logic verification method for an integrated circuit according to claim 5, wherein the execution description for individual verification and the execution description for system verification include an address assignment command. 7. The execution description for individual verification and the execution description for system verification include a command that requires arbitration of a bus in an integrated circuit, and the execution description for system verification includes a description that requests arbitration of a bus. 7. The method according to claim 5, wherein
3. The logic verification method for an integrated circuit according to claim 1. 8. The logic verification for an integrated circuit according to claim 5, wherein the description of the system verification test includes a description for selectively executing some of the plurality of individual verification tests at the same time. Method. 9. A storage medium for storing a control program for realizing a method according to claim 5 by a computer.