JP2002055030A - Method for analyzing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that conventionally a general method for analyzing the cross section of a microchip by observing the microchip subjected to FIB processing or cross-sectional polishing of resin seal, using an electron microscope that general observation of the entire surface of the chip is difficult in case of FIB processing and preparation of a sample is laborious in case of cross section polishing. SOLUTION: A groove of observation chip size is made in a silicon substrate, and an observation chip is bonded therein through eutectoid or soldering and the like. The chip can be stably bonded accurately to the substrate and cross-sectional polishing can be effected. Since the position can be confirmed easily at polishing, general observation of the entire surface of a microchip can be performed easily and stably, in the method for analyzing a semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for analyzing a semiconductor device, and more particularly to a method for analyzing a semiconductor device in which a microchip can be easily observed by polishing a cross section.

[0002]

2. Description of the Related Art As a cross-sectional observation of a micro chip having a chip size of 2 mm square or less, a method of making a hole in a corresponding portion by FIB (Fine Ion Beam) processing and observing it with an electron microscope, or a method of mounting a chip on a glass substrate or the like. Glued,
A method in which a cross section is polished and observed with an electron microscope is generally used.

[0003] At present, FIB processing analysis is the mainstream. In this method, a hole is formed in a relevant portion using an ion beam focused to a diameter of about 1 μm or less, and a cross-sectional state is obtained as an inclined image by an electron microscope. This is the method of analysis.
However, in this method, the analysis is performed in a limited area, and it is almost impossible to observe the entire surface of the chip at once.

Therefore, in the case of simultaneous observation of the entire surface of the chip, a method is employed in which a chip adhered to a glass substrate or the like is polished in cross section and observed with an electron microscope. This method involves bonding a chip to a flat glass substrate or the like, sealing the chip with a resin, and performing polishing observation. It takes a lot of trouble to adjust the position of the chip during bonding.

[0005]

First, in FIB processing analysis, observation is performed by making a minute hole using a focused ion beam, so that it is difficult to observe the entire chip at one time. After bonding, a method of polishing the cross section is used, but it takes time and effort to prepare a sample such as adjusting the position when bonding the chip to a flat glass substrate, and there is a problem that it is difficult to confirm the position at the time of polishing. .

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and comprises a step of forming a silicon substrate for cross-sectional analysis and forming a groove having a size of an observation chip size in the silicon substrate. A step of depositing a metal on a substrate and bonding a chip for observation to the silicon substrate to produce a sample for cross-sectional analysis. It is possible to provide a method of analyzing a semiconductor device that can be easily adjusted.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An analysis method according to an embodiment of the present invention will be described in detail with reference to FIGS.

The cross-sectional structure analysis of the microchip is performed by forming a silicon substrate 1 for cross-sectional analysis, forming a groove 2 having the size of a chip for observation on the silicon substrate 1, and depositing a metal 4 on the silicon substrate 1. Then, the method comprises the steps of bonding the observation chip 5 to the silicon substrate 1 to produce a cross-sectional analysis sample, and polishing the cross-sectional analysis sample.

FIGS. 1 to 3 show the features of the present invention.
A first step, a step of forming a silicon substrate for section analysis and forming a groove having a size of an observation chip size in the silicon substrate, is shown.

FIG. 1 shows a case where the pattern arrangement of the observation chip is perpendicular or parallel to the side of the chip. In this case, the groove 2 is formed such that the sides of the pattern are parallel to the OF (Orientation Flat) 3 of the silicon substrate 1.

FIG. 2 shows a case where the pattern arrangement of the observation chip is on a diagonal line of the chip. In this case, the groove 2 is formed such that the sides of the pattern are inclined by 45 degrees with respect to the OF3 of the silicon substrate 1.

In either case, it is preferable to use the plane orientation <100> so that the silicon substrate 1 can be easily cut out.

FIG. 3 is a sectional view taken along line AA of FIG. 1 or a sectional view taken along line BB of FIG. Groove 2 is large enough to set the observation tip (0.
35 mm square to 2 mm square). The depth is 100μ
m to 300 μm, the depth may be such that the observation chip is hidden by half or more, and may be deeper than the thickness of the observation chip.

By forming the deep groove 2, when the observation chip is set, the periphery of the chip is covered with the silicon substrate 1, so that stable cross section polishing can be performed.

FIGS. 4 to 7 show a second step of the present invention, in which a metal is vapor-deposited on a silicon substrate, an observation chip is bonded to the silicon substrate, and a sample for section analysis is manufactured.

A metal 4 such as Au / Ti is deposited on the bottom surface of the groove 2 of the silicon substrate 1 and is adjusted to the size of a section polishing machine.
The silicon substrate 1 is cut out to a size of about 13 × 15 mm.

FIG. 4 is cut out from the silicon substrate 1 in FIG. 1, and FIG. 5 is cut out from the silicon substrate 1 in FIG.

FIG. 6 is a sectional view taken along line CC of FIG. 4 or a sectional view taken along line DD of FIG. The observation chip 5 is taken out of the package and set in the groove 2. In this state, since the back surface of the observation chip 5 is made of metal, it can be securely bonded to the metal 4 deposited on the bottom surface of the groove 2 by eutectic or solder before cutting out the silicon substrate 1. For example, it is heated and bonded on a hot plate of about 360 to 400 ° C. for Au-Si eutectic bonding and about 200 ° C. for solder bonding, and used as a cross-sectional analysis sample.

Further, as shown in FIG. 7, the observation chip 5 adhered to the silicon substrate 1 is sealed with an epoxy resin-based transparent adhesive 6, and a glass cover 7 is adhered to the upper surface to obtain a cross-sectional analysis sample. It may be.

Next, the third step of the present invention, that is, the step of polishing the cross section of a sample for cross section analysis will be described. The completed cross-sectional analysis sample is polished in cross-section, and the entire surface of the observation chip is analyzed in batch. At this time, since the surface of the observation chip can be visually observed, the position to be observed can be easily confirmed using a metal microscope or the like.

The feature of the present invention resides in that a groove 2 is formed in a silicon substrate 1 according to the size of an observation chip, and an observation chip 5 is bonded to the groove 2. As a result, firstly, it is only necessary to dispose it in the groove 2 corresponding to the observation chip 5, so that the observation chip 5 can be easily adhered to the silicon substrate 1 in an accurate direction.

Second, the need for sealing with resin is eliminated. Further, even when sealing is performed with the transparent adhesive 6 and the glass cover 7, the observation chip 5 is accommodated in the groove 2 and adhered, so that the amount of sealing resin can be significantly reduced as compared with the conventional case.

Third, by vapor-depositing a metal 4 such as Au / Ti in the groove 2, the observation chip 5 can be securely bonded by eutectic or solder of the metal.

Fourth, since the periphery of the observation chip 5 is covered with silicon, stable cross section polishing can be performed.

Fifth, since the surface of the observation chip 5 can be visually checked, the position can be easily confirmed at the time of polishing.

[0026]

According to the analysis method of the present invention, first, the groove 2 is provided in the silicon substrate 1 so that the silicon substrate 1
And the observation chip 5 can be easily bonded in the correct direction.

Second, the need for sealing with resin is eliminated. Further, even when sealing is performed with the transparent adhesive 6 and the glass cover 7, the observation chip 5 is accommodated in the groove 2 and adhered, so that the amount of sealing resin can be significantly reduced as compared with the conventional case.

Third, by vapor-depositing a metal 4 such as Au / Ti in the groove 2, the observation chip 5 can be securely bonded with a metal eutectic or solder.

Fourth, since the periphery of the observation chip 5 is covered with silicon, stable cross section polishing can be performed.

Fifth, since the surface of the observation chip 5 can be visually checked, the position can be easily confirmed at the time of polishing.

[Brief description of the drawings]

FIG. 1 is a top view illustrating a method for analyzing a semiconductor device according to the present invention.

FIG. 2 is a top view illustrating a method for analyzing a semiconductor device according to the present invention.

FIG. 3 is a sectional view illustrating a method for analyzing a semiconductor device according to the present invention.

FIG. 4 is a top view illustrating a method for analyzing a semiconductor device according to the present invention.

FIG. 5 is a top view illustrating a method for analyzing a semiconductor device according to the present invention.

FIG. 6 is a sectional view illustrating a method for analyzing a semiconductor device according to the present invention.

FIG. 7 is a sectional view illustrating a method for analyzing a semiconductor device according to the present invention.

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Claims (3)

[Claims] 1. A step of forming a silicon substrate for cross-sectional analysis, forming a groove having a size of an observation chip size in the silicon substrate, and depositing a metal on the silicon substrate to form an observation chip on the silicon substrate. Manufacturing a cross-sectional analysis sample by bonding to a semiconductor device. 2. The method of analyzing a semiconductor device according to claim 1, wherein the silicon substrate and the observation chip are sealed with a transparent adhesive and the upper surface is covered with a transparent substrate. 3. The method for analyzing a semiconductor device according to claim 1, wherein the sample for section analysis is polished in section.