JP2002050743A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, with which a power source is separated inside the semiconductor device and latch-up will not occur, even if there is a slight time difference in the rise of power supplied from the outside. SOLUTION: This device is provided with plural power lines 71, 73, 74 and 75; external power supply pins 60, 61, 62 and 63 provided corresponding to the respective plural power lines; plural internal circuits 41-54, 56 and 58 to be respectively operated by power supplied from the plural power lines; a first switching circuit, which is provided between at least one pair of plural power lines; and a power source control circuit 59 for turning the first switch circuit into a connected state, before supplying an initializing signal from the outside and for turning the first switching circuit into non-connected state, after supplying the initializing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a plurality of separated power lines, and each of which is separately supplied with power from the outside.

[0002]

2. Description of the Related Art A semiconductor device has a power supply pin for supplying power from the outside. At least one set of power pins is required, one of which is typically a ground (VSS) pin, which also serves as a signal ground. When the external power supply has a plurality of different voltages, it is needless to say that a plurality of sets of power supply pins are required for each external power supply. In this case, a ground pin may be separately provided for each external power supply, but since the ground level is usually common,
In some cases, one power supply pin is provided for each external power supply with a common ground pin. In any case, when a plurality of power supplies having different voltages are supplied, power supply lines corresponding to the respective power supplies are formed inside the semiconductor device.

In some cases, a plurality of power pins are provided even at the same voltage. This may be performed simply to increase the power supply capability, but may be performed to separate the power supply for each circuit element inside the semiconductor device. For example, when the load connected to the output circuit is large, a large current is consumed in the output circuit, noise is generated in the power supply of the semiconductor device, and adversely affects other circuit parts via the power supply line. In order to prevent such adverse effects, the power supply of the output circuit is separated from other circuit parts. In this case, a power supply line of the output circuit is separated from a power supply line of another circuit portion, and power supply pins are separately provided. Further, as described later, the amplitude of the output signal is reduced, but in this case, the input circuit needs to accurately capture the signal having the small amplitude. Therefore, the power supply of the input circuit is separated from the power supply of another circuit to prevent the noise of the other circuit from affecting the input circuit via the power supply line. When the power supply of the same voltage is separated, when the ground wiring is also separated,
The ground wiring may be shared. The present invention is applicable to both cases where the ground wiring is separated and shared. In the following description, the ground wiring is not shown and the description is omitted for the sake of simplicity.

In recent years, dynamic random access memories (DRAMs) have been improved in speed, and in order to accurately synchronize the input and output of data signals with a clock signal, a digital lock loop (DLL) circuit is used. Adjustment of the input / output of the data signal with respect to the clock signal is performed. This DLL circuit has a problem that the operation accuracy is likely to be reduced due to the influence of noise and power supply fluctuation. Therefore, the power supply of the DLL circuit is separated from the power supply of other circuits, and noise and power supply fluctuations of the other circuits are reduced via the power supply line.
It is necessary not to affect the L circuit.

Further, in the output circuit, if the power supply voltage is kept high, the consumption current due to the data output current increases sharply and the amplitude is large, so that it is becoming difficult to cope with high-speed operation. Therefore, by using the output level lower than the power supply voltage of the semiconductor device, current consumption can be reduced and high-speed operation can be supported. In this case, the power supply voltage supplied to the output circuit needs to be lower than the power supply voltage of the semiconductor device. Further, as described above, it is desirable to prevent the noise generated in the output circuit from affecting other circuits. The power supply for the output circuit is separated from the power supply for other circuits.

In addition, a DRAM requires a stable reference voltage between a power supply voltage and a ground level for determining a logical value of a data signal. Such a reference voltage is
In some cases, it is generated inside the semiconductor device, while in other cases it is supplied from outside. From the above situation, DRAM
In the chip, various power supply pins such as a power supply pin for supplying a normal power supply voltage VDD, a power supply pin for an output circuit, a power supply pin for a DLL circuit, and a power supply pin for a reference voltage VREF have been added.

FIG. 1 shows a power supply line of such a DRAM chip. As shown, the DRAM chip 11
Is provided with an output circuit 13, a DLL circuit 14, and other normal (normal) circuits 12. The normal power supply pins 15 and 16 supply the normal power supply VDD and the reference power supply VREF to the normal circuit 12, respectively. The circuit 13 is supplied with an output circuit power supply VDDQ from a power supply pin 17 and outputs a DLL signal.
The circuit 14 has a power supply pin 18 connected to a power supply VDD for a DLL circuit.
L is supplied. For example, the normal power supply voltages VDD and DL
The voltage VDDL of the power supply for the L circuit is 2.5 V, the voltage VDDQ of the power supply for the output circuit is initially 2.5 V, and then 1.
8V, and the voltage VREF of the reference power supply is 0V and 2.5V.
A suitable voltage between V.

In some cases, the external power supply to the power supply pins of the same voltage, for example, the power supply pins 15 and 18 is common, but in order to reduce the influence of noise via the external power supply, the external power supply is also used. Desirably separate and separate power supplies.

[0009]

When starting the power supply to the power supply pins connected to the plurality of power supply lines separated in the semiconductor device as described above, the specification of the DRAM, etc.
It is required that power supply to each power supply pin be started at the same time, so that there is no time difference between the start of power supply and the controller side. However, the above requirements are not always satisfied, and the power supply may be started with a time difference between the power supplies.

In the above-described semiconductor device, a power supply line is separately provided for each power supply, and necessary power is supplied to each circuit element. High integration is being promoted in semiconductor devices,
In some cases, circuit elements driven by different power supplies are formed close to each other. FIG. 2 is a diagram showing an example in which circuit elements driven by two different power supplies are formed close to each other. Specifically, a CMOS type inverter driven by a normal power supply VDD and an output circuit power supply VDDQ is placed close to each other. FIG. 4 is a diagram showing a chip cross section when formed. As shown in FIG. 2, two CMOS inverters are formed on a P-type substrate 21, the left side is a CMOS type inverter driven by a normal power supply VDD, and the right side is a C type inverter driven by an output circuit power supply VDDQ.
This is a MOS type inverter, and the two inverters have the same structure. That is, two N-type wells 22 and 23 are provided on a P-type substrate 21, P-type regions 27 and 28 and 34 and 35 are respectively formed therein, and gate electrodes 29 and 36 are formed therebetween, respectively. A channel transistor is formed. The N-type regions 30 and 37 are N-type regions for setting the N-type wells 22 and 23 to a high potential. Also, the N-type regions 24, 25 and 31 are formed on the P-type substrate 21.
And 32 are formed, and gate electrodes 26 and 3 are interposed therebetween.
3 are formed, and an N-channel transistor is formed. N-type regions 24 and 31 are connected to ground power supply VSS, P-type region 28 and N-type region 30 are connected to normal power supply VDD, and P-type region 35 and N-type region 37 are connected to output circuit power supply VDDQ. . An input signal Vin is applied to the gates 26 and 29, and the N-type region 25 and the P-type region 27 are connected to each other to obtain an inverter output Vout. Similarly, an input signal VinQ is applied to the gates 33 and 36, and the N-type region 32 and the P-type region 34 are connected to each other to obtain an inverter output VoutQ. Latch-up is a major problem in CMOS circuits, and measures are taken to prevent latch-up from occurring under normal use conditions.

As described above, the power supply supplied from the outside is designed on the assumption that the power supply rises at the same time. When the power supply rises with a time difference, there is a problem that the possibility of occurrence of latch-up increases. Hereinafter, this problem will be described. P-type region 28, N-well 22, P-type substrate 2
The 1 and N wells 23 form a PNPN type three terminal device (thyristor). Two power supplies VDD and VDDQ
This device does not operate if both rise at the same time. For example, if the normal power supply VDD rises first, the N-well 22 goes to VDD and the P-type substrate 21 goes to ground level. At this time, the N-type region 37, that is, the N-well 23 is in a floating state.
The NPN transistor formed by the well 23 is turned on, the thyristor is turned on, and latch-up occurs. Thus, if there is a time difference between the rises of the two power supplies, there is a problem that the possibility of occurrence of latch-up increases.

In order to avoid such a problem, if the power supply lines have the same voltage, the power supply lines may be connected to each other with a high-resistance resistance element to provide an electrical connection. However, as described above, the reason why the power supply line is separated is to prevent noise generated on one side from being transmitted to the other via the power supply line, and to transmit noise even in a high-resistance resistor element. Not preferred.

If it is desired to provide a potential difference between the voltages supplied to the two power supply lines, it is not preferable to provide the above-described resistance element, since current constantly flows and current consumption increases. Therefore, control has been performed so far on the power supply side so as not to cause a time difference in the rise between a plurality of power supplies as described above. However, there is a problem that it is complicated to start power supply in such a manner. Also,
If the semiconductor device is used without satisfying the above requirements, latch-up occurs and the semiconductor element is destroyed.

Therefore, there has been a demand for a semiconductor element in which the power supply is separated inside the semiconductor device and the latch-up does not occur even if there is a slight time difference between the rise of the power supply supplied from the outside. The present invention is directed to answering such a need.

[0015]

In order to achieve the above object, a semiconductor device according to the present invention is provided with a circuit which is in a connected state immediately after the start of supply of power and then is in a disconnected state between separated power lines. . The control of this circuit uses an initialization signal supplied from outside the semiconductor device.

That is, the semiconductor device of the present invention has a plurality of power supply lines, external power supply pins provided corresponding to each of the plurality of power supply lines, and a plurality of power supply lines respectively operated by the plurality of power supply lines. An internal circuit, and further includes a first switch circuit provided between at least one pair of the plurality of power supply lines, wherein the first switch circuit is connected before an external initialization signal is supplied. And an inter-power supply control circuit that disconnects the first switch circuit after the initialization signal is supplied.

According to the present invention, the two separated power lines are connected immediately after the start of power supply by the inter-power supply control circuit. Are not in a floating state, and an increase in the possibility of occurrence of latch-up can be prevented.
Also, after the two power supplies are turned on and the initialization signal is supplied from the outside, the control circuit between the power supplies is disconnected, so that the two power supply lines are separated, and noise or the like causes the power supply lines to be disconnected. Can be prevented.

If there is a voltage difference between the power supply voltages supplied to the two power supply lines, the inter-power supply control circuit sets the connection point between the two power supply lines connected to the first power supply line of the plurality of power supply lines. A second terminal and a second terminal connected in series with each other for connecting both ends of the resistor and the two resistors to a second power line and a third power line having different set potentials from the first power line, respectively. A connection stop signal for setting the third switch circuit and the second and third switch circuits to a connection state before the initialization signal is supplied and a disconnection signal for disconnecting the second and third switch circuits after the initialization signal is supplied to the second switch circuit. And a connection stop signal generation circuit generated for the third switch circuit.

In a DRAM, a chip reset command is input after the power is turned on, and it is desirable to use the chip reset command as the initial or instruction signal. In that case, the semiconductor device
A command determination circuit for generating a reset signal in response to a chip reset command is provided, and the control circuit between power supplies controls the first switch circuit in response to the reset signal.

The semiconductor device is a dynamic random
In the case of an access memory (DRAM), as shown in FIG. 1, the plurality of power supply lines include a power supply line for a data output circuit power supply line, a power supply line for a DLL circuit, and a reference power supply path. And power supply lines to other circuits.

[0021]

FIG. 3 is a diagram showing a DRA according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating an overall configuration of M. The configuration of a DRAM is widely known. Here, a schematic configuration will be described, and a detailed description will be omitted. Reference numeral 51 denotes a cell matrix in which storage cells each including one transistor and one capacitor are arranged in a matrix, and has a bank configuration. The gate of the transistor in each memory cell is connected to a word line provided for each row, and the source of the transistor is connected to a bit line provided for each column. In a DRAM, a write operation of writing a predetermined charge to a storage cell corresponding to an address signal input from the outside, a read operation of reading a charge stored in the storage cell, and a charge of the storage cell are gradually discharged. A refresh operation for returning the state to a state immediately after writing, an operation for determining an initial state, and the like are performed.

In order to perform such an operation, there is a circuit as shown in FIG. The DRAM shown in FIG. 3 operates in synchronization with a clock CLK supplied from the outside.
M, the clock buffer 41 receives the clock CLK, generates an internal clock CK, and supplies it to the inside of the device.
From the outside, in addition to the clock signal CLK, a control signal, an address signal indicating the position of a memory cell to be accessed, and write data Din are input, and received by the control signal latch 42, the address buffer 43, and the data input buffer 57. Also, the read output data Dout
Is output from the data output buffer 56 to the outside. Therefore, the data output buffer 56 corresponds to the output circuit 13 in FIG.

There are several control signals such as RAS and CAS, and the operation is instructed by combining them. The control signal fetched by the control signal latch 42 is decoded by the command decoder 44, and a signal designating the operation content is given to the control circuit, and is also supplied to the refresh counter / mode register 47 to reduce the input / output latency. An instruction signal is generated and supplied to the input data converter 55 and the output data converter 54. As described later, since a chip reset command is instructed by a combination of control signals, the command decoder 44 identifies the chip reset command and generates a reset signal RSET.

The input address signal is fetched by an address latch 45 and supplied to a decoder 49. The decoder 49 selectively activates a word line selection circuit in the core circuit 50 according to a row address, and the word line selection circuit drives a word line of a row to be accessed. The decoder 49 selectively activates a bit line selection circuit in the core circuit 50 according to the column address, and the bit line selection circuit activates a sense amplifier connected to a bit line of a column to be accessed. Actually, the decoder 49 is composed of a plurality of stages including a bank decoder, a predecoder and a word decoder. Reference numeral 52 indicates a sense amplifier row.

In order to store data in the storage cell, the write data Din input to the data input buffer 57 is determined by an input data converter, and R / R is determined according to the determination result.
The W buffer 53 is set to a state corresponding to the input data. Then, the sense amplifier to which the storage cell to be accessed according to the address signal is connected is in a state corresponding to the state of the R / W buffer 53, and the bit line is in a state corresponding to the input data. At the same time, the word line to which the storage cell to be accessed according to the address signal is connected is activated, the transistor of the storage cell is turned on, and the capacitance becomes the state corresponding to the state of the bit line. To read data from the storage cell, the word line connected to the storage cell to be accessed is activated, and the bit line is brought into a state corresponding to the stored data. This is amplified by a sense amplifier and further accessed. The output of the sense amplifier to which the storage cell is connected is selected and read out to the R / W buffer 53. This data is output to the output data converter 54, and the data output buffer 5
6 to the outside. The control circuit 48 generates a signal for controlling the above series of operations and supplies the signal to each unit.

The DLL circuit 58 is a circuit in which a number of delay elements are connected in series, and is a circuit that generates a signal having a predetermined phase relationship with the external clock CLK by adjusting the amount of delay. By controlling the output timing of the output data converter 54 with the DLL clock generated by this circuit, it is possible to accurately synchronize the output data Dout with the external clock CLK. Also,
The input data Din is also synchronized with the external clock CLK, and it is necessary to accurately synchronize the input data Din with the external clock CLK.
The DLL clock is also used to acquire n. However,
Generally, a write cycle is longer than a read cycle, and is not necessary when there is enough timing.

The above is an explanation of the configuration and operation of a general DRAM. In the above configuration, the data output buffer 5
6 is supplied with an output circuit power supply VDDQ externally supplied to the power supply pin 62, and the DLL circuit 58 is supplied with the power supply pin 6.
3, a DLL circuit power supply VDDL supplied to
The other circuit parts are supplied with the normal power supply VDD supplied to the power supply pin 60. In the DRAM of the first embodiment, the reference power supply VREF is supplied to the power supply pin 61 and supplied to the input circuit and the like. Of course, there are power pins for ground, but they are omitted here.

In the DRAM of the first embodiment, an inter-power supply control circuit 59 is provided as shown in FIG. The power supply control circuit 59 includes the four power supplies VDD, VDDQ,
In addition to VDDL and VREF, a reset signal RSET generated by the command decoder 44 is supplied. FIG.
FIG. 3 is a diagram illustrating a circuit configuration of a power supply control circuit 59; As shown in the figure, an N-channel transistor 77 is provided between a power supply line 71 of the normal power supply VDD and a power supply line 74 of the output circuit power supply VDDQ, and the power supply line 71 of the normal power supply VDD and the power supply of the DLL circuit power supply VDDL are provided. An N-channel transistor 78 is provided between the lines 75. Further, an N-channel transistor 80, a resistor 79, a resistor 81, and an N-channel transistor 82 are connected in series between a power supply line 71 of the normal power supply VDD and a power supply line 72 of the ground VSS. The point is the reference power supply VREF
Power supply line 73. Here, resistors 79 and 8
The resistance value of 1 is selected so that VDD is divided by a resistor so that the voltage at the connection point between the resistors 79 and 81 becomes substantially equal to VREF. The connection stop signal generation circuit 76 outputs a reset signal RS
A connection stop signal SVCON is generated in response to ET and applied to the gates of the N-channel transistors 77, 78, 80 and.

FIG. 5 is a diagram for explaining the operation of the control circuit 59 between power supplies. As shown in FIG. 5A, among the power supplies supplied from the outside, the normal power supply VDD rises as shown by a solid line, and the other power supplies VDDQ, VDDL, and VREF rise with a delay as shown by a broken line. .
However, since the connection stop signal SVCON rises with VDD as shown in (4) of FIG. 5, the N-channel transistors 77, 78, 80, and 82 are conducting, and VDD, VDDQ, VDDL inside the DRAM.
And VREF rise in the same manner as the external power supply VDD. Therefore, the possibility of occurrence of latch-up remains low.

After VDD, VDDQ, VDDL and VREF of the external power supply have all risen, a chip reset command is instructed by a control signal, and the command decoder 4
Reference numeral 4 identifies a chip reset command and generates a reset signal RSET as shown in FIG. In response, the connection stop signal generation circuit 76 outputs the connection stop signal SV
Since CON is set to the “low (L)” level, the N-channel transistors 77, 78, 80 and 82 are turned off, and VDD, VDDQ, VDDL and V
The power supply lines of REF are all separated. Since the operation is performed in this state, no noise is transmitted to other circuit portions via the power supply line.

In the above embodiment, VDD, VDD
The connection between DQ, VDDL and VREF is controlled, but the power supply to be connected may be arbitrarily combined as needed. Further, in the above-described embodiment, the connection is controlled between all the power supplies. However, the connection state may be controlled only between the power supplies in which latch-up is a problem. Further, in the above-described embodiment, an N-channel transistor is used as a switch provided between power supplies, but a P-channel transistor may be used.

[0032]

As described above, according to the present invention,
Even if there is a time difference between the power supplies when the power is turned on, the possibility of latch-up does not increase. In addition, at the time of actual operation, since each power supply is separated, noise is not transmitted between different power supply paths via the power supply line, and stable operation is possible.

[Brief description of the drawings]

FIG. 1 shows a semiconductor device (DRA) to which a plurality of power sources are supplied.
FIG. 3M is a diagram illustrating a configuration example of FIG.

FIG. 2 is a diagram illustrating an example in which circuit elements driven by two different power supplies are formed close to each other, and is a diagram illustrating a mechanism in which latch-up occurs due to a time difference between rises of power supplies.

FIG. 3 is a diagram showing an overall configuration of a DRAM according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a circuit configuration of an inter-power supply control circuit according to an embodiment.

FIG. 5 is a diagram illustrating an operation in the power supply control circuit according to the embodiment.

[Explanation of symbols]

 41 to 55: a circuit that operates at VDD 56: a circuit that operates at VDDQ (data output buffer) 58: a circuit that operates at VDDL (DLL circuit) 59: a power supply control circuit 60 to 63: power supply pins 71, 73, 74, 75: power supply line 76: connection stop signal generation circuit

Continued on the front page (72) Inventor Kazuyuki Imai 5-7-1 Shiba, Minato-ku, Tokyo Inside NEC Corporation (72) Inventor Hisashi Ishikawa 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation F-term within the formula company (reference) 5B024 AA03 AA15 BA29 CA07 5F038 AV06 BH18 CD02 CD03 DF05 DF06 EZ20 5F048 AA03 AB01 AB04 AB07 AB10 AC01 AC03 AC10 BA01 BB05 BE03 BE09

Claims (4)

[Claims] A plurality of power supply lines; an external power supply pin provided corresponding to each of the plurality of power supply lines; and a plurality of internal circuits each operated by a power supply supplied from the plurality of power supply lines. A first switch circuit provided between at least one set of the plurality of power supply lines, wherein the switch circuit is connected before an external initialization signal is supplied, and the initialization signal is A semiconductor device comprising: an inter-power supply control circuit that disconnects the switch circuit after being supplied. 2. The power supply control circuit further comprises: two resistors whose connection points are connected to a first power supply line of the plurality of power supply lines; And second and third switch circuits connected in series with each other to connect to a second power supply line and a third power supply line having different set potentials, respectively. The connection stop signal for setting the switch circuit to a connection state before the initialization signal is supplied, and to a disconnection state after the initialization signal is supplied, to the second circuit.
2. The semiconductor device according to claim 1, further comprising a connection stop signal generation circuit generated for the third switch circuit. 3. The initialization signal supplied from outside is:
A command reset circuit that generates a reset signal in response to the chip reset command, wherein the inter-power supply control circuit controls the first switch circuit in response to the reset signal. 3. The semiconductor device according to claim 1, wherein: 4. The semiconductor device is a dynamic random access memory (DRAM), wherein the plurality of power lines are a power line for a data output circuit, a power line for a DLL circuit, and a reference power source. 4. The semiconductor device according to claim 1, comprising at least one of the lines.