JP2002050664A - Test structure for evaluating insulation film, and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a commonly usable test structure for evaluating an insulation film, even when the film under evaluation is comparatively thick or of a very thin film region. SOLUTION: A plurality of electrodes 2a-2j are formed on a silicon substrate 1. Insulation films 8a-8j under evaluation are formed between the electrodes 2a-2j and the substrate 1. A pad 3 for applying an evaluating voltage from outside is formed on the substrate 1, and the first ends of the electrodes 2a-2j are commonly connected to the pad 3 via diodes 6a-6j formed in the substrate 1 and a wiring 5 formed on the substrate 1. Pads 4a-4j for applying evaluating voltages from the outside are formed on the substrate 1. Second ends of the electrodes 2a-2j are connected to the pads 4a-4j via wirings 7a-7j formed on the substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test structure for evaluating an insulating film such as a TEG (Test Element Group) used in a reliability evaluation for evaluating the reliability of an insulating film such as a gate insulating film. And a method of manufacturing a semiconductor device using the test structure.

[0002]

2. Description of the Related Art Factors that lower the reliability of a gate insulating film are mainly caused by deterioration of the film quality of the gate insulating film itself (referred to as "factor" of the factor) and etching at the time of forming a gate electrode. Damage to the insulating film (referred to as a "gate edge component" as a factor) and the effect on the gate insulating film of stress generated at the boundary between the element formation region and the element isolation region (referred to as a "field edge component" as a factor) Can be considered.

In order to evaluate the reliability of such an insulating film such as a gate insulating film, a time-dependent dielectric breakdown (Time Depend Dielectric B)
An evaluation method called "reakdown: TDDB" is widely used. In a general TDDB, a TEG having a simple structure in which an insulating film is formed in a flat pattern on a silicon substrate and electrodes are formed on the insulating film is used. Such a TEG is a TEG containing only a so-called surface component.
Therefore, only the deterioration of the film quality of the insulating film can be evaluated.

Therefore, in order to evaluate the reliability in accordance with an actual device, a TEG having electrodes patterned by etching (eg, a TEG including a gate edge component together with a surface component) and an element isolation insulating film are formed. TEGs (TEGs including field edge components as well as surface components) have been used in TDDB.

In a TEG for evaluating an insulating film, it is desirable that the total area of the insulating film to be evaluated or the total gate edge length and field edge length be longer than the actual device. This is because the larger the area or the longer the gate edge length or the field edge length, the easier it is to detect a defect in the insulating film. For this reason, in a general TDDB, an evaluation is often performed by forming a large-area insulating film on a silicon substrate and applying an evaluation stress to the large-area insulating film at a time.

However, as gate insulating films have become thinner in recent years, it has become impossible to perform evaluation by applying stress for evaluation to a large-area insulating film at a time. When the thickness of the insulating film is an extremely thin region of 3.0 nm or less, a direct tunneling current becomes dominant, so that a considerable leak current flows even before dielectric breakdown occurs in the insulating film in the TDDB. Therefore, if the evaluation stress is applied to the large-area insulating film at a time, the current flowing between the electrode and the silicon substrate via the insulating film increases, which hinders the normal failure determination of the insulating film. It is.

Therefore, in the conventional TDDB, different types of TEGs are used for the TDDB which evaluates a relatively thick insulating film and the TDDB which evaluates an insulating film in an extremely thin film region.
It has been used to distinguish them.

FIG. 13 is a top view showing the structure of a TEG 151 used in a TDDB for evaluating a relatively thick insulating film. The TEG 151 is a TEG that includes a gate edge component together with a surface component. On a p-type silicon substrate 101, a plurality of (here, ten) electrodes 102
a to 102j are formed in parallel with each other.
An insulating film to be evaluated is formed between the bottom surfaces of the electrodes 102a to 102j and the upper surface of the silicon substrate 101, but does not appear in FIG. On the upper surface of the silicon substrate 101, pads 103 for applying a voltage for evaluation from the outside are formed, and the electrodes 102a to 102j are connected to the silicon substrate 101.
Through the wiring 105 formed on the upper surface of the pad 10
3 are connected in common.

The evaluation voltage applied to the pad 103 from the outside is applied to the electrodes 102 a to 102 j via the wiring 105.
Is applied to As a result, stress for evaluation is applied to all the insulating films formed under the electrodes 102a to 102j at once.

FIG. 14 is a top view showing the structure of a TEG 152 used in a TDDB for evaluating an insulating film in an extremely thin film region. Like the TEG 151, the TEG 152 includes a TE including a surface component and a gate edge component.
G. On a p-type silicon substrate 101, a plurality of (here, ten) electrodes 102a to 102j are formed in parallel with each other. An insulating film to be evaluated is formed between the bottom surfaces of the electrodes 102a to 102j and the upper surface of the silicon substrate 101.
j and does not appear in FIG. Silicon substrate 101
A plurality of pads 104a to 104j for applying a voltage for evaluation from outside are formed on the upper surface of the silicon substrate 101. The electrodes 102a to 102j are connected to the wirings 107a to 107j formed on the upper surface of the silicon substrate 101. Are connected to the pads 104a to 104j, respectively.

For example, a voltage for evaluation applied from the outside to the pad 104a is applied to the electrode 102a via the wiring 107a.
Is applied to the insulating film formed under the electrode 102a. At this time, stress for evaluation is not applied to the insulating film formed under the other electrodes 102b to 102j by application of a voltage to the pad 104a.

[0012]

However, according to such a conventional TDDB, different types of TDDBs are used for evaluating a relatively thick insulating film and for evaluating an insulating film in an extremely thin film region. However, there is a problem that the use efficiency of the TEG is low and the cost increases.

The present invention has been made to solve such a problem, and is applicable to both cases where a relatively thick insulating film is to be evaluated and when an insulating film in an extremely thin region is to be evaluated. It is an object of the present invention to obtain a test structure for evaluating an insulating film which can be used for a semiconductor device and a method for manufacturing a semiconductor device using the test structure.

[0014]

Means for Solving the Problems Claim 1 of the present invention
The test structure for evaluating an insulating film described in 1 above includes a substrate, a plurality of first insulating films which are selectively formed on a main surface of the substrate, and a plurality of first insulating films to be evaluated, and a plurality of first insulating films. It comprises a plurality of conductors formed respectively, a first pad commonly connected to the plurality of conductors, and a plurality of second pads respectively connected to the plurality of conductors.

According to a second aspect of the present invention, there is provided a test structure for evaluating an insulating film according to the first aspect, wherein the first pad and the plurality of conductors are connected to each other. And a plurality of first connection means formed between the first connection means and turned on when a voltage is applied to the first pad and turned off when a voltage is applied to the second pad. It is a feature.

According to a third aspect of the present invention, the test structure for evaluating an insulating film is the test structure for evaluating an insulating film according to the second aspect, wherein the first connecting means is a diode. It is a feature.

According to a fourth aspect of the present invention, the test structure for evaluating an insulating film is the test structure for evaluating an insulating film according to the first aspect, wherein the plurality of conductors are two or more conductors. Are further divided into a plurality of groups each including: a plurality of third pads which are connected in common to two or more conductors belonging to the same group and are provided for each group. It is.

According to a fifth aspect of the present invention, there is provided a test structure for evaluating an insulating film according to the fourth aspect, wherein the first pad and the plurality of third pads are provided. And a plurality of first connection means which are formed between the first and second pads, respectively, become conductive when a voltage is applied to the first pad, and become non-conductive when a voltage is applied to the third pad. A first pad formed between the third pad and two or more conductors belonging to a group corresponding to the third pad;
Alternatively, the semiconductor device further includes a plurality of second connection units that become conductive when a voltage is applied to the third pad and become non-conductive when a voltage is applied to the second pad. is there.

According to a sixth aspect of the present invention, there is provided a test structure for evaluating an insulating film according to the fifth aspect, wherein the first and second connecting means are diodes. It is characterized by having.

According to a seventh aspect of the present invention, the test structure for evaluating an insulating film is the test structure for evaluating an insulating film according to any one of the first to sixth aspects, wherein the main surface of the substrate is provided. A second insulating film selectively formed therein, wherein the first insulating film is formed over the main surface of the substrate and over the second insulating film. is there.

The test structure for evaluating an insulating film according to claim 8 of the present invention is the test structure for evaluating an insulating film according to claim 7, wherein the second insulating film includes a plurality of conductors. Is a strip-shaped insulating film extending in a direction perpendicular to the direction in which.

According to a ninth aspect of the present invention, there is provided a test structure for evaluating an insulating film according to the seventh aspect, wherein the second insulating film includes a plurality of cutout portions. Characterized in that it is a planar insulating film having

According to a tenth aspect of the present invention, the test structure for evaluating an insulating film is the test structure for evaluating an insulating film according to the seventh aspect.
A semiconductor substrate, an element isolation insulating film selectively formed on a main surface of the semiconductor substrate, a gate insulating film selectively formed on a main surface of the semiconductor substrate, and a gate insulating film formed on the gate insulating film. A first insulating film, a conductor, used for evaluating a gate insulating film in a semiconductor device including the gate electrode;
And the pattern comprising the second insulating film is a gate insulating film,
It is characterized in that it has the same shape as a pattern composed of a gate electrode and an element isolation insulating film.

The test structure for evaluating an insulating film according to claim 11 of the present invention is the test structure for evaluating an insulating film according to any one of claims 1 to 10, wherein The semiconductor device further includes an impurity introduction region having a conductivity type opposite to the conductivity type of the substrate, which is formed in the main surface of the substrate between the bodies.

According to a twelfth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: (a) forming an insulating film by using the test structure for evaluating an insulating film according to any one of the first to eleventh aspects; And (b) forming a gate insulating film corresponding to the insulating film on the semiconductor substrate.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a top view showing the structure of TEG 51 according to Embodiment 1 of the present invention, and FIG. 2 is a cross-sectional view showing a cross-sectional structure related to a position along line X1 shown in FIG. The TEG 51 has electrodes 2a to 2j and insulating films 8a to 8j patterned by etching, and is a TEG including a surface component and a gate edge component. Referring to FIGS. 1 and 2, a plurality (here, 10)
The electrodes 2a to 2j are formed in parallel with each other. Insulating films 8a to 8j to be evaluated are formed between the bottom surfaces of the electrodes 2a to 2j and the upper surface of the silicon substrate 1, respectively. The insulating films 8a to 8j correspond to gate insulating films in an actual device. A pad 3 for applying a voltage for evaluation from outside is formed on the upper surface of the silicon substrate 1, and one end of each of the electrodes 2 a to 2 j is connected to a diode 6 formed in the silicon substrate 1.
a to 6 j and a wiring 5 formed on the upper surface of the silicon substrate 1. A ground voltage is applied to the silicon substrate 1 from the back side of the substrate.

Pads 4a to 4j for applying a voltage for evaluation from the outside are formed on the upper surface of the silicon substrate 1, and the other ends of the electrodes 2a to 2j are connected to the upper surface of the silicon substrate 1, respectively. Via the wirings 7a to 7j formed above,
The pads are connected to the pads 4a to 4j, respectively. In the upper surface of the silicon substrate 1, an STI (Shallow Trench Isola) for electrically isolating the pads 3, 4a to 4j, the diodes 6a to 6j, and the electrodes 2a to 2j is provided.
) is formed.

FIGS. 3 and 4 are sectional views showing the structures of the diodes 6a to 6j. Referring to FIG. 3, silicon substrate 1
A P-well 12 and an N-well 13 are formed adjacent to each other in the upper surface of the substrate to constitute a diode. The P well 12 is connected to the electrode 2 (reference numerals 2a to 2 in FIGS. 1 and 2) through the electrode 10 formed on the upper surface of the silicon substrate 1.
j). The N well 13 is connected to the wiring 5 via the electrode 11 formed on the upper surface of the silicon substrate 1. Further, a P well 14 is formed below the P well 12 and the N well 13 in order to prevent a current from flowing from the upper surface of the silicon substrate 1 to the bottom surface.
Below the P well 14, an N well 15 is formed.

Referring to FIG. 4, a P-well 16 and an N-well 17 are formed adjacent to each other on the upper surface of silicon substrate 1 to constitute a diode. P well 16
Is connected to the electrode 2 via the electrode 10 formed on the upper surface of the silicon substrate 1. The N well 17 is connected to the wiring 5 via the electrode 11 formed on the upper surface of the silicon substrate 1. In addition, a silicon oxide layer 18 is formed below the P well 12 and the N well 13 in order to prevent a current from flowing from the upper surface of the silicon substrate 1 to the bottom surface. The silicon oxide layer 18 can be formed by injecting oxygen partially into the silicon substrate 1 and oxidizing the silicon substrate 1 in that portion.

When a relatively thick insulating film is formed as the insulating films 8a to 8j to be evaluated, a voltage for evaluation is applied to the pad 3 from outside. Since it is assumed here that the conductivity type of the silicon substrate 1 is p-type,
A negative voltage is applied as a voltage for evaluation. Since this voltage is a forward bias voltage for the diodes 6a to 6j, the diodes 6a to 6j are turned on. As a result, the voltage applied to the pad 3 is commonly applied to the electrodes 2a to 2j via the wiring 5 and the diodes 6a to 6j. Thereby, the stress for evaluation is applied to all the insulating films 8a to 8j formed below the electrodes 2a to 2j at once.

On the other hand, when an insulating film in an extremely thin region is formed as the insulating films 8a to 8j, a negative voltage for evaluation is externally applied to the pads 4a to 4j. Pad 4
The voltages applied to a to 4j are applied to the electrodes 2a to 2j via the wirings 7a to 7j, respectively. As a result, the insulating films 8a to 8a formed below the electrodes 2a to 2j are formed.
8j are individually applied with stress for evaluation.

At this time, since a reverse bias voltage is applied to the diodes 6a to 6j, all the diodes 6a to 6j are turned off. Therefore, no current flows between the different electrodes 2a to 2j via the wiring 5. The diodes 6a to 6j
Need to have a reverse breakdown voltage higher than the evaluation voltage applied to the pads 4a to 4j.

After a stress for evaluation is continuously applied to the insulating films 8a to 8j for a certain period of time, a physically failed portion is detected by a light emission analyzer, an electron beam testing, or the like. Microscope (Scanning Electron Mi
The failure location is observed using croscopy (SEM) or the like.

FIG. 5 is a top view showing the structure of the wafer 28 on which the TEG is formed. Relatively thick insulating films 8a to 8j
Are alternately arranged with shots 29a in which the insulating films 8a to 8j in the ultra-thin regions are formed.

FIG. 6 is a top view showing another configuration of the wafer 28 on which the TEG is formed. In each shot 29, a thick film portion 30 in which relatively thick insulating films 8a to 8j are formed
a, and a thin film portion 30b in which the insulating films 8a to 8j in the extremely thin film region are formed.

As described above, the TEG 5 according to the first embodiment
1, the pads 3 commonly connected to the electrodes 2a to 2j and the pads 4a to 4e individually connected to the electrodes 2a to 2j
4j. Therefore, the insulating films 8a to 8e to be evaluated
When the film thickness of 8j is relatively large, a voltage for evaluation is applied to the pad 3 to apply a stress for evaluation to all the insulating films 8a to 8j formed under the electrodes 2a to 2j. Can be applied. On the other hand, the insulating film 8a
In the case where the thickness of each of the insulating films 8a to 8j is formed under the electrodes 2a to 2j by applying a voltage for evaluation to the pads 4a to 4j,
In addition, stress for evaluation can be individually applied.
That is, the TEG 51 having the same configuration can be used regardless of whether a relatively thick insulating film is to be evaluated or an insulating film in an extremely thin region is to be evaluated. Can be.

A plurality of diodes between the pad 3 and the electrodes 2a to 2j are in a conductive state when a voltage is applied to the pad 3 and are in a non-conductive state when a voltage is applied to the pads 4a to 4j. 6a to 6j are formed. Therefore, in the evaluation in the case where the thickness of the insulating films 8a to 8j is the thickness of the ultra-thin region, it is possible to prevent current from flowing mutually between the different electrodes 2a to 2j via the wiring 5, and It is possible to avoid hindrance to the failure determination of the film.

Embodiment 2 FIG. 7 is a top view showing the structure of TEG 52 according to Embodiment 2 of the present invention.
FIG. 8 is a cross-sectional view illustrating a cross-sectional structure related to a position along a line X2 illustrated in FIG. 7. Referring to FIG. 7, TEG 52 according to the second embodiment is based on TEG 51 according to the first embodiment shown in FIG. 1, and has electrodes 2a to 2j extending within the upper surface of silicon substrate 1. Further, strip-shaped element isolation insulating films 19v to 19z extending in a direction perpendicular to the direction are further formed.

Referring to FIG. 8, insulating film 8j is formed on the upper surface of silicon substrate 1 in a region where element isolation insulating films 19w to 19y are not formed (corresponding to an element forming region in an actual device). And element isolation insulating film 1
In a region where 9w to 19y are formed (corresponding to an element isolation region in an actual device), the element isolation insulating film 1
9w to 19y. In addition, the insulating film 8j of a portion formed on the element isolation insulating films 19w to 19y
Is thinner than the film thickness of the portion formed on the silicon substrate 1 because the insulating film formed by the thermal oxidation method easily grows on the silicon substrate, and the element isolation insulating film. It is because it is difficult to grow on.

As described above, the TEG 5 according to the second embodiment
According to 2, based on the TEG 51 according to the first embodiment, the element isolation insulating film 1 is formed on the upper surface of the silicon substrate 1.
9v-19z were further formed. As a result, a TEG including a field component as well as a plane component and a gate edge component can be obtained, and the stress generated at the boundary between the element formation region and the element isolation region is reduced by the insulating films 8a to 8j.
The TDDB can be performed in consideration of the influence on the TDDB.

Embodiment 3 FIG. 9 is a top view showing the structure of TEG 53 according to Embodiment 3 of the present invention. In the TEG 52 according to the second embodiment, the strip-shaped element isolation insulating films 19v to 19z extending in the direction perpendicular to the direction in which the electrodes 2a to 2j extend include field edge components. TEG was obtained. On the other hand, in the TEG 53 according to the third embodiment, instead of the element isolation insulating films 19v to 19z, the element isolation insulating film 21 having the same shape as the element isolation insulating film used in the actual device is used. 1 is formed in the upper surface.

In the third embodiment, in particular, a plurality of elliptical element forming regions (so-called staggered element forming regions) adjacent to each other in a diagonal direction are defined as the actual device in order to improve the degree of integration. A memory device in which an element isolation insulating film is formed is assumed. Therefore, TEG
Also in 53, an element isolation insulating film 21 that defines a so-called staggered elliptical element formation region 22 is formed in the upper surface of the silicon substrate 1. In other words, a planar element isolation insulating film 21 having a plurality of cutouts corresponding to element formation regions is formed in the upper surface of the silicon substrate 1. Further, the insulating films 8a to 8j and the electrodes 2a to 2j
Is formed in a predetermined shape on a predetermined position on the silicon substrate 1 and the element isolation insulating film 21 in correspondence with the shape and the formation position of the gate insulating film and the gate electrode in an actual device.

In other words, in the TEG 53, the insulating films 8a to 8j, the electrodes 2a to 2j, and the element isolation insulating films 21
Has the same shape as the pattern formed by the gate insulating film, the gate electrode, and the element isolation insulating film in an actual device.

As described above, the TEG according to the third embodiment
According to 53, the insulating films 8a to 8j, the electrodes 2a to 2j, and the element isolation insulating films 21 are formed in a predetermined pattern, reflecting the pattern in the actual device. Therefore, as compared with the TEG 52 according to the second embodiment, TDDB can be performed under conditions suitable for an actual device.

Embodiment 4 FIG. 10 is a top view showing the structure of TEG 54 according to Embodiment 4 of the present invention. The plurality of electrodes 2a to 2j are electrodes 2a and 2b belonging to the first group.
Electrodes 2c and 2d belonging to the second group, electrodes 2e and 2f belonging to the third group, and electrodes 2g and 2h belonging to the fourth group.
It is divided into electrodes 2i and 2j belonging to the fifth group.

Pads 23ab and 23c for applying a voltage for evaluation from outside are provided on the upper surface of the silicon substrate 1.
d, 23ef, 23gh, and 23ij are formed.
In the silicon substrate 1, diodes 6ab, 6c
d, 6ef, 6gh, and 6ij are formed. The diodes 6ab, 6cd, 6ef, 6gh, 6ij have the same structure as the structure shown in FIGS. The cathodes of the diodes 6ab, 6cd, 6ef, 6gh, and 6ij are commonly connected to the pad 3 via the wiring 5 formed on the silicon substrate 1, and the anodes are connected to the pads 23ab, 23cd, 23ef, 23gh. , 23ij
Connected to each other.

The cathodes of the diodes 6a and 6b are on the pad 23ab, the cathodes of the diodes 6c and 6d are on the pad 23cd, the cathodes of the diodes 6e and 6f are on the pad 23ef, and the cathodes of the diodes 6g and 6h are on the pad 23ab. At 23gh, the cathodes of the diodes 6i and 6j are commonly connected to the pad 23ij. Other structures of the TEG 54 according to the fourth embodiment are the same as those of the TEG 51 according to the first embodiment.

When a relatively thick insulating film (thickness T _ox 1) is formed as the insulating films 8a to 8j, a voltage for evaluation is applied to the pad 3 from outside. As described above, since the case where the conductivity type of the silicon substrate 1 is the p-type is assumed here, a negative voltage is applied as the evaluation voltage. This voltage is applied to the diodes 6ab, 6cd, 6
ef, 6gh, 6ij, 6a to 6j are forward-biased voltages, so that the diodes 6ab, 6cd, 6e
f, 6gh, 6ij, 6a to 6j are in a conductive state. As a result, the voltage applied to the pad 3 depends on the wiring 5, the diodes 6ab, 6cd, 6ef, 6gh, 6ij, the pads 23ab, 23cd, 23ef, 23gh, 23ij,
And are applied to the electrodes 2a to 2j in common through the diodes 6a to 6j. Thereby, the stress for evaluation is applied to all the insulating films 8a to 8j formed below the electrodes 2a to 2j at once.

Next, when an insulating film (thickness T _ox 2) in an extremely thin region is formed as the insulating films 8a to 8j, a negative voltage for evaluation is applied to the pads 4a to 4j from outside. Applied. The voltages applied to the pads 4a to 4j are applied to the electrodes 2a to 2j via the wirings 7a to 7j, respectively. As a result, stress for evaluation is applied to the insulating films 8a to 8j formed below the electrodes 2a to 2j, respectively.

At this time, the diodes 6ab, 6cd, 6
Since a reverse bias voltage is applied to ef, 6gh, 6ij, 6a to 6j, the diodes 6ab, 6
cd, 6ef, 6gh, 6ij, 6a to 6j are all in a non-conductive state. Therefore, no current flows between the different electrodes 2a to 2j.

Next, as the insulating films 8a to 8j, the film thickness T _ox
If 3 is an insulating film of _{T ox 2 <T ox 3 <} T ox 1 is formed, a negative voltage for evaluation, the pad 23a from the outside
b, 23cd, 23ef, 23gh, and 23ij. Since this voltage is a forward bias voltage for the diodes 6a to 6j, the diodes 6a to 6j are turned on. As a result, for example, the voltage applied to the pad 23a is applied to the electrodes 2a, 2d via the diodes 6a, 6b.
2b are commonly applied. Thereby, the electrodes 2a, 2b
The stress for evaluation is applied to the insulating films 8a and 8b formed under the substrate at once. Electrode 2c belonging to another group
The same applies to .about.2j.

On the other hand, at this time, the diodes 6ab, 6c
Since a reverse bias voltage is applied to d, 6ef, 6gh, and 6ij, the diodes 6ab, 6cd,
6ef, 6gh, and 6ij are all non-conductive.
Therefore, no current flows between the electrodes 2a to 2j belonging to different groups.

As described above, the TEG 5 according to the fourth embodiment
According to FIG. 4, in addition to the pads 3 commonly connected to all the electrodes 2a to 2j and the pads 4a to 4j individually connected to the electrodes 2a to 2j, the electrodes 2a to 2j belonging to the same group
2j commonly connected to pads 23ab, 23cd, 2
3ef, 23gh, and 23ij were provided. Therefore, TEG
In accordance with the thickness of the insulating films 8a to 8j formed on the pad 54, the pad 3 for the large area, the pad 23ab for the medium area,
A pad to which a voltage for evaluation is to be applied can be selected from among 23cd, 23ef, 23gh, 23ij and the small area pads 4a to 4j.

The pad 3 and the pads 23ab, 23c
d, 23ef, 23gh, and 23ij become conductive with respect to the voltage applied to the pad 3, and the pads 4a to
4j or pads 23ab, 23cd, 23ef, 23g
h, 23ij, a plurality of diodes 6ab, 6cd, 6ef, 6gh, and 6i that become non-conductive when voltage is applied to them.
j are formed, and pads 23ab and 23c
d, 23ef, 23gh, 23ij and the electrodes 2a to 2j, the pad 3 or the pads 23ab, 23cd, 2
A plurality of diodes 6a to 6j which are conductive when voltage is applied to 3ef, 23gh and 23ij and are nonconductive when voltage is applied to pads 4a to 4j are formed.

Therefore, in the evaluation where the thickness of the insulating films 8a to 8j is the thickness of the ultra-thin region, different electrodes 2
It is possible to prevent currents from flowing mutually between the electrodes 2a to 2j, and to evaluate the case where the thickness of the insulating films 8a to 8j is the above-mentioned T _ox 3, and to evaluate the electrodes 2a to 2j belonging to different groups.
It is possible to prevent currents from flowing between each other.

In the above description, each group includes two electrodes as an example. However, three or more electrodes may be included.

In the above description, the first embodiment is described.
Although the example in which the invention according to the fourth embodiment is applied based on the TEG 51 according to the fourth embodiment has been described, the invention according to the fourth embodiment is based on the TEGs 52 and 53 according to the second and third embodiments. It can also be applied.

Embodiment 5 FIG. FIG. 11 is a top view showing the structure of TEG 55 according to Embodiment 5 of the present invention, and FIG. 12 is a cross-sectional view showing a cross-sectional structure related to a position along line X3 shown in FIG. In the TEG 55 according to the fifth embodiment, the TEG 55 according to the first embodiment is used.
Instead of 51, diodes 24a to 24a having an anode connected to pad 3 and a cathode connected to electrodes 2a to 2j, respectively.
24j are formed. In addition, the electrodes 2 adjacent to each other
An n-type impurity introduction region 25 is formed in the upper surface of the silicon substrate 1 between a to 2j. Further, a pad 26 is formed on the upper surface of the silicon substrate 1, and the impurity introduction region 25 is connected to the pad 26 via a wiring 27 formed on an interlayer insulating film (not shown). Other structures of the TEG 55 according to the fifth embodiment are the same as those of the TEG 51 according to the first embodiment.

In the TDDB, a ground voltage is externally applied to the pad 26, and the ground voltage is applied to the impurity introduction region 25 via the wiring 27. A positive voltage for evaluation is applied to the pads 3, 4a to 4j, and this voltage is applied to the electrodes 2a to 2j via the wiring 5 and the diodes 24a to 24j or the wirings 7a to 7j. Thereby, an inversion layer is formed in the upper surface of the silicon substrate 1 below the electrodes 2a to 2j.

As described above, the TEG 5 according to the fifth embodiment
According to 5, the electrodes 2a to 2j are gate electrodes and the insulating film 8a
To 8j are gate insulating films, and impurity introduction regions 25 are
A transistor structure serving as a drain region was formed. Therefore, a positive voltage having the same polarity as the gate voltage of the NMOS transistor can be applied to the electrodes 2a to 2j as an evaluation voltage, and evaluation can be performed under conditions more suitable for an actual device.

In the above description, the first embodiment is described.
Although the example in which the invention according to the fifth embodiment is applied based on the TEG 51 according to the first embodiment has been described, the invention according to the fifth embodiment may be implemented based on the TEGs 52 to 54 according to the second to fourth embodiments. It can also be applied.

As described above, according to the first to fifth embodiments,
The example of the case where the TEG is configured using the p-type silicon substrate 1 has been described. TE using the same silicon substrate
It is also possible to configure G.

The TEG according to the first to fifth embodiments
By manufacturing a semiconductor device by forming a gate insulating film corresponding to an insulating film evaluated using 51 to 55 on a semiconductor substrate, a semiconductor device including a highly reliable gate insulating film can be obtained.

[0064]

According to the first aspect of the present invention, when the thickness of the insulating film to be evaluated is relatively large, a voltage for evaluation is applied to the first pad. The stress for evaluation can be applied to all the insulating films formed below the plurality of conductors at once. On the other hand, when the thickness of the insulating film is the thickness of the ultra-thin region, a voltage for evaluation is applied to the second pad, so that the insulating film formed under each conductor is evaluated. Stress can be individually applied.

According to the second aspect of the present invention, in the evaluation when a voltage for evaluation is applied to each conductor through the second pad, the current between different conductors is evaluated. Can be prevented from flowing mutually.

According to the third aspect of the present invention, the first connection means can be easily formed in the substrate.

According to the fourth aspect of the present invention, the evaluation stress is applied to all of the plurality of insulating films at once according to the thickness of the insulating film to be evaluated. A first pad, a second pad for individually applying an evaluation stress to each insulating film, and a third pad for applying the evaluation stress to two or more insulating films belonging to the same group at once. Pads to which a voltage for evaluation is to be applied can be selected from the above pads.

According to the fifth aspect of the present invention, in the evaluation when a voltage for evaluation is applied to each conductor via the second pad, the current between different conductors is evaluated. Can be prevented from flowing to each other, and in the evaluation when a voltage for evaluation is applied to each conductor through the third pad, the current flows between the conductors belonging to different groups mutually. Can be prevented.

According to the sixth aspect of the present invention, the first and second connection means can be easily formed in the substrate.

According to the seventh aspect of the present invention, it is possible to obtain a test structure for evaluating an insulating film including a field edge component as well as a surface component and a gate edge component.

According to the eighth aspect of the present invention, a test structure for evaluating an insulating film including a field edge component can be obtained by forming a second insulating film having a simple shape. Can be.

According to the ninth aspect of the present invention, a second insulating film having a shape conforming to an actual device is formed, and a test structure for evaluating an insulating film including a field edge component is formed. Can be obtained.

Further, according to the tenth aspect of the present invention, it is possible to carry out the evaluation under conditions suitable for an actual device.

According to the eleventh aspect of the present invention, since a voltage having the same polarity as the gate voltage of the transistor can be applied to the conductor as a voltage for evaluation, it is more suitable for an actual device. Evaluation can be performed under conditions.

According to a twelfth aspect of the present invention, an insulating film evaluated using the insulating film evaluation test structure according to any one of the first to eleventh aspects is a gate insulating film. , A semiconductor device having a highly reliable gate insulating film can be obtained.

[Brief description of the drawings]

FIG. 1 is a top view showing a structure of a TEG according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a sectional structure of the TEG according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a structure of a diode according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a structure of a diode according to the first embodiment of the present invention.

FIG. 5 is a top view illustrating a configuration of a wafer according to the first embodiment of the present invention.

FIG. 6 is a top view showing another configuration of the wafer according to the first embodiment of the present invention.

FIG. 7 is a top view showing a structure of a TEG according to a second embodiment of the present invention.

FIG. 8 is a sectional view showing a sectional structure of a TEG according to a second embodiment of the present invention.

FIG. 9 is a top view showing a structure of a TEG according to a third embodiment of the present invention.

FIG. 10 is a top view showing a structure of a TEG according to a fourth embodiment of the present invention.

FIG. 11 is a top view showing a structure of a TEG according to a fifth embodiment of the present invention.

FIG. 12 is a sectional view showing a sectional structure of a TEG according to a fifth embodiment of the present invention.

FIG. 13 is a top view showing the structure of a conventional TEG.

FIG. 14 is a top view showing the structure of another conventional TEG.

[Explanation of symbols]

1 silicon substrate, 2a-2j electrode, 3,4a-4
j, 23ab, 23cd, 23ef, 23gh, 23i
j pad, 6a-6j, 6ab, 6cd, 6ef, 6
gh, 6ij, 24a-24j Diode, 8a-8
j insulating film, 19v to 19z, 21 element isolation insulating film,
25 Impurity introduction region, 51 to 55 TEG.

Claims (12)

[Claims] A substrate, a plurality of first insulating films to be evaluated selectively formed on the main surface of the substrate, and a plurality of first insulating films formed on the plurality of first insulating films, respectively. A test structure for evaluating an insulating film, comprising: a plurality of conductors; a first pad commonly connected to the plurality of conductors; and a plurality of second pads respectively connected to the plurality of conductors. 2. A conductive state with respect to application of a voltage to the first pad formed between the first pad and the plurality of conductors, and application of a voltage to the second pad 2. The test structure for evaluating an insulating film according to claim 1, further comprising a plurality of first connection units that are in a non-conductive state with respect to the first connection unit. 3. The test structure for evaluating an insulating film according to claim 2, wherein said first connection means is a diode. 4. The plurality of conductors are divided into a plurality of groups each including two or more conductors, and are commonly connected to the two or more conductors belonging to the same group. 2. The test structure for evaluating an insulating film according to claim 1, further comprising a plurality of third pads provided on the first substrate. 5. A state in which a voltage is applied to the first pad, which is formed between the first pad and the plurality of third pads, and the conductive state is established. A plurality of first connection units that are non-conductive with respect to a voltage application; and a plurality of first connection units respectively formed between the third pad and the two or more conductors belonging to a group corresponding to the third pad. Was
A plurality of second connection units that are turned on when a voltage is applied to the first or third pad and are turned off when a voltage is applied to the second pad;
The test structure for evaluating an insulating film according to claim 4. 6. The test structure for evaluating an insulating film according to claim 5, wherein said first and second connection means are diodes. 7. The semiconductor device further comprises a second insulating film selectively formed in the main surface of the substrate, wherein the first insulating film is on the main surface of the substrate and the second insulating film. The test structure for evaluating an insulating film according to any one of claims 1 to 6, wherein the test structure is formed over the upper surface. 8. The test for evaluating an insulating film according to claim 7, wherein the second insulating film is a strip-shaped insulating film extending in a direction perpendicular to a direction in which the plurality of conductors extend. Construction. 9. The test structure for evaluating an insulating film according to claim 7, wherein said second insulating film is a planar insulating film having a plurality of cutouts. 10. The test structure for evaluating an insulating film includes a semiconductor substrate, an element isolation insulating film selectively formed in a main surface of the semiconductor substrate, and a test structure selectively formed on the main surface of the semiconductor substrate. In a semiconductor device including a formed gate insulating film and a gate electrode formed on the gate insulating film,
The pattern formed of the first insulating film, the conductor, and the second insulating film, which is used for evaluating the gate insulating film, includes the gate insulating film, the gate electrode, and the element isolation insulating film. The test structure for evaluating an insulating film according to claim 7, wherein the test structure has the same shape as a pattern formed of: 11. The semiconductor device according to claim 1, further comprising an impurity introduction region formed in the main surface of the substrate and having a conductivity type opposite to a conductivity type of the substrate, between the conductors adjacent to each other. 11. The test structure for evaluating an insulating film according to any one of items 10 to 10. 12. (a) a step of evaluating an insulating film using the test structure for evaluating an insulating film according to any one of claims 1 to 11, and (b) a step of: Forming a corresponding gate insulating film.