JP2002050605A - Stabilization method of silicon surface and manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To readily and surely establish a technique for realizing making operational rapidity of a semiconductor element for fixing to a silicon substrate surface to be easily applicable to mass production by heavy hydrogenation of the hydrogenated silicon substrate surface. SOLUTION: In the stabilization method of a silicon surface, a silicon substrate is immersed in heavy water or heavy hydrogen, containing solution comprising reducing ion and a hydrogenated surface is thereby subjected to heavy hydrogenation treatment. In the manufacturing method of a semiconductor device, stabilization method of a silicon surface is adopted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for stabilizing a silicon surface and a method for manufacturing a semiconductor device using the same as one step.

[0002]

2. Description of the Related Art Silicon wafers (silicon substrates), which are widely used in the manufacture of semiconductor devices, are very susceptible to oxidation, so that conductive impurity ions are introduced to selectively impart conductivity to the surface thereof. Alternatively, a cleaning step of removing a silicon oxide film from the surface of a silicon wafer is indispensable before a step of forming a semiconductor element by attaching a conductive material to the surface or the like. A long-known conventional means for cleaning silicon wafer surfaces is to expose the silicon wafer surface to a solution containing a small amount of hydrofluoric acid (HF) to dissolve away the silicon oxide film on the surface. is there. Since the silicon wafer surface obtained by the hydrofluoric acid (HF) treatment is covered with hydrogen (light hydrogen), a clean surface can be maintained relatively stably. The hydrogen-terminated surface serves as a source for supplying hydrogen atoms to the interface when the device is fabricated, and is expected to have improved electrical characteristics.

It is already known that, as a proposal for improvement, if the surface of a silicon wafer is covered with deuterium atoms instead of hydrogen atoms, further improvement in electrical characteristics can be expected. This is described in Japanese Unexamined Patent Application Publication No. 10-3
Since it is disclosed in Japanese Patent No. 35289, it will be described below. This method considers that the terminating treatment of silicon atoms with hydrogen atoms and fluorine atoms has a small or low surface terminating effect, and it is difficult to suppress the actual oxidizing action by oxygen or moisture. The terminus focuses on terminating the silicon atom by deuterium, that is, deuterium and tritium are isotopes of hydrogen and have almost the same chemical properties as hydrogen, but have a mass number of 2 of hydrogen. Due to the double and triple times, even if there is disturbance such as adsorption of foreign matter or thermal energy, vibration between the bonded silicon atoms terminated with deuterium or tritium is unlikely to occur, and therefore, the vibration energy is increased. Bond dissociation between deuterium or tritium and silicon atoms hardly occurs. Therefore, the bonding force between the deuterium atom or tritium atom and the surface silicon atom is stronger than the bonding force between the hydrogen atom and the silicon atom, so that the terminal effect is large and persistent. As means for that purpose, the above-mentioned publication discloses that a mixed agent containing at least (tri) fluoride deuterium or a mixed agent containing at least both (tri) deuterium fluoride and hydrogen fluoride is added to a silicon semiconductor substrate. The method is characterized in that the silicon semiconductor substrate is subjected to a deuterium termination treatment of surface silicon atoms by contact. In this method, (tri) deuterium fluoride means at least one of tritium fluoride and deuterium fluoride, that is, tritium fluoride or deuterium fluoride, and furthermore tritium fluoride and fluoride. Means both deuterium. Further, according to the method disclosed in the above publication, a purity of 1
It is not necessary to use 00% (tri) deuterium fluoride, and a mixture of (tri) deuterium fluoride and hydrogen fluoride may be used.

Certainly, if the deuteration termination treatment of the silicon wafer surface can be easily performed, it can be widely used in the manufacturing process of semiconductor devices.
To obtain a 00% deuterated surface requires a fully deuterated hydrofluoric acid solution. For this purpose, a production method in which deuterium fluoride (DF) gas is dissolved in heavy water (D ₂ O) is known as the only practical method, but the production method has been reduced to a level that can be practically applied to mass production. Not established.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has been made to provide a new means for easily and quickly performing a deuteration termination treatment on a silicon wafer surface. Things.

[0006]

In order to solve the above-mentioned problems, the present invention employs, for example, the following arrangement. (1) The surface of a silicon substrate is brought into contact with a solution containing a substance having a reducing property that can be dissolved by ionization and contains heavy water (D ₂ O), and the surface of the silicon substrate is deuterium-terminated or hydrogen-terminated. To stabilize the silicon surface. (2) The method of manufacturing a semiconductor device according to (1), wherein the step is performed after the step of exposing the surface of the silicon substrate to a hydrofluoric acid solution containing deuterium. (3) (as a first step) on the surface of the silicon substrate,
Selectively adding a conductive impurity to form an impurity region; and (as a second step) forming a conductive film on the impurity region so as to be in contact with the impurity region. In the method for manufacturing a semiconductor device, before the first step, the surface of the silicon substrate is brought into contact with a solution containing heavy water (D ₂ O) and containing a substance having a reducing property that can be dissolved by ionization. And a method for manufacturing a semiconductor device having a silicon surface stabilizing step of terminating the surface of the silicon substrate with deuterium or terminating with hydrogen. (4) Between the first step and the second step, the surface of the silicon substrate is brought into contact with a solution containing a deionizable substance containing heavy water (D ₂ O) and being ionizable and soluble. The method of manufacturing a semiconductor device according to (3), further comprising a silicon surface stabilizing step of terminating the surface of the silicon substrate with deuterium or terminating with hydrogen. (5) (as a first step) on the surface of the silicon substrate,
Selectively adding a conductive impurity to form an impurity region; and (as a second step) forming a conductive film on the impurity region so as to be in contact with the impurity region. A method for manufacturing a semiconductor device, comprising: between a first step and a second step, a solution containing a substance having heavy water (D ₂ O) and having an ionizable and reducible reducing property, A method for manufacturing a semiconductor device, comprising: a silicon surface stabilizing step of bringing the surface of a silicon substrate into contact with the surface of the silicon substrate and terminating the surface of the silicon substrate with deuterium or hydrogen. (6) The conductive film is a refractory metal, and after the second step, a step of forming a refractory metal silicide between the conductive film and the silicon substrate is provided. (5) The method for manufacturing a semiconductor device according to (5). (7) The method of manufacturing a semiconductor device according to (2) to (6), wherein the first step is performed after the step of exposing the surface of the silicon substrate to a hydrofluoric acid solution containing deuterium. (8) The substance having a reducing property is SO ₃ ^2- ,
^{_{I -, H 2 PO 2 2-}} , S 2 O 3 2-, N 2 H 5 +, COOH -, C 6 H 4 N
H ₂ NH ₃ ⁺ , C ₆ H ₄ OHO ⁻ , C ₆ H ₄ O ₂ ²⁻ , HPHO ₃ ⁻ , P
^{_{HO 3 2-, C 6 H 3}} C 4 H 9 OCH 3 OH - said which is characterized in that which has been selected from either (1) to (7)
The manufacturing method of the semiconductor device described in the above. (Effects of the Invention) In the present invention, similarly to the above-mentioned prior art,
The treatment is performed in a solution. A hydrofluoric acid (HF) solution is applied to the surface of the silicon wafer to remove a silicon oxide film naturally formed on the surface of the silicon wafer, and then heavy water (D ₂ O) is used. Reducing ions, since heavy water (D ₂ O) dissolved to have oxygen and aggressive reaction in proceeds, the ions become able to stably present in heavy water (D ₂ O), deuterium oxide (D ₂ O) and hydrofluoric acid (HF) already on the silicon wafer surface
The atom exchange reaction between the hydrogen that has been terminated by the treatment and the attached hydrogen and the deuterium in the heavy water easily proceeds, and oxidation of the wafer surface by oxygen is suppressed, so that the deuteration of the silicon wafer surface is completed in a short time. It will be.

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. [Example of hydrogen termination process on silicon wafer surface] The hydrogen termination process on the silicon wafer surface may be performed, for example, in the procedure shown in FIG. See FIG.

FIG. 1 is an explanatory view (schematic cross-sectional view) of a hydrogen termination process on a silicon wafer surface according to an embodiment of the present invention. (First Step) First, the prepared silicon wafer (silicon substrate) is immersed in a liquid tank storing a 1.5% hydrofluoric acid (HF) aqueous solution for 5 minutes. Through this process, the silicon oxide film is dissolved and removed from the silicon wafer surface. The etching speed is about 10 nm per minute. (Second step) Next, the silicon wafer is treated with hydrofluoric acid (H
F) Pulled up from the liquid tank, and then 10 minutes in pure water tank
It is shower washed for a minute. (Third step) Thus, after the hydrofluoric acid chemical was washed away,
10 (NH ₄ ) ₂ SO ₃ containing reducing ions SO ₃ ^2-
It is immersed in heavy water (D ₂ O) containing 15% by weight for 15 minutes.

(Fourth Step) Next, spin drying is performed to remove droplets from the surface of the silicon wafer. In this step, a chemical treatment for causing IPA (isopropyl alcohol) to act on the surface of the silicon wafer may be performed.

[0010] Thus, the surface of the silicon wafer is substantially 100% deuterated. When it is desired to control the degree of deuteration, it can be obtained by changing the mixing ratio of heavy water (D ₂ O) and light water (H ₂ O). See FIG.

FIG. 2 is a diagram showing the results of infrared spectroscopy analysis of the silicon wafer surface. In the figure, the upper part (a) shows the results of infrared spectroscopy analysis when the silicon wafer surface is terminated with hydrogen. On the other hand, the lower part (b) shows the result of infrared spectroscopy analysis in the case where the silicon wafer surface is terminated with deuterium after the example of (a) in which the silicon wafer surface is terminated with hydrogen. In both cases (a) and (b), the horizontal axis indicates the wave number (cm ^-1 ) and the vertical axis indicates the absorbance (dimensionless). FIG. 2 shows the results of infrared spectroscopic analysis of the stretching vibration of the Si—H bond (or Si—D bond) on the silicon wafer surface after the deuterium termination performed according to the above-described embodiment of the present invention. Obtained by observation,
The position of the peak of the Si—H bond appearing in FIG.
083 cm ^-1 , while the Si appearing in FIG.
The position of the peak of the -D bond is about 1515 cm ^-1 , indicating that H (hydrogen) has been completely replaced by D (deuterium).

The above is an example of the hydrogen termination processing step on the silicon wafer surface according to the present invention. Then, if the process is shifted to the step of forming devices in the silicon wafer having undergone the above deuterium termination processing, the effects of the invention can be obtained. Can be

Actually, the opportunity to expose the silicon substrate surface appears not only at the beginning of the semiconductor device manufacturing process but also during the manufacturing process. An application example in such a case will be described based on a plurality of embodiments described below. [First Embodiment of Manufacturing Method of Semiconductor Device of the Present Invention] FIGS. 3A to 3D and FIGS. 4A to 4
A first embodiment of the present invention will be described with reference to FIG.

The silicon substrate 1 shown in FIG. 3A is a p-type substrate having a resistivity of 10 Ωcm. The surface of the silicon substrate 1 is selectively oxidized by the LOCOS method to form a field oxide film 2. For example, by performing oxidation for 6 hours at a substrate temperature of 950 ° C. in a wet oxygen atmosphere,
A field oxide film 2 having a thickness of 250 nm is formed. Active regions 20A and 20B are defined by field oxide film 2.

As shown in FIG. 3B, the active region 20
Gate oxide films 3A and 3B are formed on the surfaces of A and 20B by thermal oxidation, respectively. For example, oxidation is performed for 10 minutes at a substrate temperature of 1000 ° C. in a dry oxygen atmosphere diluted with argon to form an oxide film having a thickness of 6 nm.

A 180 nm-thick polysilicon film 4 is deposited on the surfaces of the field oxide film 2 and the gate oxide films 3A and 3B by chemical vapor deposition (CVD). For example, the polysilicon film 4 is formed at a growth temperature of 650 ° C. using SiH 4 as a source gas.

As shown in FIG. 3C, the polysilicon film 4 is patterned, and the gate electrodes 4A, 4B are formed on the surfaces of the active regions 20A, 20B via gate oxide films, respectively.
To form At the same time, a polysilicon wiring 4C is formed on the surface of the field oxide film 2 at the right end of the figure. The polysilicon wiring 4C is, for example, another MOSFET not shown in the drawing.
Connected to the gate electrode. The polysilicon film is etched by, for example, reactive ion etching (RIE) using HBr as an etching gas. If necessary, an n-type impurity is ion-implanted using the gate electrodes 4A and 4B as a mask.

This ion implantation is for forming a source / drain region having an LDD structure.
If no structure is used, this ion implantation is omitted. Next, a silicon oxide film having a thickness of about 100 nm is deposited by CVD. CF4 + C is applied to this silicon oxide film.
RIE using an HF3 mixed gas as an etching gas is performed to form sidewall oxide regions 5A on the side walls of the gate electrodes 4A and 4B and the polysilicon wiring 4C, respectively.
The silicon oxide film on the flat surface is removed, leaving 5B and 5C.

After that, the surface of the silicon substrate is sacrificed once, the sacrificial oxide film is removed using a 10% dilute HF (hydrofluoric acid) solution, and the surface of the silicon substrate is cleaned. Similarly, the surface is subjected to hydrogen termination using heavy water containing reducing ions. At this time, a 10% diluted DF (deuterium fluoride) solution may be used. Also,
If the purpose of process simplification is strongly considered or if a heating step cannot be added carelessly, it is better to omit the step of forming a sacrificial oxide film.
If surface treatment is performed using a (hydrofluoric acid) solution or a 10% dilute DF (deuterium fluoride) solution, a natural oxide film attached to silicon exposed on the substrate surface after the completion of the previous process can be removed, and hydrogen termination is performed. It is preferable to increase the effect of the treatment.
Here, the wafer in which the gate portion where silicon is exposed has been deuterated is put into a heat treatment apparatus, and thermal desorption of hydrogen is not performed.
Put in O2 or NO gas at 400 ° C or lower to form a thin oxide film of 1 nm. This oxide film contains a large amount of 1e19 cm-3 of deuterium, and efficiently functions as a deuterium supply source to the interface with Si. Further, in order to obtain a desired thickness of the oxide film, oxidation is continued in, for example, O2 at a temperature of 850 ° C. or less so that deuterium is not diffused and disappeared, and a SiO2 film of, for example, 30 nm is obtained. Furthermore, annealing at 850 ° C in NO gas and introducing nitrogen atoms to the interface with Si does not affect the effect of deuterium.

As shown in FIG. 3D, the gate electrode 4
A and 4B and As are ion-implanted using the sidewall oxide regions 5A and 5B as masks. For example, ion implantation is performed under the conditions of an acceleration energy of 25 keV and a dose of 2.times.10@15 cm @ -2. Subsequently, rapid thermal annealing is performed at 1000 ° C. for 10 minutes to activate the ion-implanted As. Thus, source regions 6A and 6B and drain regions 7A and 7B are formed. At this time, the gate electrodes 4A and 4B are also doped with As to reduce the resistance.

Next, a cobalt (Co) film 8 having a thickness of 10 nm is deposited on the entire surface of the substrate by sputtering. In this sputtering step, for example, an argon gas as a sputtering gas is flowed at 100 sccm,
Keep the pressure in the sputtering chamber at about 0.1 Pa,
This is performed by applying an RF power of about 3.7 W / cm 2 to the target o.

As shown in FIG. 4A, at a temperature of 800.degree.
Heat treatment is performed for 30 seconds to cause a silicide reaction between the Co film 8 and silicon in contact therewith. By this silicide reaction, the source regions 6A and 6B and the drain region 7
A Co silicide layer 9 is formed on the surfaces of A and 7B, the upper surfaces of the gate electrodes 4A and 4B, and the upper surface of the polysilicon wiring 4C. Subsequently, the unreacted Co film is removed with a mixed solution of aqueous hydrogen peroxide and sulfuric acid.

As shown in FIG. 4B, a nickel (Ni) film 10 having a thickness of 5 nm is deposited on the entire surface of the substrate by sputtering. Subsequently, a polysilicon film is deposited by sputtering. This polysilicon film is patterned by photolithography using a novolak-based resist mask 12 to form a polysilicon pattern 1.
1A and 11B are formed.

The polysilicon pattern 11A extends from the region where the drain region 7A is formed to the region where the drain region 7B is formed by passing over the field oxide film 2 in the center of the figure. The polysilicon pattern 11B is formed in the source region 6B.
From the region where is formed to the upper surface region of the polysilicon wiring 4C through the field oxide film 2 on the right end of the figure.

After patterning the polysilicon film, the resist mask 12 is removed by ashing. In this ashing process, for example, a barrel type plasma asher is used, the pressure in the ashing chamber is set to about 1 torr, and the RF
A power of 1 kW is applied to generate oxygen plasma, and ashing the resist mask.

Under this condition, the Ni film 10 in a region not covered with the polysilicon film is oxidized by about 4 nm. This damage remains in the Ni film, and the underlying Co silicide layer 9 and the silicon substrate 1 are not damaged.

As shown in FIG. 4C, at a temperature of 400.degree.
Heat treatment is performed for 20 minutes to cause a silicide reaction between the Ni film 10 and the polysilicon patterns 11A and 11B. Thereby, the Ni silicide patterns 13A, 13A
B is formed. Subsequently, the unreacted Ni film is removed.

At 400 ° C., since Co and Si hardly react with each other, the silicide layer 9 has the source regions 6A, 6B,
And hardly penetrate into the drain regions 7A and 7B.
Therefore, even if the source / drain regions are made shallow, the silicide layer 9 does not reach the substrate 1 beyond the pn junction, and the occurrence of a leak current can be prevented.

As described above, as the metal film to be silicided for the second time, a metal which is easier to silicide at a lower temperature than the metal film to be silicided for the first time is used, and the temperature for the second silicidation is changed to the first silicidation. By setting the temperature to be lower than the temperature, the occurrence of a leak current when the source / drain regions are made shallow can be prevented. In the case where Co is used as the metal to be silicided the first time, the temperature for siliciding the second time is set to 700 ° C.
It is preferable to set the following.

One end of the Ni silicide pattern 13A contacts the Co silicide layer 9 formed on the surface of the drain region 7A, and the other end contacts the Co silicide layer 9 formed on the surface of the drain region 7B. One end of the Ni silicide pattern 13B contacts the Co silicide layer 9 formed on the surface of the drain region 7B, and the other end contacts the Co silicide layer 9 formed on the upper surface of the polysilicon wiring 4C.

Next, as in the ordinary LSI manufacturing process, C
An interlayer insulating film is deposited by VD, a contact hole is opened, and metal wiring is performed. In the first embodiment described above, at the time of the ashing step of the resist mask 12 shown in FIG. 4B, the Co silicide layer 9 has already been formed and the resistance has been reduced. Therefore, the Ni film 1 is formed by ashing.
Even if 0 is damaged, the source / drain region, gate electrode and polysilicon wiring which have already been reduced in resistance are hardly affected.

By inverting all conductivity types, a p-channel MOS transistor can be formed by the same process. For CMOS devices, n
A p-channel MOS transistor and an n-channel MOS transistor may be formed on the well and the p-well, respectively.

In the first embodiment, the first embodiment shown in FIG.
In the second silicidation, Co silicide is formed, and FIG.
Although the case where Ni silicide is formed by the second silicidation shown in FIG. 2C has been described, another metal silicide may be formed. Further, the same metal silicide may be formed in the first and second times. For example, silicide such as titanium, tungsten, platinum, chromium, and molybdenum may be used.

In the first embodiment, FIG.
As shown in (B), for the second silicidation, a Ni film 10 is formed as a lower layer, and a polysilicon pattern 11A is formed as an upper layer.
Although 11B is formed, the upper layer and the lower layer may be exchanged, and a polysilicon film may be formed in the lower layer and a Ni pattern may be formed in the upper layer. Alternatively, the lower layer film may be patterned, and the upper layer film may be deposited on the entire surface.

Next, a second embodiment of the present invention will be described with reference to FIGS. 5 (A) to 5 (D). FIG.
5A to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. In order to explain the method of manufacturing the local wiring, other parts are simplified.

As shown in FIG. 5A, a MOS transistor having an LDD structure is formed on the surface of a substrate 51 surrounded by a field oxide film 52 by a usual method. In the figure, MO
S transistor Q is an n-channel MOS transistor, and is formed in p-type silicon region 51. A silicon gate electrode 54 is formed on gate insulating film 53, and both side surfaces are covered with an oxide film of sidewall oxide region 55. An n-type source region 56 and a drain region 57 are formed on both sides of the gate electrode. At this stage, the surface of the silicon substrate is sacrificed once,
The sacrificial oxide film is removed using a solution of HF (hydrofluoric acid) at a low concentration, and the surface of the silicon substrate is cleaned. Then, as in the above-described heavy water treatment, the surface is terminated with hydrogen using heavy water containing reducing ions. I do. At this time, a 10% diluted DF (deuterium fluoride) solution may be used. When the purpose of simplifying the process is strongly considered or when the heating step cannot be added carelessly, it is better to omit the step of forming the sacrificial oxide film. If the surface treatment is performed using an acid) solution or a 10% dilute DF (deuterium fluoride) solution, a natural oxide film adhered to silicon exposed on the substrate surface after the completion of the previous process can be removed. It is preferable for improving the effect.

On the field oxide film 52 on the right side of FIG.
A continuous silicon wiring 58 extends from the gate electrode of another transistor. Oxide films of the sidewall oxide regions 59 are also formed on both side walls of the silicon wiring 58. Hereinafter, the drain region 5 of the MOS transistor Q
7 will be described with respect to a method of forming a local wiring connecting the silicon wiring 58 to the silicon wiring 58.

Referring to FIG. 5B, a Co film 60 having a thickness of about 10 nm and a platinum (P) film having a thickness of about 3 nm
t) A film 61 and a Si film 62 having a thickness of about 30 nm are formed by sputtering. A resist mask 63 is formed so as to cover a region where the Si film 62 is to be left.

As shown in FIG. 5C, the Si film 62 is etched to form a Si film pattern 62a. The etching of the Si film 62 is performed, for example, using an ordinary parallel plate type RIE apparatus, using SF6 gas at a flow rate of about 100 sccm as an etching gas, maintaining the pressure at about 50 mtorr, and applying a pressure of approximately 20
This is performed by applying RF power of 0 W.

After completion of the etching, the resist pattern 63
Is separated by a down-flow ashing apparatus using oxygen plasma. At the time of ashing, an ashing residue is usually generated, and thus the ashing residue is removed with a resist developer. Ashing residue is generated in the Si film 62.
It is considered that the resist is deteriorated during the etching.

Thereafter, the substrate is carried into a sputtering apparatus, and a TiN film 64 is deposited by sputtering to a thickness of about 50 nm. That is, the Pt film 61 and the TiN film 64 are stacked with the Si film pattern 62a interposed therebetween.

Thereafter, the substrate is heated to about 600 ° C. by, for example, rapid thermal annealing (RTA) to cause a silicide reaction of the Pt film 61 and the Co film 60 to proceed. C
The portion where the o film 60 is in contact with the surface of the substrate 51, the portion where the o film 60 is in contact with the gate electrodes 54 and 58, and the Pt film 61
A silicide reaction proceeds in a portion in contact with the i-film pattern 62a. As shown in FIG.
After forming the local wiring 66 of silicide in the region where the film pattern 62a was present, the remaining TiN film 64 and the unreacted Pt film 61 are removed with a mixed solution of NH4 OH + H2 O2, and the unreacted Co film 60 is further removed. H2SO4 + H2
Remove with O2 (1: 1) mixture. The unreacted Co film may be removed by HCl + H2 O2 (1: 1). After this, it is preferable to introduce the hydrogen termination treatment step of the present invention described above. At this stage, 10%
After removing the natural oxide film from the surface using a dilute HF (hydrofluoric acid) solution and cleaning the surface of the silicon substrate, hydrogen termination of the surface is performed using heavy water containing reducing ions in the same manner as the heavy water treatment described above. Perform processing. At this time, a 10% diluted DF (deuterium fluoride) solution may be used.

As described above, the silicide layer 65 is formed on the surface of the Si region, and the local wiring 66 extending on the field oxide film 52 can also be formed. Here, the ion-implanted Si surface is covered with deuterium by the method of the present invention, but at the same time, defects and unbonded bonds in Si generated by ion implantation also diffuse during the deuteration process to form SiD bonds. Is also expected. This silicon substrate is put into a sputtering apparatus, and a substrate temperature of 400 ° C. or less (for example,
(25 ° C.) while depositing Co atoms. After heating this silicon substrate to react (silicide) with the Si substrate,
When only unreacted Co is removed in sulfuric acid, a silicide layer remains only in the portion where Si was exposed. At this time, deuterium is present at about 1e20 cm-3 on the initial Si surface or in the immediate vicinity thereof,
It has the effect of lowering the electrical resistance at the interface between Si and the silicide by combining with defects due to ion implantation and dangling bonds. This lowers the output impedance of the MOS device, increases the number of transistors that can be driven by one transistor, and improves the performance of the MPU circuit.

In the second embodiment shown in FIGS. 5A to 5D, when the ashing residue of the resist mask 63 is removed using a resist developing solution, the surface of the Co film 60 becomes a Pt film. It is covered with 61. Since Pt is hardly damaged by the developing solution, the underlying Co film 60 is hardly damaged. During the silicide reaction, substantially uniform Co is formed on the surface of the substrate 51, the upper surface of the gate electrode 54, the upper surface of the silicon wiring 58, and the lower surface of the Si film pattern 62a.
Since the film 60 remains, a suitable silicide film 65 can be obtained.

In the second embodiment, the silicide reaction was performed by covering the surfaces of the Si film pattern 62a and the Pt film 61 with the TiN film 64. Since the Si film pattern 62a is covered with the TiN film 64, the Si film pattern 62a
a is prevented from being oxidized, and a suitable silicide film can be obtained.

Next, a third embodiment in which a silicide layer is used as a contact pad will be described with reference to FIGS. 6A and 6B. In FIG. 6A,
For example, a gate oxide film 72 is formed on the surface of a p-type Si substrate 71.
a is formed thereon, and silicon gate electrodes 73a, 73
3b is formed. The surfaces of the gate electrodes 73a and 73b are further covered with an insulating film. Also,
The side walls of the gate electrode are also covered by the insulating films 74a and 74b. By ion implantation using the gate electrode as a mask, an n-type region 75 is formed on the surface of the p-type substrate region 71.
a, 75b and 75c are formed.

A silicide pad 77 extends from n-type region 75b onto an insulating film surrounding gate electrodes on both sides.
To form The structure shown in FIG. 6A can be formed by adding a step of forming an insulating film 76 to the method of the first and second embodiments. The pad 77 is
It has an area larger than the exposed surface of the Si substrate 71.

An interlayer insulating film 78 is formed so as to cover the pad 77, and a contact hole is formed. This contact hole only needs to be aligned with the pad 77, and the n-type region 7
The positional accuracy can be eased as compared with the case where the position alignment is performed with the exposed surface of 5b.

Thereafter, an electrode layer 79 made of Al or the like is formed on the surface, and by patterning, an interconnect 79 electrically connected from the n-type region 75b via the pad 77 is formed.

FIG. 6B shows another configuration example of the third embodiment. A field oxide film 83 is formed on the surface of Si substrate 71, and a MOS transistor Q is formed in an element region defined by field oxide film 83. The MOS transistor Q has a structure in which the surface of the gate electrode is covered with an insulating film 76, similarly to the MOS transistor shown in FIG.

That is, a gate insulating film 72, a gate electrode 73, and an insulating film 76 are laminated on the surface of the Si substrate 71, and are patterned to form a gate electrode structure whose surface is insulated. Further, the side wall of the gate electrode structure is covered with an insulating film in the side wall oxide region 74. N-type regions 75d and 75e are formed on both sides of the gate electrode.

In this state, silicide pad 80 extending from the surface of n-type region 75e to the surface of field oxide film 83 is formed by the same method as in the first and second embodiments. Thereafter, an opening exposing the pad 80 is formed by covering the surface with an interlayer insulating film 78. At this time, the pad 80 functions as an etching stop layer.

Thereafter, a wiring layer of Al or the like is formed on the surface, and is patterned to form a wiring 81. Wiring 8
Since the connection between 1 and n-type region 75e is made via pad 80, the positioning accuracy is relaxed.

In the embodiment described above, the thickness of the Co film is about 10 nm, but can be arbitrarily selected from the range of 5 to 50 nm. The thickness of the Si film is about 5
Although it was 0 nm, it can be arbitrarily selected from the range of 20 to 200 nm. The patterning of the Si film or the TiN film is not limited to the method of the above embodiment. Further, similar silicide electrodes or wirings can be applied to circuits other than the above-described embodiments.

Next, FIG. 7A, FIG. 7B, FIG.
(A), FIG. 8 (B), and FIG. 9, an embodiment in which local wiring using a silicide reaction is applied to a ring oscillator and an SRAM will be described. FIG. 7A is an equivalent circuit diagram of a part of the ring oscillator, and FIG.
FIG. 3 is an equivalent circuit diagram of a RAM cell.

In FIG. 7A, two inverter circuits INV1 and INV2 are connected between a power supply voltage line VDD and a ground line VSS (or two power supply lines). In the first inverter circuit INV1, the source S1 of the p-channel MOS transistor Q1 is connected to the power supply line VDD,
The drain D1 is an n-channel MOS transistor Q2
Is directly connected to the drain D2. Also, n channel M
The source S2 of the OS transistor Q2 is connected to the ground line VSS. The gates of the two transistors Q1 and Q2 are commonly connected to a gate electrode G1,
1, a common input signal is applied to the gates of Q2.

In the second inverter circuit INV2, the source S3 of the p-channel MOS transistor Q3 is connected to the power supply line VDD, and the drain D3 is directly connected to the drain D4 of the n-channel MOS transistor.
The source S4 of the n-channel MOS transistor Q4 is connected to the ground line VSS. Two transistors Q3,
The gate of Q4 is connected to a common gate electrode G2. Drains D1, D of the first inverter circuit INV1
The output line connected to the second inverter circuit INV
2 is connected to the second gate electrode G2.

As described above, the plurality of inverter circuits INV connected between the two power supply lines VDD and VSS are connected in cascade. Here, the first inverter circuit I
An output line connecting the drains D1 and D2 of the NV1 is connected to the second
Is connected to the gate electrode G2 of the inverter circuit INV2 by the local wiring LI1.

In FIG. 7B, two power supply lines VD
Two inverter circuits INV1 and INV2 are connected between D and VSS as in FIG. 7A. Also, the first
The drains D1 and D2 of the inverter circuit INV1 are connected to the gate electrode G2 of the second inverter circuit INV2 by the local wiring LI1.

In this configuration, the output line connecting the drains D3 and D4 of the second inverter circuit INV2 is fed back to the gate electrode G1 of the first inverter circuit INV1 by the local wiring LI2.

Further, the output line of the first inverter circuit is connected to the bit line via the transfer transistor Q5. BL (B
L), and the output line of the second inverter circuit INV2 is connected to the bit line BL via the transfer transistor Q6.
It is connected to the. Two transfer transistors Q5, Q6
Are connected to the word line WL.

FIGS. 8A and 8B show FIG. 7A.
FIG. 3 is a schematic diagram showing an upper surface of a semiconductor device forming a part of the ring oscillator shown in FIG. FIG. 8A is a plan view at the stage when a gate electrode is formed over a semiconductor substrate and source / drain regions are formed. In the figure, an n-well is formed on the left side and a p-well is formed on the right side.

The regions other than the surface regions 43 and 44 of the n-well are covered with a field oxide film. Further, regions other than the surface regions 45 and 46 of the p-well are covered with the field oxide film. Gate electrode G1 is formed through a gate oxide film so as to penetrate surface regions 43 and 45. Further, the gate electrode G2 has a surface region 44,
46 is formed through a gate oxide film so as to penetrate through the gate oxide film 46.

As described above, after the gate electrodes G1 and G2 are formed, the p-well region is covered with a resist mask, and p-type impurities are ion-implanted, so that the p-well is formed in the n-well region.
Source regions S1, S3 and p-type drain regions D1, D
Form 3

Further, the n-well region is covered with a resist mask and n-type impurities are ion-implanted to form n-type source regions S2 and S4 and n-type drain regions D2 and D4 in the p-well region. Thus, FIG.
The four MOS transistors Q1, Q2, Q shown in FIG.
3. The basic structure of Q4 is formed.

FIG. 8B shows a state in which inverters are cascaded by forming local wirings LI on the basic structure shown in FIG. 8A by the method of the first or second embodiment. Is shown. The local wiring LI1 connects the two drains D1 and D2 of the first inverter circuit INV1, and further connects the gate electrode G2 of the second inverter INV2.
Connect to The local wiring LI1 has two drain regions D
1, except for the portion overlapping with D2 and the gate electrode G2,
Since it is arranged directly on the field oxide film, there is no need to provide an interlayer insulating film to insulate it from other circuit elements.

FIG. 9 is a plan view of a semiconductor device showing a configuration example of the SRAM circuit shown in FIG. 7B. FIG. 7 (B)
In order to realize the cross wiring of FIG.
The arrangement is different from that of FIG.

In FIG. 9, an n-well is formed on the upper side, and a p-well is formed on the lower side. a surface region 41 in the n-well is defined surrounded by a field oxide;
A surface region 42 in the p-well is similarly defined by the field oxide. The Si surface other than these surface regions 41 and 42 is covered with a field oxide film.

The surface region 41 of the n-well has an inverted T-shape, and the surface region 42 of the p-well has an inverted U-shape. Two gate electrodes G1 and G2 are formed so as to penetrate the horizontal portion of the T-type surface region 41 and the horizontal portion of the U-type surface region 42. In this configuration, a gate electrode G3 is further formed below in the figure.

By ion implantation using these gate electrodes G1, G2, G3 as a mask, the gate electrodes G1, G2,
The portion of the surface region 41 not covered with G2 is doped with a p-type impurity to form a p-type region, and the portion of the surface region 42 not covered with the gate electrodes G1, G2, and G3 is doped with an n-type impurity. It is an n-type region.

As described above, FIG. 8A and FIG.
As in (B), four MOS transistors Q1, Q2,
Q3 and Q4 are formed, and two other MOs are formed.
S transistors Q5 and Q6 are also formed.

In this configuration, MOS transistor Q
The source regions of Q1 and Q3 are common regions, and are denoted by S1 in the figure. Also, two MOS transistors Q2, Q
The source region No. 4 is also formed in the common region and is indicated by S2 in the figure. Furthermore, two MOS transistors Q5, Q5
The drain region 6 is formed as a common region with the drain regions of the two MOS transistors Q2 and Q4, respectively, and is indicated by D2 and D4 in the figure, respectively.

In such a configuration, the gate electrode G
1, the surfaces of G2 and G3 are covered with an insulating film, and the insulating film is peeled off only in the contact regions CT1 and CT2. That is, the gate electrode is exposed only in the portion of the contact region CT, and the substrate surface is exposed only in portions of the surface regions 41 and 42 that are not covered by the gate electrodes G1, G2, and G3.

In such a configuration, local wirings LI1 and LI2 are formed by the method of the first or second embodiment. The local wiring LI1 is formed to connect the drain regions D1, D2 and the contact region CT2 of the gate electrode G2, and the local wiring LI2 is formed to connect the drain regions D3, D4 and the contact region CT1 of the gate electrode G1.

Although these local wirings LI1 and LI2 are in contact with the surface of the underlying semiconductor at three ends, they are arranged on the insulating film in other regions. Therefore, when forming the local wirings LI1 and LI2, it is not necessary to particularly provide an interlayer insulating film.

An interlayer insulating film is formed on local interconnections LI1 and LI2, and contact holes CT3, CT4 and CT4 are formed so as to expose the surfaces of source regions S2, S5 and S6.
Form CT5.

By forming a silicide pad P3 so as to cover the surface of the source region S2 and extend over the insulating film surrounding the gate electrodes G1 and G2 on both sides, a description will be given with reference to FIG. As described above, the contact hole C
The alignment accuracy of T3 can be reduced. Also,
By forming pads P4 and P5 extending from the surfaces of source regions S5 and S6 on the field oxide film in the regions where contact holes CT4 and CT5 are to be formed,
As described with reference to FIG.
4. The positioning accuracy of CT5 can be reduced.
In the local wiring forming method according to the conventional example, in an intermediate process,
A region where a silicon pattern is to be formed is covered with a resist pattern, and the silicon film is selectively etched. After this etching, the resist pattern used as a mask is peeled off by ashing using plasma or dissolution by an etchant containing acid. At the time of removing the resist, the titanium film is exposed in a region not covered with the resist pattern. For this reason, the exposed titanium film 106 is oxidized or thinned by sputtering with plasma. If the titanium film 106 is damaged as described above, a good silicide layer with low resistance may not be formed in the subsequent silicide reaction. Therefore, after improving the process, a metal film extending from the silicon substrate surface onto the local oxide film and reacting with silicon by silicide is deposited,
By heating the substrate, metal silicide is formed on the surface of the silicon substrate in contact with the metal film, and the surface is reduced in resistance. Further, when a metal film that reacts with silicide with silicon is deposited, and a patterned silicon film is deposited thereon and the substrate is heated, the silicon film reacts with the metal film to form another metal silicide. At the time of patterning the silicon film, metal silicide has already been formed on the surface of the silicon substrate. Therefore, even when the exposed metal film is damaged during the patterning of the silicon film, it is possible to form a good metal silicide on the surface of the silicon substrate. When forming the second layer of metal silicide,
Even if a silicon film is deposited as a lower layer and a patterned metal film is deposited thereon, it is possible to form a good metal silicide similarly.

The first metal film extending from the silicon substrate surface to the local oxide film and reacting with silicon by silicide
When a patterned silicon film is deposited thereon and the substrate is heated, the surface of the silicon substrate in contact with the metal film and the patterned silicon film are converted into a metal silicide. When patterning the silicon film, the first and second metal films are stacked thereunder. Therefore, when the silicon film is patterned, even if the upper second metal film is damaged, the lower first metal film is hardly damaged. During silicidation, the first metal film that is not damaged is in contact with the surface of the silicon substrate, so that a good metal silicide can be formed on the surface of the silicon substrate. In addition, when the metal film has a two-layer structure, an optimum metal material can be selected. For example, a material that is less likely to be damaged during patterning of the silicon film can be used for the upper second metal film.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

The above is the description of the embodiment of the present invention.
In the present invention, without being bound by the above-described embodiment,
Modifications can be made by freely replacing elements without departing from the essential features of the invention. First, as the reducing ions, examples of other replaceable ions in addition to the above-mentioned SO ₃ ²⁻ include I ⁻ , H ₂ PO ₂ ²⁻ , S ₂ O ₃ ²⁻ , N ₂ H ₅ ⁺ , COOH ^- , C
^{_{6 H 4 NH 2 NH 3 +}} , C 6 H 4 OHO -, C 6 H 4 O 2 2-, HPHO
^{_{3 -, PHO 3 2-, C}} 6 H 3 C 4 H 9 OCH 3 OH - , and the like. As a substance containing these ions, for example, (NH ₄ ) ₂ S
O ₃ , HI, NaH ₂ PO ₂ , Na ₂ S ₂ O ₃ , N ₂ H ₄ , HCOOH, C ₆ H
₄ (NH ₂ ) ₂ , C ₆ H ₄ (OH) ₂ , (NH ₄ ) ₂ PHO ₃ , Na ₂ PHO ₃ , C ₆ H ₄ O
CH ₃ OH, p-Methoxyphenol, etc. In addition, heavy water (D ₂
Instead of the deuterium termination treatment with O), a tritium termination treatment with triple water (T ₂ O) can be used. Furthermore, the solution that can be used for the deuterium termination treatment is not limited to pure heavy water (D ₂ O). Of course, a mixture of heavy water (D ₂ O) and another solution may be used, and the effect of hydrogen termination should be slightly reduced. However, a mixture of heavy water (D ₂ O) and light water (H ₂ O) may be used. . Furthermore, heavy water (D ₂ O) and light water (T ₂ O)
Can also be used. In this case, the effect of the deuterium termination treatment can be expected to be even higher. Further, a hydrofluoric acid (HF) solution treatment for introducing a pre-treatment to remove a silicon oxide film is performed by a deuterium fluoride (D) treatment.
If F) solution or tritium fluoride (TF) solution treatment can be used, it can be expected that deuterium (tritium) termination treatment in the silicon wafer surface can be performed more reliably.

Further, in addition to those shown as one embodiment of the present invention, similar effects can be obtained by applying the invention to fine devices such as semiconductor devices and display devices.

[0082]

As described above, according to the present invention,
Hydrogen termination of the exposed silicon surface can be effectively performed. Such a hydrogen termination treatment can provide a particularly high effect when used in a logic device that requires a high-speed operation. In other words, a semiconductor device including a logic circuit that attempts to achieve a high-speed operation by reducing the resistance value at the interface at the time of wiring connection by using salicide technology or the like is particularly preferable because a high-speed operation characteristic can be obtained. As a result, such an effect
It would also be suitable for the purpose of achieving higher miniaturization of high-speed logic devices with higher reliability.

[Brief description of the drawings]

FIG. 1 is an explanatory view (schematic cross-sectional view) of a hydrogen termination process on a silicon wafer surface according to an embodiment of the present invention.

FIG. 2 is a diagram showing a result of infrared spectroscopy analysis of a silicon wafer surface.

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view of a substrate in each step of a local wiring forming method according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view of a pad portion of a substrate according to an embodiment using a silicide layer formed in the first and second embodiments as a contact pad.

FIG. 7 is an equivalent circuit diagram showing an example of an electronic circuit suitable for using local wiring.

FIG. 8 is a plan view illustrating a configuration of a semiconductor device that realizes the circuit in FIG.

FIG. 9 is a plan view illustrating a configuration of a semiconductor device that realizes the circuit in FIG. 7B;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 field oxide film 3 gate oxide film 4A, 4B gate electrode 4C polysilicon wiring 5A, 5B, 5C sidewall oxide region 6A, 6B source region 7A, 7B drain region 8 Co film 9 silicide layer 10 Ni film 11A 11B Polysilicon pattern 12 Resist mask 13A, 13B Ni silicide pattern 20A, 20B Active region 51 Substrate 52 Field oxide film 53 Gate oxide film 54 Gate electrode 55, 59 Side wall oxide region 56 Source region 57 Drain region 58 Silicon wiring 60 Co film 61 Pt film 62 Si film 63 Resist mask 64 TiN film 65, 66 Silicide film 71 Si substrate 72 Gate oxide film 73 Gate electrode 74 Side wall oxide region 75 a to 7 en type region 76 insulating film 77, 80 silicide film 78 interlayer insulating film 79, 81 wiring 83 field oxide film 100 substrate 101 field oxide film 102A, 102B active region 103AS, 103BS source region 103AD, 103BD drain region 104A, 104B gate electrode 104C amorphous silicon wiring 105A, 105B, 105C sidewall oxide region 106 titanium film 107 amorphous silicon film 108A, 108B silicide layer 109 interlayer insulating film 110 wiring

Claims (8)

[Claims] 1. A method comprising: contacting a surface of a silicon substrate with a solution containing a substance having a reducing property which can be dissolved by ionization and contains deuterated water (D ₂ O); A method for stabilizing the silicon surface to be terminated. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step is performed after the step of exposing the surface of the silicon substrate to a hydrofluoric acid solution containing deuterium. 3. A step of: (1) selectively adding a conductive impurity to the surface of the silicon substrate to form an impurity region; and (2) forming a contact with the impurity region.
Forming a conductive film on the impurity region, wherein before the step (1), heavy water (D ₂ O) is contained and ionized and dissolved. A method for manufacturing a semiconductor device, comprising: a silicon surface stabilizing step of bringing a surface of a silicon substrate into contact with a solution containing a substance having a property and terminating the surface of the silicon substrate with deuterium or hydrogen. 4. A method according to claim 1, wherein the step (1) and the step (2) include the step of adding a silicon substrate to a solution containing heavy water (D ₂ O) and containing an ionizable and reducible substance. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising a silicon surface stabilizing step of terminating the surface of the silicon substrate by deuterium termination or hydrogen termination by touching the surface. 5. A step of (1) selectively adding a conductive impurity to the surface of the silicon substrate to form an impurity region; and (2) forming a region so as to be in contact with the impurity region.
A method of manufacturing a semiconductor device, comprising: forming a conductive film on the impurity region, wherein between the step (1) and the step (2), heavy water (D ₂
O) by contacting the surface of the silicon substrate with a solution containing a substance having a reducing property that can be dissolved by ionization,
A method for manufacturing a semiconductor device, comprising a silicon surface stabilizing step of terminating the surface of the silicon substrate with deuterium or terminating with hydrogen. 6. The conductive film is a refractory metal,
6. The method according to claim 3, further comprising, after the step (2), a step of forming a refractory metal silicide between the conductive film and the silicon substrate. 7. The method according to claim 2, wherein the step (1) is performed after the step of exposing the surface of the silicon substrate to a hydrofluoric acid solution containing deuterium. 8. The substance having a reducing property is SO _{3
^{2-, I -, H 2 PO}} 2 2-, S 2 O 3 2-, N 2 H 5 +, COOH -, C 6
^{_{H 4 NH 2 NH 3 +,}} C 6 H 4 OHO -, C 6 H 4 O 2 2-, HPHO 3
^{_{-, PHO 3 2-, C 6}} H 3 C 4 H 9 OCH 3 OH - A method according to claim 1 to 7, wherein it is a member selected from either.