JP2002050195A - Memory evaluating system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory evaluating system which can obtain FBM required for defect analyzing and write-in data in a memory mat at the time of fail. SOLUTION: This system is a memory evaluating system in which selection is performed by a test being equivalent to a test of a memory module loaded in a PC, which can analyze a defective device, the system is constituted of a mother board 1 in which a reference device or the like is loaded, an evaluating board 2 in which ASIC or the like is loaded, a memory tester 3, or the like, test devices to be tested DUT1-DUT3 are inserted into sockets 7-9 for the device to be tested, devices DUTA, DUTB for obtaining FBM (for holding write-in data at the time of fail) being a normal product and the same product as a device to be tested are inserted into sockets 10, 11 for obtaining FBM (for holding write-in data at the time of fail), two pieces out of three pieces are selected, the FBM is simultaneously obtained for the DUTA, DUTB, also, write-in data at the time of fail of one piece out of three pieces is held in either of the DUTA, DUTB.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory evaluation technology, for example, a personal computer (Personal Computer: P).
The present invention relates to a technique that is effective when applied to a memory evaluation system suitable as an analysis function in a use process of a PC-mounted sorting device that performs sorting by a test equivalent to a memory module mounted in C).

[0002]

2. Description of the Related Art For example, as a PC-mounted sorting apparatus that performs sorting by a test equivalent to a memory module mounted on a PC, a technique previously filed by the present inventors (Japanese Patent Application No. 11-3).
No. 58305). This Japanese Patent Application No. 11-358305
In the technology of No. 1, a signal is extracted from a memory module mounted on a PC or the like, and a large number of devices to be inspected are connected to the point from which the signal is extracted. Memory test system. The pass / fail judgment is based on the output of the mounted memory product, and the output of the device under test is compared with the ASIC (Application Specification).
c Integrated Circuit).

[0003]

The inventors of the present invention have studied the technology of the memory test system as described above, and as a result, have found the following. For example, the memory test system can perform pass / fail determination of a device under test, but when the device under test is determined to be defective, information required for analyzing the defective device, for example, FBM (Fail) B
It is not considered to obtain it map) or write data at the time of a failure.

Accordingly, an object of the present invention is to utilize a method of comparing and judging the output of a device to be inspected and a reference device of a PC mounting and sorting apparatus, and to obtain FBM and write data in a memory mat at the time of a failure from this judgment result. An object of the present invention is to provide a memory evaluation system capable of constructing a mechanism capable of acquiring the FBM required for failure analysis and writing data in a memory mat at the time of a failure.

[0005] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A memory evaluation system according to the present invention further includes an FBM acquisition circuit and a write data holding circuit at the time of a failure added to the ASIC portion of the memory test system as described above, and a 1DUT (Device Under Test).
It is configured using a memory tester (not necessary to be a high-speed tester) capable of acquiring FBM for t).

That is, as an overall configuration of the memory evaluation system according to the present invention, a reference device (for example, a motherboard on which a memory module is mounted) including a control circuit for mounting a non-defective memory serving as a reference device and performing a read / write operation of the reference device. ASIC), an evaluation board, and a memory tester. On the evaluation board, an ASIC, a socket for a device under test, and an FBM acquisition socket are mounted. The memory of the device to be inspected is inserted into one of the sockets, and the memory of a good product of the same product as the device to be inspected is inserted into the other socket as a device for acquiring an FBM or holding write data at the time of a failure. The contents of the ASIC include an FBM acquisition circuit and a write data holding circuit at the time of a failure in addition to the pass / fail determination circuit of the memory test system.

In the above-mentioned memory evaluation system, the FBM
The mechanism for acquiring the write data in the device to be inspected at the time of a failure and the failure is as follows.

(A) FBM Acquisition Mechanism (Function of FBM Acquisition Circuit) When reading a device under test, the output (expected value) of the reference device and the output of the device under test are EXOR-determined at any time. The EXOR determination value is “L” when passing, and “H” when failing. Then, the read command input to the device under test is converted into a write command, and the FBM acquisition device is operated with the write data as the EXOR determination value. With this function, “H” data is written to the FBM acquisition device at the same address as the fail address of the device under test. Thereafter, if the memory tester reads the FBM acquisition device at the expected value “L” at a simple scan and at a low speed, the fail address of the device to be inspected can be obtained (a memory tester with low performance is possible).

(B) Acquisition of write data in the device under test at the time of failure Uses the latch output after the output determination (EXOR determination) of the reference device and the device under test. When the output determination latch of the device under test is “L” (pass), the device for holding write data at the time of failure (= device for acquiring FBM) operates in the same manner as the reference device (= device under test), and the output determination latch changes to “ H ”(fail)
Writing to the write data holding device at the time of failure is stopped. For this reason, the write-time data retention device retains the write data when the device under test fails. After that, with a memory tester,
By reading the write data holding device at the time of fail and acquiring the FBM, the write data in the mat at the time of the fail of the device to be inspected can be acquired.

In another memory evaluation system according to the present invention, a socket for a reference device is mounted on an evaluation board in addition to a socket for an ASIC and a device to be inspected and for obtaining an FBM. Good memory for the device, memory for the device under test
A good memory of the same product as the device to be inspected is inserted into another socket as an FBM acquisition device. The contents of the ASIC include a pass / fail determination circuit and an FBM acquisition circuit. Also, read the reference device into the memory tester /
It includes a control circuit for performing a write operation.

Therefore, according to the memory evaluation system, the following effects can be obtained.

(1) By adding two circuits of an FBM acquisition circuit and a fail-time write data holding circuit and an inexpensive memory tester to the memory test system on the premise, the FBM and fail-time write data patterns required for failure analysis are added. Information can be obtained.

(2) The following effects can be obtained by providing a device for acquiring an FBM or holding write data at the time of a failure. Fail bits can be stored, a fail memory can be added at a low cost (for a memory tester), and a plurality of devices under test can be simultaneously tested with one test pattern.
It is possible to obtain write data at the time of BM or failure.

(3) Other FBM acquisition methods (for example, AS
A method of latching an address in an IC)
C can be simplified.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a block diagram showing a memory evaluation system according to Embodiment 1 of the present invention. FIG. 2 is a block diagram showing a memory evaluation system according to this embodiment for FBM acquisition and write data retention at the time of a failure. FIG. 3 is a timing chart showing read command conversion of the device under test, and FIG. 4 is a timing diagram showing write command conversion of the device under test.

First, the configuration of an example of the memory evaluation system according to the present embodiment will be described with reference to FIG. The memory evaluation system according to the present embodiment is a system capable of performing selection by a test equivalent to a memory module mounted on a PC and analyzing a defective device, and a motherboard 1 serving as a reference device mounting a reference device and the like. And the ASIC, the device under test, and the FB
An evaluation board 2 mounted with a device for acquiring M or holding write data at the time of a failure, and a memory tester 3 connected to the evaluation board 2 and capable of acquiring an FBM. The clock signal (CLK), address, etc. And input / output data (I / O) can be input / output.

The motherboard 1 includes, for example, a non-defective memory module serving as a reference device 4 and a reference device 4.
PC that is a control circuit for reading / writing data
(Chip set LSI) 5 and the like. A clock signal (CLK), various signals such as addresses, input / output data (I / O), and the like are output from the reference PC 5 to the reference device 4 and the evaluation board 2.

The evaluation board 2 includes, for example, an ASIC 6
And three sockets 7 to 9 for devices to be inspected, two sockets 10 and 11 for FBM acquisition (shared with write data holding at the time of failure), and the like. The device under test DUT is provided in each of the device sockets 7 to 9
1 to DUT3 are inserted, and each FBM
A non-defective memory module of the same product as the device to be inspected is provided in the acquisition sockets 10 and 11 for FBM acquisition (shared with the write data holding device at the time of failure).
Inserted as UTB. The ASIC 6 includes a plurality of buffers and three EXOR gates EXOR1 to EXOR3.
A command / conversion circuit 12, two selectors (A) 13, (B) 14, a latch circuit 15, and a plurality of switches ASW1 to ASW.
3, BSW1 to BSW3, FSW1 to FSW3, DSW
A, DSWB, TSW1 to TSW3, TSWA, TSW
It is composed of an FBM acquisition circuit including B, a write data holding circuit at the time of failure, and the like.

The memory tester 3 has an FBM for one DUT.
And a function of acquiring a driver, a comparator, and an FBM for one DUT. Also, FB
M has no problem in its ability to only acquire at low speed.

In the memory evaluation system configured as described above, three devices to be inspected are taken (DUT1 to DUT1).
This is an example of the system of 3), in which a non-defective device for acquiring FBM or holding write data at the time of failure is inserted into DUTA and DUTB. By inserting non-defective products into both DUTA and DUTB, out of three (DUT1 to DUT3)
Can be selected and the two FBMs can be acquired simultaneously. In addition, one of DUTA and DUTB is 3
The write data in the mat at the time of one of the failures (DUT1 to DUT3) can be held.

Next, the configuration of an example of a command conversion circuit for acquiring an FBM and holding write data at the time of a failure will be described with reference to FIG.

The command conversion circuit 12 includes a decoder 21,
Write command generating circuit 22, Nop command generating circuit 23, two selectors & phase (timing) adjusting circuit 2
4, 25, two phase (timing) adjustment circuits 26, 2
7, a plurality of buffers and inverters, and a reference signal, reference data (I / O), and a fail latch signal are respectively input from input terminals, a command conversion output signal for FBM acquisition, a command for holding write data at the time of failure, A conversion output signal and a data (I / O) output signal for holding write data during a failure are output.

The decoder 21 receives the reference signal as an input,
The reference signal is decoded to output a write signal, a read signal, and other signals. The selector & phase adjustment circuit 24 for converting and outputting the command for FBM acquisition includes a reference signal, a write command, a nop command,
The decoded write, read, and other signals are input and converted into read (R) → write (W), write (W) → nop (Nop: Noperation), other → invariant, and command conversion output for FBM acquisition. Output a signal. The selector & phase adjustment circuit 25 for converting and outputting the write data retention command at the time of a failure receives a reference signal, a nop command, a decoded write, and other signals as inputs, and writes a write (W) → nop (No).
p), and others → unchanged, and outputs a command conversion output signal for holding write data at the time of failure.

In the command conversion circuit 12, the relationship between the command conversion output for holding write data at the time of fail, the data output for holding write data at the time of fail, and the input of the fail latch signal is as follows when the fail latch signal is "L" (Pa).
During ss), the operation is the same as that of the reference device. Upon receiving the fail latch signal “H” (Fail), the operation is performed so as to stop the subsequent writing to hold the write data at the time of fail.

Next, referring to FIGS. 3 and 4, read command conversion and write command conversion of the device under test will be described.

As shown in FIG. 3, in the read command conversion of the device under test, in the device under test, the read command Read is issued after the active command ACTV is issued in synchronization with the clock signal CLK, and the X address X
-Add, Y address Y-add, pass signal Pass, fail signal F as output data Dout
When “ail” is output, the EXOR determination value becomes “L” for the pass signal Pass and “H” for the fail signal Fail, respectively. Then, the read command is converted into a write command, and the FBM acquisition device issues a write command Wri after issuing an active command ACTV in synchronization with a clock signal CLK by phase (timing) adjustment.
When te is issued, a fail signal Fai based on the EXOR determination value of the device under test is input data Din by designating the X address X-add and the Y address Y-add.
1 is input and "H" data is written to the failed address.

As shown in FIG. 4, in the write command conversion of the device under test, the device under test issues a write command Write after the issuance of the active command ACTV in synchronization with the clock signal CLK, and the X address X-add, By specifying the Y address Y-add, data Data is input as input data Din. Then, it converts the write command into a nop command, and
The acquisition device issues a nop command NOP after issuing the active command ACTV in synchronization with the clock signal CLK based on the phase (timing) adjustment, so that a value other than the determination value at the time of reading the device under test is not written as input data Din. To

Next, the operation of the present embodiment will be described with reference to FIGS.
(B) Each operation of holding write data at the time of failure will be described.

(A) Example of actual operation of FBM acquisition (device under test is SDRAM (Synchronous DR)
AM) and DIMM (Dual In-line M)
memory module), device under test DUT
1, when the FBM of the DUT 3 is obtained simultaneously) (1) The input enable terminal is “L” (disabled), the switches TSW1 to TSW3 are turned off, the switches TSWA and TSWB are turned on, and the FBM obtaining device is obtained from the memory tester 3. "0" is written in all address spaces only for DUTA and DUTB. This is the pre-processing of the FBM acquisition devices DUTA and DUTB.

(2) Switches ASW1 and BSW3 Total 2
The switches are turned on and the remaining switches are turned off.

(3) Both the selectors (A) 13 and (B) 14 select an FBM acquisition command conversion output. In other words, the FBM of the device under test DUT1 is represented by the device DUTA for acquiring FBM, and the FBM of the device
Each is assigned to the BM acquisition device DUTB.

(4) The input enable terminal is set to “H” (enable), and the reference device 4 is tested by the reference PC 5.

(5) During execution of the test, the same pattern is input to the reference device 4 and the devices under test DUT1 to DUT3, and the EXOR determination of the devices under test DUT1 to DUT3 is performed as needed using the output of the reference device 4 as an expected value. . Also, for the FBM acquisition device DUTA,
The command conversion circuit 12 performs the conversion as shown in FIGS. 3 and 4, and writes “1” data only to the fail address generated in the device under test DUT1. FBM
Similarly, for the acquisition device DUTB, “1” is set only in the fail address generated in the device under test DUT3.
Data is written.

(6) When the test is completed, the input enable terminal is set to “L” (disabled) and the switch TSW
A is turned on, and the FBM acquisition device DUTA is read from the memory tester 3 with the expected value “0”, so that the FBM of the device under test DUT1 can be acquired. Similarly, switch TSWA is turned off and switch TSWB is turned off.
By setting N, the FBM of the device under test DUT3 can be obtained.

It should be noted that, for the three devices under test DUT1 to DUT3 on the evaluation board 2, the FBM acquisition devices DUTA and DUTB are separated by a switch or the like while the FBM is acquired by the memory tester 3 one by one. Then, the FBMs of the three devices under test DUT1 to DUT3 can be acquired simultaneously with one test pattern.

(B) Example of actual operation of obtaining write data in the mat at the time of failure (FBM of device under test DUT1)
(1) The input enable terminal is “L” (disabled), the switches TSW1 to TSW3 are turned off, the switches TSWA and TSWB are turned on, and the FBM acquisition device DUTA is obtained from the memory tester 3. , DUTB are written in all address spaces. This is the pre-processing of the FBM acquisition devices DUTA and DUTB.

(2) Switches ASW1, BSW3, FS
The three switches W1 are turned on, and the remaining switches are turned off.

(3) The selector (A) 13 selects the command conversion output for FBM acquisition, and the selector (B) 14 selects the command conversion output for holding write data at the time of failure. That is, the FBM of the device under test DUT1 and the device DU of FBM acquisition are added to the FBM acquisition device DUTA.
The write data at the time of the failure of the device under test DUT1 is held in the TB.

(4) The input enable terminal is set to “H” (enable), and the reference device 4 is tested by the reference PC 5.

(5) During the test, "1" data is written into the FBM acquisition device DUTA only at the fail address generated in the device under test DUT1. For the FBM acquisition device DUTB, while the device under test DUT1 passes, the device under test DUT1
Is written to the device under test DUT1.
And the subsequent writing is stopped at the same time as the failure. For this reason, the FBM acquisition device DUTB can hold the write data in the mat at the time of the failure of the device under test DUT1.

(6) When the test is completed, the input enable terminal is set to “L” (disabled) and the switch TSW
A is turned on, and the FBM acquisition device DUTA is read from the memory tester 3 with the expected value “0”, so that the FBM of the device under test DUT1 can be acquired. Similarly, switch TSWA is turned off and switch TSWB is turned off.
N, the write data in the mat at the time of a failure of the device under test DUT1 can be obtained.

Therefore, according to the memory evaluation system of the present embodiment, the evaluation board 2 equipped with the ASIC 6 including the FBM acquisition circuit and the write data holding circuit at the time of failure, the memory tester 3 capable of acquiring the FBM, etc. With this, it is possible to obtain the FBM and the write data pattern at the time of failure required for failure analysis. Also, FB
By providing M acquisition devices (devices for holding write data at the time of failure) DUTA and DUTB, fail bits can be stored, and fail memories can be added at a low cost (for a memory tester).
If n FBM acquisition devices are inserted into a plurality of devices to be inspected, n
The FBMs of the devices to be inspected can be obtained. Further, the ASIC 6 can be simplified as compared with the case where the FBM is acquired by using, for example, a method of latching an address in the ASIC 6.

(Embodiment 2) FIG. 5 is a configuration diagram showing a memory evaluation system according to Embodiment 2 of the present invention. As in the first embodiment, the memory evaluation system according to the present embodiment is a system capable of performing selection by a test equivalent to a memory module mounted on a PC, for example, and analyzing a defective device. The difference from the first embodiment is that a socket for a reference device is mounted on an evaluation board in addition to an ASIC, a socket for a device under test, and a socket for obtaining an FBM, and a pass / fail determination circuit and an FB
An M acquisition circuit is provided, and the memory tester includes a control circuit for performing a read / write operation of the reference device.

That is, the memory evaluation system according to the present embodiment comprises an evaluation board 2a on which an ASIC, a reference device, a device under test, and a device for FBM acquisition are mounted.
And a memory tester 3a connected to the evaluation board 2a and capable of acquiring an FBM.
dd) and input / output data (I / O).

The evaluation board 2a includes, for example, an ASIC 6
a, one reference device socket 31, three DUT sockets 7a to 9a, two FBM acquisition sockets 10a and 11a, and the like. The reference device socket 31 has a good reference device DU.
TR, device under test DUT1 to DUT3, socket 1 for FBM acquisition are provided in sockets 7a to 9a for device under test.
0a and 11a are non-defective F of the same product as the device under test.
The memory modules of the BM acquisition devices DUTA and DUTB are respectively inserted. ASIC6a is FPGA
(Field Programmable Gate A
rray), a plurality of buffers and three EXs
Path consisting of OR gates EXOR1 to EXOR3 /
Fail determination circuit, FBM circuit 32, latch circuit 3
3 and a plurality of switches ASW1 to ASW3, BSW1
To BSW3, CSW1 to CSW3, DSW1, DSW2
And the like.
The FBM circuit 32 has a function similar to that of the command conversion circuit of the first embodiment, and converts a read command to a write command, a write command to a nop command, and a phase (timing).
It has an adjustment function and the like.

The memory tester 3a has an FB for one DUT.
It is only necessary to have a function of acquiring M and to have a driver, a comparator, and an FBM acquiring capability for one DUT. The memory tester 3a includes a control circuit for performing read / write operations on the reference device DUTR. The memory tester 3a supplies various signals such as an address (add) and input / output data (I / O) to the ASIC 6a.
Can be input and output.

In the memory evaluation system configured as described above, three devices to be inspected are taken (DUT1 to DUT1).
3) This is an example of a system in which a good reference device for outputting an expected value is inserted into DUTR, and DUTA and DUTB are inserted.
, A non-defective device of the FBM acquisition device is inserted. DUT
By inserting non-defective products into both A and DUTB, two out of three (DUT1 to DUT3) are selected, and the two F
It is possible to acquire BM at the same time.

Next, the operation of the present embodiment will be described.
(A) The operation of FBM acquisition will be described.

(A) Example of actual operation of FBM acquisition (when a device under test acquires a DIMM by SDRAM and an FBM of devices under test DUT1 and DUT3 simultaneously) (1) Switches DSW1, CSW1, ASW1 to ASW
3, a total of eight switches BSW1 to BSW3 are turned off,
The switches CSW2, CSW3, and DSW2 are turned on, and the memory tester 3a writes "0" to the entire address space only for the FBM acquisition devices DUTA and DUTB. This is the pre-processing of the FBM acquisition devices DUTA and DUTB.

(2) Switches DSW1, CSW1, AS
The four switches W1 and BSW3 are turned on, and the remaining switches are turned off. That is, the device under test D
The FBM of UT1 is an FBM acquisition device DUTA, and the FBM of device under test DUT3 is an FBM acquisition device D.
Assign to each UTB.

(3) The test pattern is executed by the memory tester 3a. Further, the output judgment by the memory tester 3a is unnecessary.

(4) During execution of the test pattern, the same pattern is input to the reference device DUTR and the devices under test DUT1 to DUT3, and the EX of the devices under test DUT1 to DUT3 is used as the expected value of the output of the reference device DUTR.
An OR determination is made as needed. Also, for the FBM acquisition device DUTA, the FBM circuit 32 shown in FIG.
4 is performed, and "1" data is written only in the fail address generated in the device under test DUT1. Similarly, "1" data is written only to the fail address generated in the device under test DUT3 for the FBM acquisition device DUTB.

(5) In the case of a failure, the latch circuit 33
Devices under test DUT1 through DUT
3 identification signal (DUT1Fail to DUT3Fail)
Is output.

(6) When the test pattern is completed,
Switches DSW1, CSW1, ASW1 to ASW3, B
SW1 to BSW3, CSW3, 9 switches in total
F, the switches CSW2 and DSW2 are turned on, and the FBM acquisition device DUTA is read from the memory tester 3a with the expected value “0” to acquire the FBM of the device under test DUT1. Similarly,
By turning off the switch CSW2 and turning on the switch CSW3, the FBM of the device under test DUT3 can be acquired.

Therefore, according to the memory evaluation system of the present embodiment, the ASIC 6a including the FBM acquisition circuit and the like
The FBM required for failure analysis can be obtained by having the evaluation board 2a on which the device is mounted and the memory tester 3a capable of obtaining the FBM. Further, by providing the FBM acquisition devices DUTA and DUTB, it is possible to accumulate fail bits, and to add a fail memory at a low cost (for a memory tester). , N devices for FBM acquisition, FBMs of n devices under test can be acquired simultaneously in one test pattern. Further, the ASIC 6a can be simplified as compared with the case where the FBM is acquired by using, for example, a method of latching an address in the ASIC 6a.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, P
In the above description, a case is described in which a selection is performed by a test equivalent to a memory module such as a DIMM mounted on C and a memory evaluation system capable of analyzing a defective device is applied.
IMM (Single In-line Memory)
The present invention can be applied to analysis of other memory modules such as an external memory module and a defective device of a single memory.
It goes without saying that the present invention can be widely applied to RAM, SRAM, and the like.

Although the present invention is effective for a PC-mounted sorting apparatus, it can be further applied to a hardware system of a memory tester. For example, a reference signal is taken out from the memory tester, and the ASIC performs signal distribution and pass / fail determination. At the same time, FB
Since the fail bit is stored in the M acquisition device, an FBM can be obtained by reading the fail bit with a memory tester.

[0062]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) Since an evaluation board equipped with an ASIC including an FBM acquisition circuit and a write data holding circuit at the time of failure and a memory tester capable of acquiring an FBM are provided, an inexpensive memory tester can be used for failure analysis. Necessary FBM and information on the write data pattern at the time of failure can be acquired.

(2) An evaluation board equipped with an FBM acquisition or fail-time write data holding socket for inserting a non-defective memory of the same product as the device under test as an FBM acquisition device or a fail-time write data holding device. This makes it possible to accumulate fail bits, add a fail memory at a low cost (for a memory tester), and obtain FBM of a plurality of devices to be inspected and write data at the time of a failure simultaneously with one test pattern. Becomes possible.

(3) According to the above (1) and (2), the ASIC mounted on the evaluation board can be simplified as a method of acquiring the FBM of a plurality of devices under test and write data at the time of failure.

(4) According to the above (1) and (2), information necessary for failure analysis can be easily obtained.
T can be shortened.

(5) According to the above (1) and (2), the burden on the high-speed memory tester used for memory product selection and failure analysis can be reduced, and on the other hand, the low-speed memory tester can be used. The cost of tester investment can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a memory evaluation system according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a command conversion circuit for acquiring an FBM and holding write data during a failure in the memory evaluation system according to the first embodiment of the present invention;

FIG. 3 is a timing chart showing read command conversion of a device under test in the memory evaluation system according to the first embodiment of the present invention;

FIG. 4 is a timing chart showing write command conversion of a device under test in the memory evaluation system according to the first embodiment of the present invention;

FIG. 5 is a configuration diagram illustrating a memory evaluation system according to a second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Motherboard 2, 2a Evaluation board 3, 3a Memory tester 4 Reference device 5 Reference PC 6, 6a ASIC 7-9, 7a-9a Socket for device under test 10, 11, 10a, 11a Socket for FBM acquisition 12 Command conversion circuit 13 , 14 selector 15 latch circuit 21 decoder 22 write command generation circuit 23 nop command generation circuit 24, 25 selector & phase adjustment circuit 26, 27 phase adjustment circuit 31 reference device socket 32 FBM circuit 33 latch circuit DUT1 to DUT3 device under test DUTA, DUTB FBM acquisition device EXOR1 to EXOR3 EXOR gate ASW1 to ASW3, BSW1 to BSW3, FSW1
FSW3, DSWA, DSWB, TSW1 to TSW3
TSWA, TSWB, CSW1 to CSW3, DSW1,
DSW2 Switch DUTR Reference Device

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hideyuki Aoki 5-2-1, Kamimizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 2G032 AA07 AC03 AE07 AE08 AE10 AE11 AG07 AH01 AH04 AK16 5B018 GA03 HA01 NA01 QA13 5L106 DD24 EE02

Claims (5)

[Claims] A reference device including a control circuit for mounting a non-defective memory serving as a reference device and performing a read / write operation of the reference device, a pass / fail determination circuit, an FBM acquisition circuit, and a write data holding circuit at the time of failure. An ASIC that includes a device-under-test socket and an FBM acquisition or fail-time write data holding socket; and a memory tester that can acquire an FBM. Inserting a memory of a device and inserting a non-defective memory of the same product as the device to be inspected into the socket for holding the FBM or holding write data at the time of fail as the device for holding FBM or holding the write data at the time of fail; Before the FBM of the device under test by the acquisition circuit A memory evaluation system for acquiring the FBM acquisition device, and acquiring the fail write data of the device under test by the fail write data holding circuit by the fail write data holding circuit. 2. The memory evaluation system according to claim 1, wherein when the FBM acquisition circuit acquires the FBM of the device under test by the device for FBM acquisition, the reference is used when reading the device under test. Means for EXOR-determining the output of the device and the output of the device under test, converting the read command input to the device under test into a write command, and operating the device for FBM acquisition using the write data as the EXOR determination value Means for causing the memory tester to scan and read the FBM acquisition device with an expected value “L” to acquire a fail address of the device under test. 3. The memory evaluation system according to claim 1, wherein the fail-time write data holding circuit acquires fail-time write data of the device under test to the fail-time write data holding device. Means for latching the output after the EXOR judgment of the reference device and the device under test, and means for stopping the writing to the write data holding device at the time of failure after the output judgment latch of the device under test becomes "H" Means for reading the write data holding device at the time of fail by the memory tester to obtain an FBM, and acquiring write data in the mat at the time of the fail of the device under test. Evaluation system. 4. The memory evaluation system according to claim 1, wherein the memory tester is a low-speed tester capable of acquiring an FBM for one DUT. 5. An ASIC including a pass / fail determination circuit and an FBM acquisition circuit, an evaluation board equipped with a socket for a reference device, a socket for a device under test, and a socket for FBM acquisition, and control for performing read / write operations on the reference device. A memory tester including a circuit, capable of acquiring an FBM, inserting the reference device, which is a non-defective memory, into the reference device socket, and inserting the memory of the device under test into the socket for the device under test. A non-defective memory of the same product as the device under test is inserted into the socket for FBM acquisition as a device for FBM acquisition, and the FBM of the device under test is replaced by the FBM by the FBM acquisition circuit.
A memory evaluation system obtained by an acquisition device.