JP2002049652A - デジタル回路設計方法、そのコンパイラーおよびシミュレータ - Google Patents
デジタル回路設計方法、そのコンパイラーおよびシミュレータInfo
- Publication number
- JP2002049652A JP2002049652A JP2000236286A JP2000236286A JP2002049652A JP 2002049652 A JP2002049652 A JP 2002049652A JP 2000236286 A JP2000236286 A JP 2000236286A JP 2000236286 A JP2000236286 A JP 2000236286A JP 2002049652 A JP2002049652 A JP 2002049652A
- Authority
- JP
- Japan
- Prior art keywords
- unit
- line
- register
- variable
- digital circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S707/00—Data processing: database and file management or data structures
- Y10S707/99941—Database schema or data structure
- Y10S707/99942—Manipulating data structure, e.g. compression, compaction, compilation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000236286A JP2002049652A (ja) | 2000-08-03 | 2000-08-03 | デジタル回路設計方法、そのコンパイラーおよびシミュレータ |
| US09/917,283 US6578187B2 (en) | 2000-08-03 | 2001-07-24 | Digital circuit design method using programming language |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000236286A JP2002049652A (ja) | 2000-08-03 | 2000-08-03 | デジタル回路設計方法、そのコンパイラーおよびシミュレータ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002049652A true JP2002049652A (ja) | 2002-02-15 |
| JP2002049652A5 JP2002049652A5 (enExample) | 2005-09-08 |
Family
ID=18728354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000236286A Pending JP2002049652A (ja) | 2000-08-03 | 2000-08-03 | デジタル回路設計方法、そのコンパイラーおよびシミュレータ |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6578187B2 (enExample) |
| JP (1) | JP2002049652A (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004036463A1 (ja) * | 2002-10-15 | 2004-04-29 | Renesas Technology Corp. | コンパイラ及び論理回路の設計方法 |
| KR100965856B1 (ko) | 2009-12-04 | 2010-06-24 | 주식회사 모뎀게이트 | 순차 실행 고급 프로그래밍 언어를 이용한 디지털 집적 회로 설계, 시뮬레이션 및 검증 방법 및 시스템 |
Families Citing this family (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6597664B1 (en) * | 1999-08-19 | 2003-07-22 | Massachusetts Institute Of Technology | Digital circuit synthesis system |
| US6625798B1 (en) * | 2000-07-25 | 2003-09-23 | Hewlett-Packard Development Company, L.P. | Method for translating conditional expressions from a non-verilog hardware description language to verilog hardware description language while preserving structure suitable for logic synthesis |
| US6792580B2 (en) * | 2001-01-31 | 2004-09-14 | Kabushiki Kaisha Toshiba | Method and computer program product for software/hardware language model conversion |
| US7266489B2 (en) * | 2003-04-28 | 2007-09-04 | International Business Machines Corporation | Method, system and program product for determining a configuration of a digital design by reference to an invertible configuration database |
| US7062746B2 (en) | 2003-04-28 | 2006-06-13 | International Business Machines Corporation | Method, system and program product that utilize a configuration database to configure a hardware digital system having multiple access methods |
| US7080347B2 (en) * | 2003-04-28 | 2006-07-18 | International Business Machines Corporation | Method, system and program product for specifying a configuration of a digital system described by a hardware description language (HDL) model |
| US7168061B2 (en) * | 2003-04-28 | 2007-01-23 | International Business Machines Of Corporation | Method, system and program product for implementing a read-only dial in a configuration database of a digital design |
| US7080346B2 (en) * | 2003-04-28 | 2006-07-18 | International Business Machines Corporation | Method, system and program product for automatically transforming a configuration of a digital system utilizing traceback of signal states |
| US7134098B2 (en) * | 2003-04-28 | 2006-11-07 | International Business Machines Corporation | Method, system and program product for specifying a configuration for multiple signal or dial instances in a digital system |
| US7162404B2 (en) * | 2003-04-28 | 2007-01-09 | International Business Machines Corporation | Method, system and program product for configuring a simulation model of a digital design |
| US7146302B2 (en) | 2003-04-28 | 2006-12-05 | International Business Machines Corporation | Method, system and program product that utilize a configuration database to configure a hardware digital system having an arbitrary system size and component set |
| US7039894B2 (en) * | 2003-04-28 | 2006-05-02 | International Business Machines Corporation | Method, system and program product for specifying and using dials having phased default values to configure a simulated or physical digital system |
| US6993729B2 (en) * | 2003-04-28 | 2006-01-31 | International Business Machines Corporation | Method, system and program product for specifying a dial group for a digital system described by a hardware description language (HDL) model |
| US7062745B2 (en) * | 2003-04-28 | 2006-06-13 | International Business Machines Corporation | Method, system and program product for specifying and using a dial having a default value to configure a digital system described by a hardware description language (HDL) model |
| US7143387B2 (en) * | 2003-08-28 | 2006-11-28 | International Business Machines Corporation | Method, system and program product providing a configuration specification language that supports the definition of links between configuration constructs |
| CN100378735C (zh) * | 2003-12-31 | 2008-04-02 | 国际商业机器公司 | 指定具有阶段缺省值的标度盘配置数字系统的方法和系统 |
| US7620942B1 (en) * | 2004-05-20 | 2009-11-17 | Xilinx, Inc. | Method and system for parameterization of imperative-language functions intended as hardware generators |
| US7213225B2 (en) | 2004-05-28 | 2007-05-01 | International Business Machines Corporation | Method, system and program product for specifying and using register entities to configure a simulated or physical digital system |
| US7856094B2 (en) | 2005-03-21 | 2010-12-21 | Tekelec | Methods, systems, and computer program products for providing telecommunications services between a session initiation protocol (SIP) network and a signaling system 7 (SS7) network |
| US7716608B2 (en) * | 2005-06-01 | 2010-05-11 | Massachusetts Institute Of Technology | Circuit synthesis with sequential rules |
| US7783467B2 (en) * | 2005-12-10 | 2010-08-24 | Electronics And Telecommunications Research Institute | Method for digital system modeling by using higher software simulator |
| US8050253B2 (en) * | 2006-01-09 | 2011-11-01 | Tekelec | Methods, systems, and computer program products for decentralized processing of signaling messages in a multi-application processing environment |
| US7434193B2 (en) * | 2006-02-02 | 2008-10-07 | International Business Machines Corporation | Method, system and program product for specifying a configuration for a digital system utilizing dial biasing weights |
| US20080092113A1 (en) * | 2006-10-12 | 2008-04-17 | Weinstein Randall K | System and method for configuring a programmable electronic device to include an execution engine |
| US8059667B2 (en) * | 2007-01-31 | 2011-11-15 | Tekelec | Methods, systems, and computer program products for applying multiple communications services to a call |
| US20080285438A1 (en) * | 2007-04-20 | 2008-11-20 | Rohini Marathe | Methods, systems, and computer program products for providing fault-tolerant service interaction and mediation function in a communications network |
| JP5187308B2 (ja) * | 2007-08-01 | 2013-04-24 | 日本電気株式会社 | 変換プログラム探索システムおよび変換プログラム探索方法 |
| US9712341B2 (en) | 2009-01-16 | 2017-07-18 | Tekelec, Inc. | Methods, systems, and computer readable media for providing E.164 number mapping (ENUM) translation at a bearer independent call control (BICC) and/or session intiation protocol (SIP) router |
| GB201522216D0 (en) | 2015-12-16 | 2016-01-27 | Lambda Logic Ltd | System and method for the design of digital hardware |
| US11847207B2 (en) * | 2019-03-04 | 2023-12-19 | Microsoft Technology Licensing, Llc | Security-adaptive code execution |
| CN112818616B (zh) * | 2021-01-15 | 2024-03-12 | 珠海泰芯半导体有限公司 | 管脚命名方法、寄存器激励源添加方法及电子装置 |
| CN116895325B (zh) * | 2023-06-21 | 2024-05-07 | 合芯科技有限公司 | 数字阵列寄存器的icg分类方法、测试方法及分类装置 |
Family Cites Families (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5355496A (en) * | 1992-02-14 | 1994-10-11 | Theseus Research, Inc. | Method and system for process expression and resolution including a generally and inherently concurrent computer language |
| SE505783C2 (sv) * | 1995-10-03 | 1997-10-06 | Ericsson Telefon Ab L M | Förfarande för att tillverka en digital signalprocessor |
| US5870585A (en) * | 1995-10-10 | 1999-02-09 | Advanced Micro Devices, Inc. | Design for a simulation module using an object-oriented programming language |
| US6035106A (en) * | 1997-04-28 | 2000-03-07 | Xilinx, Inc. | Method and system for maintaining hierarchy throughout the integrated circuit design process |
| GB2317245A (en) * | 1996-09-12 | 1998-03-18 | Sharp Kk | Re-timing compiler integrated circuit design |
| US6053947A (en) * | 1997-05-31 | 2000-04-25 | Lucent Technologies, Inc. | Simulation model using object-oriented programming |
| US6152612A (en) * | 1997-06-09 | 2000-11-28 | Synopsys, Inc. | System and method for system level and circuit level modeling and design simulation using C++ |
| US5966534A (en) * | 1997-06-27 | 1999-10-12 | Cooke; Laurence H. | Method for compiling high level programming languages into an integrated processor with reconfigurable logic |
| US6083269A (en) * | 1997-08-19 | 2000-07-04 | Lsi Logic Corporation | Digital integrated circuit design system and methodology with hardware |
| US6226776B1 (en) * | 1997-09-16 | 2001-05-01 | Synetry Corporation | System for converting hardware designs in high-level programming language to hardware implementations |
| US6292765B1 (en) * | 1997-10-20 | 2001-09-18 | O-In Design Automation | Method for automatically searching for functional defects in a description of a circuit |
| US6075935A (en) * | 1997-12-01 | 2000-06-13 | Improv Systems, Inc. | Method of generating application specific integrated circuits using a programmable hardware architecture |
| US6421815B1 (en) * | 1998-01-09 | 2002-07-16 | Synopsys, Inc. | Method and apparatus for optimized partitioning of finite state machines synthesized from hierarchical high-level descriptions |
| US6421808B1 (en) * | 1998-04-24 | 2002-07-16 | Cadance Design Systems, Inc. | Hardware design language for the design of integrated circuits |
| US6226777B1 (en) * | 1998-11-25 | 2001-05-01 | Agilent Technologies, Inc. | Method and system for improving the performance of a circuit design verification tool |
| US20020104073A1 (en) * | 1998-12-08 | 2002-08-01 | Sanjiva Weerawarana | Component oriented programming (cop) language |
| US6298472B1 (en) * | 1999-05-07 | 2001-10-02 | Chameleon Systems, Inc. | Behavioral silicon construct architecture and mapping |
| US6374403B1 (en) * | 1999-08-20 | 2002-04-16 | Hewlett-Packard Company | Programmatic method for reducing cost of control in parallel processes |
| US6324680B1 (en) * | 1999-08-30 | 2001-11-27 | International Business Machines Corporation | Synthesis of arrays and records |
| US20020138244A1 (en) * | 1999-09-30 | 2002-09-26 | Meyer Steven J. | Simulator independent object code HDL simulation using PLI |
| JP2002073719A (ja) * | 2000-08-31 | 2002-03-12 | Hitachi Ltd | 回路動作モデル記述の生成方法および論理設計検証装置 |
| US7058562B2 (en) * | 2001-03-03 | 2006-06-06 | Hewlett-Packard Development Company, L.P. | Apparatus and method for performing event processing in a mixed-language simulator |
| US6985842B2 (en) * | 2001-05-11 | 2006-01-10 | International Business Machines Corporation | Bidirectional wire I/O model and method for device simulation |
-
2000
- 2000-08-03 JP JP2000236286A patent/JP2002049652A/ja active Pending
-
2001
- 2001-07-24 US US09/917,283 patent/US6578187B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004036463A1 (ja) * | 2002-10-15 | 2004-04-29 | Renesas Technology Corp. | コンパイラ及び論理回路の設計方法 |
| KR100965856B1 (ko) | 2009-12-04 | 2010-06-24 | 주식회사 모뎀게이트 | 순차 실행 고급 프로그래밍 언어를 이용한 디지털 집적 회로 설계, 시뮬레이션 및 검증 방법 및 시스템 |
Also Published As
| Publication number | Publication date |
|---|---|
| US6578187B2 (en) | 2003-06-10 |
| US20020108092A1 (en) | 2002-08-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050311 |
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| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060221 |
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| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060404 |
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| A02 | Decision of refusal |
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