JP2002049359A - Active matrix liquid crystal display element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a driving circuit-integrated type liquid crystal display element whose panel frame size is suppressed to the minimum while holding high display quality and also whose power consumption is low in a driving circuit- integrated type liquid crystal display panel. SOLUTION: In this display element, a horizontal scanning circuit is made to be blocks of a number equivalent to the number of the division of data lines and data signals are inputted independently for every block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called drive circuit integrated type liquid crystal display device in which an internal drive circuit is integrally formed on a glass substrate by using a polysilicon process or the like.

[0002]

2. Description of the Related Art In recent years, in order to reduce the cost and increase the reliability of a liquid crystal display device, a drive circuit integrated type liquid crystal display device in which an internal drive circuit is integrally formed on a glass substrate using a polysilicon process has been developed. Is being actively conducted.

This type of device has a disadvantage that the size of a drive circuit is increased because the performance of a transistor formed using a polysilicon process is inferior to the performance of a transistor formed on single crystal silicon. A simple driving circuit mainly for point-sequential driving is currently widely used. However, the point-sequential driving method is not suitable for a large-sized liquid crystal display device having a large number of pixels because the time for writing data to the liquid crystal is originally short.

On the other hand, in recent years, studies have been made to apply a liquid crystal display element integrated with a drive circuit to a large-sized liquid crystal display element. For this purpose, data writing such as that used in a general liquid crystal driving driver IC is required. It is necessary to employ a digital line-sequential drive circuit that can take a sufficient time. In the case of this system, a so-called D / A converter for converting an input digital signal into an analog signal is required. D / A converter
There are several types of data types, for example, R-2R ladder
A method using a resistor as a weighting element, such as a type D / A converter, is commonly used as a general-purpose IC.

[0005]

However, when a digital line sequential driving circuit is used for a liquid crystal display element integrated with a driving circuit using a polysilicon process or the like, the driving capability of the thin film transistor element is insufficient and the circuit scale is large. As a result, restrictions on the method of arranging the thin film transistor element and the wiring are increased, and as a result, a problem occurs that the wiring becomes longer than necessary, which causes an increase in wiring delay. A specific restriction on the arrangement is that basically, the horizontal scanning drive circuit requires several columns (also referred to as source lines or image signal lines) and one column drive circuit requires one column.
This is due to the fact that one drive circuit must be vertically elongated because it is necessary to arrange the pixel within a very narrow width of the pixel.

The present invention has been made in view of this point, and by devising the arrangement of the horizontal scanning circuit and the arrangement of the wiring,
An object of the present invention is to realize a drive circuit integrated type active matrix liquid crystal display element with a low power consumption while suppressing the panel frame size to a minimum while maintaining high display quality.

[0007]

According to the present invention, an active matrix type liquid crystal display device integrated with a driving circuit has a horizontal scanning circuit arrangement and a wiring arrangement for minimizing a panel frame size and power consumption. It has been devised.

According to the present invention, the horizontal scanning circuit is divided into blocks corresponding to the number of data line divisions, and the data is independently obtained for each block.
Data signal.

Here, for example, consider a case where digital data is divided into four parts. In the case of the line-sequential driving method, the number of data divisions is a dot period automatically determined by the number of pixels, and
It is determined by the performance of the thin film transistor constituting the horizontal scanning circuit. Since the performance of a thin film transistor made of polysilicon or the like is inferior to that of a MOS transistor made of single crystal silicon, it is necessary to divide a data line and perform parallel transfer so that a longer period of writing to a latch circuit can be taken. is there.

Here, the number of data lines is required to be 18 for 6 bits × 3 RGB even if there is no division, and it is necessary to further increase the number of data lines to 72 for four divisions. In this case, normally, data from the data line of the first division is written in order from the data latch circuit corresponding to the first pixel (including RGB) at the left end, and 2nd data is written to the second pixel on the right. Data from the data line of the division is written, and when the fourth division is reached, the process returns to the first division again, and by repeating this, data is written to all the pixels. However, in this case, all 72 data lines are arranged in the horizontal direction with respect to the horizontal scanning circuit in the entire area, and the line spacing / line width directly affects the circuit size in the vertical direction. Is increased. Further, the power consumption increases due to the large cross capacitance between the data lines.

On the other hand, in the case of the method of the present invention, the horizontal scanning circuit is divided into blocks by the number of data line divisions, and a data signal is input independently for each block. In order to write all the data from the first division data line and to write all the pixels in the second block from the second division data line, the size of the horizontal scanning circuit corresponding to the first block is set. (1) Since only the data line of the first division is affected and the cross capacity is reduced, both the frame and the power consumption can be reduced. However, in order to perform such a method, it is necessary to rearrange the data at the stage of the external circuit before inputting the data to the horizontal scanning circuit, and the power consumption increases by that amount. In comparison, power consumption is reduced by using the method of the present invention.

On the other hand, when the method of the present invention is used, there is a concern about unevenness in image quality near a joint between blocks when divided into blocks. As a countermeasure against this, the block is further divided into two parts at the center and arranged at a certain area, and the data is vertically arranged from above in an empty area at the center.
Input lines such as data lines, latch pulse lines, and power supply lines,
Further, by arranging the input wirings in the left and right lateral directions, it is effective to make the image quality deterioration at the end of the block difficult to see.

In the present invention, further, among the horizontal scanning circuits,
A unit for driving one pixel, comprising a data latch circuit and a D / A converter circuit, is arranged within a width corresponding to two pixels, and the units are vertically stacked in two stages in a vertical direction. By arranging it as a structure, the frame is narrowed and the power consumption is reduced. The processing dimension when patterning the array substrate constituting the liquid crystal panel is coarser than that of the semiconductor chip, and the width of one pixel is as long as one thin film transistor element is included in a CMOS structure in a CMOS structure. There is only. For this reason, there is a restriction on how to route the wires connecting the elements, and the number of cross portions between the wires is increased more than necessary, and the area occupied by the wiring portions is increased. Therefore, when the width is doubled and vertically stacked, both the size and the power can be reduced as a result.

In addition, as a countermeasure against the reduction of the frame size according to the present invention, a pair of positive-phase and negative-phase output wirings corresponding to one stage of the shift register circuit is occupied by the entire unit that the shift register circuit simultaneously latches. In the direction area, wiring is performed in a vertical direction at a pair ratio, and further from the respective positions in the vertical direction where the data latch circuit corresponding to each bit is arranged, wiring is further performed in the horizontal direction, and power supply lines and grounds are provided. The wires are wired in the horizontal direction at the upper or lower end of the unit, and the wires are wired in a vertical direction at a pair ratio in the horizontal area occupied by a certain number of units, and the arrangement of the inverter elements and the like constituting the unit is arranged. It is effective to perform wiring in the horizontal direction from each of the vertical positions.

Here, the method of the present invention is used as a method of wiring output lines from the shift register,
Unnecessary cross capacity,
In order to further reduce the area occupied by the wiring, among a plurality of units that respectively drive a plurality of adjacent pixels, a plurality of units that are simultaneously latched by the shift register circuit for one stage are vertically stacked as a vertically stacked structure. It is effective to arrange adjacently only the upper stage or the lower stage without arranging over. These wiring methods basically share the vertical wiring between a plurality of adjacent units, thereby minimizing as much as possible, securing a horizontal area necessary for element arrangement, and occupying the area occupied by the wiring itself. The aim is to reduce.

However, the output line from the shift register is
When the block division according to the present invention is applied, the number of units to be latched at the same time is at most only three pixels corresponding to RGB, so that the signal delay does not matter even if the horizontal wiring width is small. There is no clear limitation on the horizontal area width allocated to a pair of vertical wiring, but if the area width is too large, signal delay due to the increase in load on the horizontal wiring becomes a problem, and the horizontal wiring width is reduced. It is necessary to increase the width, and conversely, the cross capacitance and the area occupied by the wiring are increased. Therefore, it is necessary to set the width of the lateral region to an optimum value.

As described above, by devising the arrangement of the horizontal scanning circuit and the arrangement of the wiring, the panel frame size can be minimized while maintaining high display quality, and driving with low power consumption can be achieved. A circuit-integrated liquid crystal display device can be realized.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) First, a pixel and a circuit configuration on an array substrate which constitute a drive circuit integrated type active matrix liquid crystal element will be described with reference to FIG. As shown in FIG. 1, the active matrix array glass substrate 1 is provided with a display unit 2 and a vertical scanning circuit unit 3 and a horizontal scanning circuit unit 4 as drive circuit units arranged around the display unit 2.

In the display unit 2, a plurality of source lines 5 (image signal lines) and a gate line 6 are provided so as to be orthogonal to each other. A transparent pixel electrode 7 and a pixel transistor 8 are provided at each intersection of the source line 5 and the gate line 6.

The source electrode 8a of the pixel transistor 8
Are connected to the source line 5, and the gate electrode 8b is connected to the gate line 6. A liquid crystal layer 10 exists between the transparent pixel electrode 7 and the transparent counter electrode 9.

As the actual structure of the element, a portion of the display portion 2 except for the liquid crystal layer 10 and the transparent counter electrode 9, the horizontal scanning circuit 1 and the vertical scanning circuit portion 3 are formed on the same substrate 1. The transparent counter electrode 9 is formed on a counter substrate (not shown) facing the liquid crystal layer 10.

The drain electrode 8c of the pixel transistor 8 is connected to the transparent pixel electrode 7.

In order to improve the display quality, a capacitance element or the like (not shown) is provided in parallel with the transparent pixel electrode 7 and the transparent counter electrode 9, or each transparent pixel electrode 7 is connected to the adjacent pixel. -A capacity (not shown) may be provided between the capacitor and the drain line 8.

The vertical scanning circuit section 3 is provided with a vertical shift register 3a and a pulse buffer 3b. The vertical shift register 3a stores one signal every one vertical scanning period.
The pulse of the vertical synchronization signal Vsync which is input once is sequentially shifted in synchronization with the horizontal synchronization signal Hsync which is also a vertical clock, and is output to the pulse buffer 3b as a timing signal.

The pulse buffer 3b sequentially outputs a drive pulse to each gate line 6 in accordance with the timing signal, and turns on the pixel transistor 8 for each horizontal scanning line. The horizontal scanning circuit unit 4 includes a horizontal shift register 4a, a latch circuit 4b, and a D / A converter 4c. The horizontal shift register 4a sequentially shifts the pulse of the horizontal synchronizing signal Hsync input once every one horizontal scanning period in synchronization with the horizontal clock Hck, and outputs the same to the latch circuit 4b as a timing signal.

The latch circuit 4b holds display image data for each pixel of one horizontal scanning line in accordance with a timing signal from the horizontal shift register 4a.

The D / A converter 4c has a latch circuit 4b.
An analog source voltage (for example, 0 to 6 V) corresponding to the digital signal (display image data) held in the memory is output to the source line 5, and a predetermined voltage is applied between the transparent pixel electrode 7 and the transparent counter electrode 9. Is stored.

The above is a description of the pixels and the circuit configuration on the array substrate. FIG. 2 shows the configuration and the arrangement method of the first embodiment. FIG. 2 is an explanatory diagram showing the arrangement of the horizontal scanning circuit section 4 and the data wiring when the display section 2 and the horizontal scanning circuit section 4 on the array substrate are divided into blocks.

FIG. 2 shows an example in which the number of data line divisions is four. The horizontal scanning circuit section 4 is divided into four horizontal scanning circuit blocks 11. Various signals input to the horizontal scanning circuit unit 4 are sent from an external circuit to the vertical wiring group 14 via the bus flexible 12 and the connection pads 13 corresponding to the respective horizontal scanning circuit blocks 11.

Further, signals necessary for each element constituting the horizontal scanning circuit are supplied by horizontal wiring. As for the horizontal wiring, only the horizontal power line 15, the horizontal ground line 16, and the horizontal data signal line 17 are shown in the figure, and other signal lines are omitted. Although not distinguished in the drawing, the vertical wiring group includes all signal lines required for driving the horizontal scanning circuit block 11, including data signal lines. I have. The number of data signal lines supplied to one horizontal scanning circuit block 11 is as follows:
According to the present embodiment, even if data division is performed, only data lines equivalent to the same number of data lines as in the case where data division is not performed are provided. It can be seen that the frame width and the cross capacitance value are not affected. As a result,
The frame width and power consumption can be reduced.

(Embodiment 2) This embodiment relates to a method of arranging wirings and scanning circuits in units of horizontal scanning circuits corresponding to one pixel as shown in FIG. In FIG. 3, the horizontal scanning circuit is divided into a horizontal shift register circuit unit 18 and a horizontal scanning circuit unit 19.

Here, the horizontal scanning circuit unit 19 represents a combination of circuit components for driving one pixel in the horizontal scanning circuit excluding the shift register circuit, and includes a combination of a latch circuit and a D / A converter circuit. It is configured.
The horizontal scanning circuit units 19 are arranged at a ratio of one within the width of two pixels, and are vertically stacked by two pixels in the vertical direction.

Therefore, as a total, within a width of 12 pixels,
Twelve horizontal scanning circuit units 19 are arranged. By doing so, the restrictions on the arrangement of the elements constituting the horizontal scanning circuit unit 19 and the wiring connecting the elements are reduced, so that the number of cross portions between the wirings is increased more than necessary, The occupied area does not increase, and as a result, both the size and the power can be reduced.

Since three pixels are simultaneously latched in the horizontal shift register circuit unit 18 for one stage, the horizontal shift register circuit unit 18 for one stage is latched.
May be arranged within a width of three pixels, and a relatively sufficient degree of freedom of arrangement of elements and wirings is given. On the other hand, the vertical shift register output line 20 output from the horizontal shift register circuit unit 18 becomes a constraint on the horizontal width direction when the horizontal scanning circuit unit 19 is arranged.

Therefore, instead of arranging a pair of vertical shift register output lines 20 for one horizontal scanning circuit unit 19, as shown in FIG. In order to supply the signals to the latch circuits corresponding to the respective bits from the vertical direction at the ratio of the horizontal shift register output lines 21, the horizontal shift circuit output lines 21 are arranged. In addition, the area restriction in the pixel width direction is reduced, and as a result, both the size and the power can be reduced.

On the other hand, in the present embodiment, as shown in FIG. 3, the power supply line and the ground line are arranged with the horizontal power supply line 15 and the horizontal ground line 16 at the uppermost end, and from there, in the vertical direction. A power supply line 22 and a vertical ground line 23 are arranged, and are further wired in the horizontal direction (not shown) from the power supply line 22 to supply power to each inverter element and the like constituting the horizontal scanning circuit unit 19. It has the configuration.

However, when the block division as described in the first embodiment is applied to the output lines from the shift register, the number of the unit horizontal scanning circuit units 19 to be latched simultaneously is at most three pixels corresponding to RGB. The signal delay does not matter even if the width of the horizontal shift register output line 21 is small, while the power supply line is allocated to a pair of the vertical power supply line 22 and the vertical earth line 23. There is no clear limitation on the width of the horizontal region, but if the width of the region is too large, signal delay due to an increase in the load on the horizontal wiring (not shown) becomes a problem, and it is necessary to increase the width of the horizontal wiring. Occurs, and conversely, the cross capacitance and the area occupied by the wiring increase. Therefore, it is necessary to set the width of the lateral region to an optimum value.

In this embodiment, an example is shown in which the vertical power supply line 22 and the vertical earth line 23 are arranged in a pair at a region width corresponding to 12 pixels. The horizontal scanning circuit block 11 as described in the first embodiment is formed by arranging the structural units adjacent to each other in the horizontal direction as the upper structural units. Here, the vertical power supply line 22 and the vertical ground line 23 are arranged in a pair at a region width corresponding to 12 pixels, but a value that is an integral multiple of 6, that is, 6, 12, 18 , 24, etc., is desirable for the structural unit on the layout. This is because, as shown in FIG. 3, the number of the horizontal scanning circuit units 19 latched by the horizontal shift register circuit unit 18 at the same time is three.
Alternatively, since they are arranged adjacent to the lower stage, 2 × 3 = 6 elements constitute a structural unit on the layout when only the restrictions from the horizontal shift register circuit unit 18 are considered.

Therefore, when the vertical power supply line 22 and the vertical earth line 23 are further considered, six units are defined as a minimum unit.
It is simplest in terms of arrangement to form a structural unit on the layout with the horizontal scanning circuit units 19 of an integral multiple of 6, which is a desirable configuration.

Further, by repeatedly arranging the structural units on the layout by an integral multiple of the number of adjacent units, 1
If the number of horizontal scanning circuit blocks 11 can be configured, it is the simplest in terms of arrangement. Conversely, the number of horizontal scanning circuit units 19 constituting a structural unit on the layout is determined so that such a configuration is possible. This is effective for simplifying the entire configuration.

When the wiring method of the horizontal shift register output lines 21 in this embodiment is applied to the vertical stacking structure of the horizontal scanning circuit unit 19 in this embodiment, as shown in FIG. Horizontal shift register circuit unit 18 for one stage among a plurality of horizontal scanning circuit units 19 for driving a plurality of pixels
Are simultaneously latched by three horizontal scanning circuit units 19
Is a vertically stacked structure that does not straddle the upper and lower tiers,
By arranging it only adjacent to the upper row or the lower row,
Unnecessary cross capacitance between wires and the area occupied by wires are reduced.

By devising the arrangement of the horizontal scanning circuit and the arrangement of the wiring as described above, the panel frame size can be minimized while maintaining high display quality, and driving with low power consumption can be achieved. A circuit-integrated liquid crystal display device can be realized.

[0043]

The present invention is embodied in the form described above and has the following effects. That is, by devising the arrangement of the horizontal scanning circuit and the arrangement of the wiring in the drive circuit integrated type liquid crystal display element, the panel frame size can be minimized while maintaining high display quality, and low power consumption can be achieved. A liquid crystal display element integrated with a power drive circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a pixel and a circuit configuration formed on an array glass substrate 1.

FIG. 2 is a diagram showing an arrangement configuration of a horizontal scanning circuit unit 4 and data wirings.

FIG. 3 is a diagram showing a specific arrangement configuration of a horizontal scanning circuit unit 17;

[Description of Signs] 1 Active matrix array glass substrate 2 Display unit 3 Vertical scanning circuit unit 3a Vertical shift register 3b Pulse buffer 4 Horizontal scanning circuit unit 4a Horizontal shift register 4b Latch circuit 4c D / A converter circuit 5 SO -Sline 6 Gate line 7 Transparent pixel electrode 8 Pixel transistor 8a Source electrode 8b Gate electrode 8c Drain electrode 9 Transparent counter electrode 10 Liquid crystal 11 Horizontal scanning circuit block 12 Bus flexible 13 Connection pad 14 Vertical wiring group 15 Horizontal direction Power supply line 16 Horizontal earth line 17 Horizontal data signal line 18 Horizontal shift register circuit unit 19 Horizontal scanning circuit unit 20 Vertical shift register output line 21 Horizontal shift register output line 22 Vertical power supply line 23 Vertical Direction earth wire

Continued on the front page F term (reference) 2H093 NA16 NA22 NA43 NA51 NC13 NC22 NC23 NC26 NC34 ND39 ND42 NE03 NE10 5C006 AA16 AC11 AC24 AF43 AF83 BB16 BC02 BC12 BF03 BF04 FA41 5C080 AA10 BB05 DD22 EE29 FF11 JJ02 JJ06

Claims (10)

[Claims] 1. An active matrix liquid crystal display device comprising: a plurality of image signal lines on a substrate; and a horizontal scanning circuit for driving the image signal lines, wherein the horizontal scanning circuit is provided on a glass substrate. The horizontal scanning circuit is integrally formed, and the horizontal scanning circuit temporarily holds N-bit digital data as an image input signal, and a timing signal for causing the data latch circuit to sequentially hold data. An active matrix liquid crystal display device, comprising: a shift register circuit for supplying digital data; and a D / A converter circuit for converting digital data temporarily held by the data latch circuit into an analog voltage. . 2. The active circuit according to claim 1, wherein said horizontal scanning circuit is divided into blocks by the number of data line divisions, and a data signal is input independently for each horizontal scanning circuit block. Matrix liquid crystal display device. 3. The horizontal scanning circuit block is further divided into two parts at the center and arranged at predetermined intervals, and a data line, a latch pulse line, a power supply line, and the like are arranged vertically from above in an empty region at the center. 3. The active matrix liquid crystal display device according to claim 2, wherein each input signal is supplied to said horizontal scanning circuit by arranging said input wiring and further arranging said input wiring in the left and right lateral directions. 4. A horizontal scanning circuit unit for driving one pixel, comprising the data latch circuit and the D / A converter circuit, of the horizontal scanning circuit, having a width corresponding to two pixels. 2. The active matrix liquid crystal display device according to claim 1, wherein the active matrix liquid crystal display element is arranged in a vertical stacking structure in two stages in a vertical direction. 5. A plurality of horizontal scanning circuit units which respectively drive a plurality of adjacent pixels, wherein a plurality of said horizontal scanning circuit units which are simultaneously latched by one stage of said shift register circuit have a vertical stacking structure. 2. The active matrix liquid crystal display device according to claim 1, wherein the active matrix liquid crystal display element is arranged adjacent to only the upper stage or the lower stage without being arranged over the upper and lower stages. 6. A pair of normal-phase and negative-phase output wirings corresponding to one stage of the shift register circuit are provided in a horizontal region occupied by the entire horizontal scanning circuit unit simultaneously latched by the shift register circuit. The timing signal is supplied to the data latch circuit by wiring in the vertical direction at a ratio and further wiring in the horizontal direction from each position in the vertical direction where the data latch circuit corresponding to each bit is arranged. The active matrix liquid crystal display device according to claim 1, wherein 7. A power supply line and an earth line are wired in a horizontal direction at an upper end or a lower end of the horizontal scanning circuit unit, and a pair of horizontal scanning circuit units occupy a certain number of horizontal regions. Power is supplied to the inverter elements and the like by wiring in the vertical direction at a ratio, and further wiring in the horizontal direction from each vertical position where the inverter elements and the like constituting the horizontal scanning circuit unit are arranged. 2. The active matrix liquid crystal display device according to claim 1, wherein 8. When the number of said horizontal scanning circuit units to be simultaneously latched by one stage of said shift register circuit is Na and Nb is set to an integer value, said horizontal scanning circuit unit becomes 2 × Na × Nb 7. The active matrix liquid crystal display device according to claim 6, wherein the power supply line and the ground line are arranged in a vertical direction at a pair in a horizontal region occupied only by the power supply lines. 9. The horizontal scanning circuit block of the horizontal scanning circuit block, wherein 2.times.Na.times.Nb horizontal scanning circuit units are set as one structural unit for repetition in a layout arrangement, and the structural units are repeatedly arranged adjacent to each other. 2. The active matrix liquid crystal display element according to claim 1, wherein one element is constituted. 10. When the Na and Nb are used, and the total number of pixels in the horizontal direction is Nc and the number of data line divisions is Nd,
2. The active matrix liquid crystal display device according to claim 1, wherein the integer value Nb is set such that Ne satisfying × Na × Nb × Ne = Nc / Nd is an integer value.