JP2002049308A - Data converting device and data converting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up the data conversion processing such as encipher, decipher and data diffusion by constituting a data converting device so as to perform plural sub-conversion processing in parallel. SOLUTION: A-input data 101 are subjected to a first nonlinear conversion by a first key parameter 111 and the exclusive OR of the converted result 109 and B-input data 102 is made to be the B-input data of the sub-conversion processing part 122 of a next stage as B-intermediate data 106. B-input data 102 is made to be the A-input data of the sub-conversion processing part of the next stage and are subjected to a second nonlinear conversion by a second key parameter 112, and the exclusive OR of the converted result and the B- intermediate data 106 are made to be the B-input data of the sub-conversion processing part 123 of a next stage as B-intermediate data 108.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data conversion apparatus and a data conversion method for encrypting and decrypting input data for protecting digital information in information communication and the like, and for spreading data.

[0002]

2. Description of the Related Art As a conventional data conversion method for encryption, for example, the FEAL-8 algorithm by Miyaguchi et al. (Miyaguchi, Shiraishi, Shimizu "FEAL-8 Encryption Algorithm" NTT Research and Commercialization Vol. 39, No. 4 / No. 5, 198
8).

FIG. 29 shows a part of the FEAL-8 encryption algorithm.

In FIG. 1, reference numerals 1001 and 1002 denote input data of two systems, 1003 and 1004 denote output data of two systems, and 1005, 1006, 1007, and 1008 denote intermediate data. Also, 1011, 1012, 101
3, 1014 are first, second, third, and fourth key parameters, respectively, 1021, 1022, 1023, and 1024 are sub-conversion processing units of each stage, and 103
1, 1032, 1033, and 1034, and an exclusive-OR circuit 1041, 1042, 1043, and 1044.

Next, the operation will be described. First, input data 1001 and 1002 of the two systems are input to the first system.
The data is input to the sub-conversion processing unit 1021 of the stage, and as a result, it is converted into new two-system intermediate data 1005 and 1006.
Subsequently, these converted intermediate data are input to the second-stage sub-conversion processing unit 1022, and as a result, are converted into new two-system intermediate data 1007 and 1008. This operation is performed eight times in total, and the data of the two systems after the sub-conversion processing in the eighth stage is output as final output data 1003, 1004.

The operation of the sub-conversion processing unit will be described by taking the first-stage sub-conversion processing unit 1021 as an example.

[0007] The sub-conversion processing unit 1021 receives the input data 1001 and 1002 of two systems and inputs the intermediate data 1 of two systems.
005, 1006 are output. Second input data 100
2 is divided into bytes in the non-linear conversion circuit 1031, an exclusive-OR operation is performed on the key parameters, and arithmetic addition is subsequently repeated, as described in detail in the R & D report of the above document. Then, a non-linear transformation is performed in which the data that has been finally split is fused. The converted data is subjected to an exclusive OR operation with the first input data 1001 to obtain a first-stage conversion result, and the second intermediate data 1
006 is output. Also, the second input data 10
02 is output as the first intermediate data 1005 as it is.

The second-stage sub-conversion processing unit 1022 obtains the second-stage intermediate data by the same process as described above, and thereafter, in this example, similarly, in this example, the processing is performed for a total of eight stages and the output data 1003 And 1004 are the final result.

[0009]

The conventional data conversion device is configured as described above, and outputs data after the non-linear conversion included in the one-stage sub-conversion process is completed.
The configuration was such that it could be used as an input for the sub-conversion processing in the next stage. That is, there is a problem that each sub-conversion process is performed sequentially and the process is slow.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is configured so that a plurality of sub-conversion processes can be performed in parallel, thereby achieving high-speed data conversion processes such as encryption / decryption and data diffusion. For the purpose of

[0011]

SUMMARY OF THE INVENTION A data conversion apparatus according to the present invention performs a first non-linear conversion of any two A input data and B input data with a first key parameter. A configuration in which an exclusive OR of the first non-linearly converted output data and the B input data is output as B intermediate data, and the B input data is directly output as A intermediate data; The second non-linear conversion is performed using the key parameter of No. 2 and the exclusive OR of the output data subjected to the second non-linear conversion and the B intermediate data is output as the next B intermediate data. Is output as A intermediate data, and the above arrangements are cascaded to make the final A intermediate data and B intermediate data converted output data.

Still further, in the basic configuration, the first non-linear conversion circuit and the exclusive OR circuit existing from the input side of the first non-linear conversion to the input side of the second non-linear conversion are provided in the first configuration.
And a second non-linear conversion circuit and an exclusive OR circuit existing from the input side of the second non-linear conversion to the input side of the next first non-linear conversion are connected to the second sub-conversion processing section. Alternatively, the exclusive OR circuit and the second non-linear conversion circuit existing from the output side of the first non-linear conversion to the output side of the second non-linear conversion are defined as a first sub-conversion processing unit, 2
The exclusive OR circuit and the first non-linear conversion circuit existing from the output side of the non-linear conversion to the output side of the next first non-linear conversion are defined as a second sub-conversion processing unit, and these first sub-conversion units The processing unit and the second sub-conversion processing unit are connected alternately by the required number of stages, and the final stage is used to convert A intermediate data and B intermediate data output from either the first or second sub-conversion processing unit after conversion. Output data.

Further, in addition to the above-mentioned basic configuration, the configuration of the data conversion device having the basic configuration is used as a non-linear conversion circuit in each sub-conversion processing unit as a nested structure.

The data conversion method according to the present invention is applicable to any two
In response to the two A input data and the B input data, the first B output data is directly output as the first A intermediate data.
A second step of performing a non-linear transformation of the A input data with the first key parameter, taking an exclusive OR of the output data after the non-linear transformation and the B input data, and outputting the result as first B intermediate data; Enter the first B intermediate data,
A third step of outputting the second A intermediate data as it is, and inputting the first A intermediate data to perform a non-linear conversion with a second key parameter, and output data after the non-linear conversion,
The exclusive OR with the first B intermediate data is calculated and the second B
And a fourth step of outputting the intermediate data as intermediate data. The first to fourth steps are repeated, and finally, the second or fourth step is completed.
The intermediate data is converted data.

Alternatively, the operation order of the non-linear conversion and the exclusive OR is changed to provide steps equivalent to the above method.

Still further, in addition to the basic configuration, a first nonlinear conversion circuit and an exclusive OR circuit existing from the input side of the first nonlinear conversion to the input side of the second nonlinear conversion are connected to the first nonlinear conversion circuit.
And a second non-linear conversion circuit and an exclusive OR circuit existing from the input side of the second non-linear conversion to the input side of the next first non-linear conversion are connected to the second sub-conversion processing section. Or an exclusive OR circuit existing from the output side of the first non-linear conversion to the output side of the second non-linear conversion and the second
Is a first sub-conversion processing unit, and an exclusive OR circuit and a first nonlinear conversion circuit existing from the output side of the second nonlinear conversion to the output side of the next first nonlinear conversion are A second sub-conversion processing unit, a first sub-conversion processing unit and a second sub-conversion processing unit are connected alternately by the required number of stages, and a data selection unit is connected to the input side of the first first sub-conversion processing unit. And a data holding unit is added to the output side of the last one of the first and second sub-conversion processing units. First, any two A-input data and B-input data are added to the data selection unit. In the next and subsequent times, when the selection input is completed, a feedback connection is performed so as to selectively input the output of the data holding unit, and conversion processing is performed. A intermediate data and B intermediate data that are output from and are held and output by the data holding unit And output data after conversion.

Still further, in addition to the basic configuration, any two of the A input data and the B input data have the same number of digits, and from the input side of the first nonlinear conversion to the input side of the second nonlinear conversion. From the first non-linear conversion circuit and the exclusive-OR circuit or from the output side of the second non-linear conversion.
The second non-linear conversion circuit and the exclusive OR circuit existing up to the output side of the non-linear conversion are used as the sub-conversion processing units, the necessary number of sub-conversion processing units are connected, and each of the first sub-conversion processing units A and B A data selection section is added to the input side, and a data holding section is added to each output side of A and B of the last sub-conversion processing section. First, A input data and B input data are selected and input by the data selection section. Then, when the selection input is completed, from the next time onward, a feedback connection is performed so that the output of the data holding unit is selected and input, and conversion processing is performed. In the final round, the A intermediate data and the B intermediate data output from the data holding unit are converted. Output later.

Further, in the first or second nonlinear conversion, the A input data to the sub-conversion processing unit is divided into an arbitrary number of digits to obtain A1 input data and A2 input data, and a key parameter is also optional. The first divided key parameter or the n-th divided key parameter is divided by the number of digits, and the A1 input data obtained by dividing the A input data is internally nonlinearly transformed by the first divided key parameter, and the output data which is internally nonlinearly transformed The exclusive OR of the A2 input data and the A2 input data is output as first A2 internal intermediate data, and the A2 input data
A first internal sub-transformation processing unit that outputs the A1 internal intermediate data of the first A1 internal intermediate data, and internally nonlinearly converts the first A1 internal intermediate data of the first internal sub-conversion processing unit as A1 input data using a second divided key parameter. The exclusive-OR of the output data subjected to the internal nonlinear conversion and the first A2 internal intermediate data as the A2 input data and the A2 input data is output as the second A2 internal intermediate data, and the first A2 internal intermediate data is output. The second internal sub-transformation processing unit that outputs the data as it is as the second A1 internal intermediate data, the first internal sub-transformation processing unit, and the second internal sub-transformation processing unit are connected alternately in n stages. Adding an internal data selection unit to the input side of the first internal sub-conversion processing unit, and adding an internal data holding unit to the output side of one of the last first and second internal sub-conversion processing units; A1 first
Input data and A2 input data are selected and input by the internal data selection unit, and when the selection input is completed, a feedback connection is performed so that the output of the internal data holding unit is selectively input from the next time onward, and an internal conversion process is performed. A1 after conversion of A1 intermediate data and A2 intermediate data output from the internal data holding unit
Perform nonlinear conversion as output data.

Further, at the time of the non-linear conversion in each sub-conversion processing unit, the A input data to the sub-conversion processing unit is divided by an arbitrary number of digits into A1 input data and A2 input data.
Further, the key parameter is also divided into an arbitrary number of digits to obtain a first divided key parameter or an n-th divided key parameter. A1 input data obtained by dividing the A input data is internally nonlinearly transformed by the first divided key parameter. The output data subjected to the non-linear conversion is output as first A2 internal intermediate data, and the exclusive OR of the A1 input data and the A2 input data is calculated as the first A1 input data.
A first internal sub-transformation processing unit that outputs as internal intermediate data, and a first internal sub-transformation processing unit that performs first non-linear conversion of the first A1 internal intermediate data as A1 input data by using a second divided key parameter. 2 as the A2 internal intermediate data, and the exclusive A1 of the first A1 internal intermediate data and the A2 internal intermediate data as the A1 input data and the A2 input data, and output as the second A1 internal intermediate data The internal sub-conversion processing unit, the first internal sub-conversion processing unit, and the second internal sub-conversion processing unit are connected alternately in n stages, and the internal side is connected to each input side of the first first internal sub-conversion processing unit. A data selection unit is added, and an internal data holding unit is added to the output side of the last one of the first and second internal sub-conversion processing units.
The input data and the A2 input data are selected and input by the internal data selection unit. When the selection input is completed, a feedback connection is performed so that the output of the internal data holding unit is selectively input from the next time onward, and an internal conversion process is performed. The A1 intermediate data and the A2 intermediate data output from the internal data holding unit are combined to perform non-linear conversion as converted A output data.

When the division of the A input data to the non-linear conversion in each of the above-mentioned or above-mentioned sub-conversion processing units has the same digit length, only the first internal sub-conversion processing unit is connected to the required number of stages.

Further, the first internal sub-conversion processing unit and the second internal sub-conversion processing unit are connected alternately by the required number of stages, and internal data selection is performed on the input side of the first first internal sub-conversion processing unit. An internal data holding unit is added to the output side of the last one of the first and second internal sub-conversion processing units, and first, the B1 input data and the B2 input data are added by the internal data selection unit. After the selection input is completed, after the next time, a feedback connection is performed so as to selectively input the output of the internal data holding unit, an internal conversion process is performed, and the B1 intermediate data output from the internal data holding unit is output last time. The converted B output data is obtained by combining the B2 intermediate data.

If the B input data to the internal sub-conversion processing units in the respective sub-conversion processing units have the same digit length, only the first internal sub-conversion processing unit is connected to the required number of stages.

Further, a sub-conversion processing unit using each key parameter is connected in an even number of stages, a data selection unit is added to the input side of the first sub-conversion processing unit, and the output side of the last sub-conversion processing unit. A data holding unit is added, and a key parameter supply unit is added. First, any two A-input data and two B-input data are selected by the data selection unit, and when the selection input is completed, a feedback connection is required so that the output of the data holding unit is selectively input after the next time. The key parameter supply unit supplies the key parameter to each sub-conversion processing unit corresponding to the repetition conversion process, and the last time the A intermediate data output from the data holding unit And B intermediate data as converted output data.

Further, at least one of the non-linear conversion circuits is an n-th power circuit of X on a Galois field.

Further, an n-th power circuit of the element X on the Galois field is constituted by normal bases.

A read only memory is used for at least a part of the nonlinear conversion circuit.

In addition, Random Access Memory is used for at least a part of the nonlinear conversion circuit.

A Logic Circuit is used for at least a part of the nonlinear conversion circuit.

Further, two logical operation circuits composed of two exclusive logical sums and a logical product or a logical sum are used as a data conversion unit, and one or both of the A input and the B input of the first sub conversion unit are used. At the input side, A input or B input is further divided into two AA data and AB data having an arbitrary digit length, the key parameter is divided into the corresponding A conversion key parameter and B conversion key parameter, and the AA data and A conversion A first logical product or logical sum with the key parameter is calculated, a first exclusive logical sum of the first logical product / logical sum output data and the AB data is calculated, and a first exclusive logical sum is calculated. The output is output data after AB data conversion, and a second logical product or logical sum of a first exclusive logical sum output and a B conversion key parameter is obtained, and the second logical product / logical sum output is obtained. Second exclusive logic of data and AA data And the second exclusive OR output is used as the output data after AA data conversion, and the output data after AA data conversion and the output data after AB data conversion are combined and output to the subsequent stage as A input data or B input data. I do.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 In order to maintain the confidentiality of data for information processing and the confidentiality of communication contents between parties,
Attention has been paid to encryption and decryption techniques. In the data conversion for encryption and decryption, it is important to obtain high-speed data conversion processing and to reduce the risk of decryption by others.

For encryption, a technique for performing non-linear conversion of input data using key parameters is known. Further, there is a concept of so-called difference probability as a scale representing the strength of encryption, and the smaller the value of the difference probability, the stronger the encryption.
As reference 1, Kaisa Nyberg, Lars
Ramkille Knudsen, Provab
le Security Against Diff
rental Cryptanalysis, Jo
urnal of Cryptology vol. 8
No. 1 (1995) shows that when encryption is performed by connecting a plurality of sub-conversion processes, the following holds when the difference probability of the non-linear conversion in each sub-conversion process is p.

(1) When the non-linear conversion is executed in a manner in which the input data and the output data are determined on a one-to-one basis, the sub-conversion processing becomes 3
If there are more stages, the overall difference probability is less than or equal to 2p ² .

Here, input data and output data are one-to-one.
This means that, for example, when output data Y having any value of 0 to 255 is output with respect to input data X having any value of 0 to 255, a certain value of the input data X And a certain value of the output data Y are in a one-to-one correspondence. For example, input data X
Is 8, the value of 125 is always output as the value of the output data Y.

An algorithm of the type shown in FIG.
If the difference probabilities of the three nonlinear transforms of the nonlinear transform circuits 1031, 1032, and 1033 are p, respectively, FIG.
Is 2p ²
It is as follows.

The conventional FEAL algorithm is shown in FIG.
FEAL is an algorithm of the type shown in
Since the difference probability p of the non-linear transformation in each sub-transformation process is 1, even if the above discussion is applied, only the conclusion that the difference probability of the entire algorithm is 2 or less can be obtained, and nothing can be proved regarding the encryption strength.

FIG. 2 is a diagram showing an example of a conventionally known nonlinear conversion circuit.

In the figure, 151 is an exclusive OR circuit in the non-linear conversion circuit, and 152 is a Galois field inverse circuit. However, 0 is output for 0 input. N represents the input / output bit size. When the configuration of FIG. 2 is used as the nonlinear conversion circuit, the difference probability p = 2/2 ⁿ (when n is an odd number) and p = 4
/ 2 ⁿ (when n is an even number).

However, the Galois field inverse circuit 152 in FIG.
However, there is a disadvantage that the scale becomes large when the size of the input data is large.

According to the present invention, the description of the above (1) holds even with the configuration described below, as Document 2, "Proofable security against differential decryption and linear decryption of block ciphers" ( Mitsuru Matsui, Proceedings of the 18th Symposium on Information Theory and Its Applications, October 2, 1995
4 to 27 days). Reference 2
According to the present invention, according to the present invention, even if the nonlinear transformation is performed as shown in FIG.
Even if the same thing as that described in No. 9 is used, 2) of (1)
Since p ² can be changed to p ² , the encryption strength is further increased.

In the present embodiment, a data conversion device that can perform data conversion at high speed by using a sub-conversion processing unit that can evaluate that the value of the difference probability p is small will be described.

FIG. 1 is a diagram showing a configuration of a data conversion device according to the present embodiment.

Referring to FIG.
Input data and B input data, 103 and 104 are A output data and B output data at the last stage, both of which are output data for data conversion. 105 to 108 are intermediate data, and 111 to 114 are key parameters for encryption. 121 to 124 are first to n-th sub-conversion processing units, 131 to 134 included therein are first to n-th non-linear conversion circuits, 141 to 14
4 is an exclusive OR circuit.

Next, the operation of the data converter having the above configuration will be described. Here, a case where the lengths of two input data are equal will be described. Note that the time required for the data conversion process is a non-linear conversion, and the time required for the exclusive OR operation is negligible compared to the nonlinear conversion.

In FIG. 1, one A input data 101
The first key parameter 111 allows the exclusive OR circuit 151 and the Galois field inverse circuit 152 shown in FIG.
Undergoes a non-linear transformation. This conversion result 109 is subjected to an exclusive OR operation with the other B input data 102 to obtain B intermediate data 106 for the next stage (S2). On the other hand, B
The input data 102 is the first stage A intermediate data 1
05, which is an input to the next stage (S1). The A intermediate data 105 undergoes the second non-linear conversion, and the B intermediate data 1
06 and an exclusive OR operation. As a result, B intermediate data 108 is obtained (S4). B intermediate data 106
Becomes the A intermediate data 107 to the next stage as it is (S
3). According to this procedure, the calculation is performed in the second nonlinear conversion circuit 132 in parallel with the first nonlinear conversion temporally.

In this way, in the odd-numbered and even-numbered sub-conversion processing sections, nonlinear conversion is performed almost in parallel, and high-speed data conversion can be performed.

In the above embodiment, the case where the lengths of the two input data are equal has been described.
_{When 1} bit and the length n ₂ bits of the B input data are different (n ₁ > n ₂ ), the following holds.

(2) When nonlinear conversion is performed in a manner in which input data and output data are determined one-to-one, if there are three or more sub-conversion processes, the total difference probability is p ² or less.

Therefore, even if the length of the two input data is changed in the configuration of FIG. 1, the difference probability p of each sub-transformation processing unit does not change, but the value of the total difference probability is p ² or less. Thus, it is possible to configure a data conversion device that is found to be. In this case, the input to the exclusive OR circuit, to the length of the A input data and B input data have different relative protruding portions for long data (n ₁ -n _2-bit portion) Then, the exclusive OR operation is performed on only the portion (n ₂ bits) having the same length as the short data without performing the exclusive OR operation on the short data. Or, a part that is insufficient for short data as compared with long data (part of n ₁ -n ₂ bits)
The exclusive OR operation is made equal to long data by, for example, filling constants in the data. When the lengths of the A input data and the B input data are different, the key parameters also supply appropriate key parameters corresponding to the lengths.

Although the hardware configuration has been described in the present embodiment, even if the nonlinear conversion and the exclusive OR operation are performed by software, the operations corresponding to the odd-numbered stages and the operations corresponding to the even-numbered stages are performed in parallel. Can be processed and a similar effect can be obtained.

Embodiment 2 Another configuration example of the high-speed nonlinear conversion which is the gist of the present invention will be described.

In this embodiment, the position of the exclusive OR in each sub-conversion processing unit is changed. FIG. 3 is a block diagram showing the configuration.
Denote first to fourth sub-conversion processing units, respectively. The key parameters 111 to 114, the non-linear conversion circuits 132 to 135, and the exclusive OR circuits 141 to 144 are the same as those in the first embodiment shown in FIG. The sub-conversion processing units 161 to 164 are different in internal connection from the sub-conversion processing units 121 to 124 in FIG.

With this connection, as in the first embodiment, the total difference probability can be set to p ² or less, and a strong cipher whose overall difference probability is smaller than 2p ² described in (1) can be generated.

The first sub-transformation processing section 161 non-linearly converts the A-input data 101 and the B-input data 102 with the first key parameter 111, and performs the non-linear conversion with the non-linear conversion circuit 132. The output data is output as the first stage B intermediate data 106 (S1).
2). Also, the exclusive OR circuit 141 outputs the A input data 1
01 and the B input data 102 are obtained as an exclusive OR, and this is output as the first stage A intermediate data 105 (S1).
1).

The second sub-transformation processing section 162 receives the A intermediate data 105 output from the first sub-transformation processing section 161 as one input and performs a non-linear conversion using the second key parameter 112. The output data nonlinearly converted in 133 is output as the second stage B intermediate data 108 (S14). The exclusive OR circuit 142 performs an operation on the first stage A intermediate data 105 and the B intermediate data 106 as inputs, and the second stage A intermediate data 10
7 (S13).

Thereafter, the first and second sub-conversion processing units are connected alternately. It is the same as in the first embodiment that the end may be either the first or the second sub-conversion processing unit.

The operation based on this connection is also based on the basis of Document 2 described in the first embodiment, and an apparatus having an overall difference probability of p ² or less can be obtained. In addition, comparing the operation speed of the non-linear conversion with the operation speed of the exclusive OR operation, the operation of the exclusive OR operation is much faster, so that it is clear from the connection state shown in FIG. The operation of the nonlinear conversion of the second stage and the operation of the second stage are performed almost in parallel, thereby enabling high-speed operation of the entire apparatus.

Here, the fact that the configuration shown in FIG. 1 and the configuration shown in FIG. 3 are substantially the same will be described with reference to FIG.

In FIG. 4, 121 to 124 are the sub-conversion processing units shown in FIG. Reference numerals 161 to 164 denote sub-conversion processing units shown in FIG. As can be seen from FIG. 4, the sub-conversion processing unit shown in FIGS. 1 and 3 depends on what part of the circuit shown in FIG. 4 is cut out. That is, FIG.
In the case of, the elements from the input side of the first nonlinear conversion circuit 131 to the input side of the second nonlinear conversion circuit 132 (the first nonlinear conversion circuit 131 and the exclusive OR circuit 141) are
Elements from the input side of the second non-linear conversion circuit 132 to the input side of the next first non-linear conversion circuit 133 (the second non-linear conversion circuit 132 and the exclusive OR circuit) 142) is the second sub-conversion processing unit 122. In the case of FIG. 3, the first nonlinear conversion circuit 131
The elements (exclusive OR circuit 141 and second non-linear conversion circuit 132) from the output side of the second non-linear conversion circuit 132 to the output side of the second non-linear conversion circuit 132 are referred to as a first sub-conversion processing unit 161 and the second non-linear conversion Elements from the output side of the circuit 132 to the output side of the next first nonlinear conversion circuit 133 (the exclusive OR circuit 1
42 and the first nonlinear conversion circuit 133) constitute a second sub-conversion processing unit 162.

FIG. 5 is a diagram showing another example having a configuration substantially the same as the configuration shown in FIG. 1 or FIG.

The example shown in FIG.
145 are connected in cascade. The exclusive OR circuit is cascaded so that the output data becomes one of the two input data to the next exclusive OR circuit. The nonlinear conversion circuits 131, 133, and 135 are:
Among the exclusive OR circuits connected in cascade, they are connected to odd-numbered exclusive OR circuits 141, 143, and 145. The nonlinear conversion circuits 132, 134, 136
It is connected to even-numbered exclusive OR circuits 142 and 144.

Even if the configuration shown in FIG. 5 is used, FIG.
Similarly, the first and second nonlinear conversion circuits 131 and 1
32 or 133 and 134 or 135 and 136 are executed in parallel, and high-speed processing is possible.

Embodiment 3 As described in the first embodiment, the scale of the nonlinear conversion circuit illustrated in FIG. 2 increases when the size of input / output data is large. Therefore, in the present embodiment, a compact configuration is considered in which the data conversion device has a nested structure and the nonlinear conversion circuit of FIG. 2 is also combined with a smaller nonlinear conversion circuit (for example, an inverse circuit).

Further, the FEAL of the document of the conventional example has a large value of the difference probability p, and is therefore insufficient as an evaluation of encryption strength.

In the present embodiment, a non-linear conversion circuit will be described in which one non-linear conversion has a smaller scale and can reduce the total difference probability.

FIG. 6 is a diagram showing details of the sub-conversion processing section and its non-linear conversion circuit.

In FIG. 6, a denotes a first-stage sub-conversion processing unit, 221 denotes an external sub-conversion processing unit, and 231 denotes an external non-linear conversion circuit. b is an external nonlinear conversion circuit 231
351 is an internal dividing unit that divides the A input data 101 into two, and 301 and 302 are two divided A1s.
Input data, A2 input data, 303 to 308 are internal intermediate data, 311 to 313 are key parameters 11
1 is a divided key parameter, 352 is an internal fusion unit that fuses the internal intermediate data 303 and 304, 321 to 323 are internal sub-conversion processing units, 331 to 333 are internal nonlinear conversion circuits, and 341 to 343 are internal exclusive. It is an OR circuit. Reference numeral 158 denotes a key parameter supply unit that divides the key parameter 111.

[0067] For example, in the case of the algorithm of FIG. 6, when used as a differential probability p as an internal nonlinear transformation circuit 331, 332, and 333, differential probability of the external nonlinear transformer circuit 231 is p ² or less. Therefore, the external sub-conversion processing unit 2
The difference probability of the algorithm in which three or more layers 21 are overlapped is (p ² ) ² = p ⁴ or less.

FIG. 7 shows four stages of the external sub-conversion processing units shown in FIG. 6A, and a three-stage internal sub-processing unit shown in FIG. 6B as a nonlinear conversion circuit in each external sub-conversion processing unit. FIG. 3 is a diagram illustrating a configuration of an entire sub-conversion processing unit when a conversion processing unit is connected.

In the figure, each of the external sub-conversion processing units 221 to 224 which are representative components, each of the external non-linear conversion circuits 231 to 234, the exclusive OR circuits 141 to 144 in the external sub-conversion processing unit, Sub-conversion processing unit 3
21 to 323, and the internal nonlinear conversion circuits 331 to 3 in the first and second external nonlinear conversion circuits 231 and 232.
Although the number of 36 is described, the numbers of the other components are omitted.

FIGS. 8 to 10 are diagrams for explaining the order in which the data conversion device having the configuration shown in FIG. 7 performs data conversion in a time-dependent manner.

First, the external nonlinear conversion circuit 23 shown in FIG.
1 will be described.

The A input data 101 to the external sub-transformation processing unit 221 is divided into two by an arbitrary number of digits by an internal dividing unit 351 to obtain A1 input data 301 and A2 input data 302. Parameter supply unit 1
The first divided key parameter and the n-th divided key parameters 311 to 313 are supplied after being divided by an arbitrary number of digits by 58. In the first internal sub-conversion processing section 321,
The A1 input data 301 obtained by dividing the input data 101 is subjected to an internal non-linear conversion using the first split key parameter 311. The output data subjected to the internal non-linear conversion and the A2 input data 3
XOR with the first A2 internal intermediate data 3
06 and outputs the A2 input directly to the first A1
Output as internal intermediate data 305.

The second internal sub-transformation processing section 322 receives the first A1 internal intermediate data 305 of the first internal sub-transformation processing section 321 as A1 input, and performs internal non-linear conversion with the second divided key parameter 312. . The first A2 internal intermediate data 306 is used as A2 input data, and the exclusive OR of the A2 input and the output data subjected to the internal non-linear conversion is calculated as a second
, And outputs the first A2 internal intermediate data 306 as it is as the second A1 internal intermediate data 307. Then, the first internal sub-conversion processing unit and the second internal sub-conversion processing unit are connected alternately in n stages, and the A1 internal intermediate data 303 and A2 internal intermediate data 304 in the final stage are converted into an internal fusion unit. The result is converted into the conversion result 109 by 352.

Next, the operation of the data converter having the above configuration shown in FIG. 7 will be described.

First, in the first cycle, A input data 1
The processing shown in FIG. 8 is performed on the 01 and B input data 102. That is, since the nonlinear conversion takes time, in the first cycle, the internal nonlinear conversion circuits 331 and 332 of the external sub-conversion processing unit 221 and the external sub-conversion processing unit 222
Most of the time is used in the internal nonlinear conversion circuits 334 and 335 of FIG. That is, in the first cycle, as shown in FIG. 8, the data indicated by the thick line is transmitted, and the processing of the internal nonlinear conversion circuits 331, 332, 334, and 335 is executed.

In the next cycle, the processing shown in FIG. 9 is performed. That is, the internal nonlinear conversion circuit 333 in the first external sub-conversion processing unit 221 and the second external sub-conversion processing unit 222
The internal nonlinear conversion circuit 336 in the inside, the internal nonlinear conversion circuit 337 in the third external sub-conversion processing unit 223, and the internal nonlinear conversion circuit 391 in the fourth external sub-conversion processing unit 224 take time. . The thick broken line indicates that the data on the A input side has been transmitted.

In the next cycle, the processing shown in FIG. 10 is performed. That is, the remaining internal non-linear conversion circuits 338, 339 and 3 of the third and fourth external sub-conversion processing units 223 and 224
The processing time is assigned to 92,393. At the end of these three cycles, all conversion processing ends. When this is compared with the data conversion of the conventional sequential processing method, the conventional method requires 12 cycles because the internal nonlinear conversion of the next stage does not start unless the internal nonlinear conversion of the previous stage is completed. In the method of (1), about four times as high speed processing can be performed.

In the above embodiment, the nested internal non-linear conversion circuits 331 to 39 in the internal sub-conversion processing section are used.
Reference numeral 3 shows the connection configuration of the first embodiment. However, the same operation is performed by using the connection configuration of the second embodiment as a nested nonlinear conversion circuit, and the same effect is obtained.

Embodiment 4 In this embodiment, an embodiment in which a non-linear conversion circuit having a small circuit configuration is applied to a non-linear conversion circuit in a conventional sub-conversion processing unit will be described.

FIG. 11 is a diagram showing details of the sub-conversion processing section and its non-linear conversion circuit.

In FIG. 11, a indicates a first-stage sub-conversion processing unit, 421 indicates an external sub-conversion processing unit, and 431 indicates an external non-linear conversion circuit. FIG. 11B shows a detailed configuration of the external nonlinear conversion circuit 431, where 551 is an internal dividing unit,
501 to 508 are input data, 511 to 513
Is a divided key parameter obtained by dividing the key parameter 111,
Reference numeral 552 denotes an internal fusion unit, 521 to 523 denote internal sub-transformation processing units, and 531 to 533 denote internal nonlinear conversion circuits.
Reference numerals 41 to 543 denote exclusive OR circuits.

In the case of the algorithm of FIG.
The conversion circuits 531, 532, and 533 use the difference probability p as
Is used, the difference probability of the external nonlinear conversion circuit 431 is
Is p ^TwoIt is as follows. Therefore, the external sub-conversion processing unit 421
The difference probability of the algorithm of three or more stages is 2 (p^Two)^Two=
2p^FourIt is as follows.

FIG. 12 is a circuit diagram showing a configuration in which the external sub-conversion processing units shown in FIG. 11A are connected in two stages, and a three-stage internal sub-processing unit shown in FIG. 13A and 13B are diagrams illustrating a configuration of an entire sub-conversion processing unit when a conversion processing unit is connected, and a diagram for explaining a sequence of performing data conversion by the data conversion device having the configuration illustrated in FIG.

In the figure, each of the external sub-conversion processing units 421 and 422, which are representative components, exclusive OR circuits 441 and 442 in the external sub-conversion processing unit, and internal sub-conversion processing units 521, 522 and 523 are shown. And the numbers of the internal non-linear conversion circuits 531 to 536 in the first and second internal sub-conversion processing sections are described, but the numbers of the other components are omitted.

Next, the operation of the data converter having the above configuration will be described.

First, in the first cycle, as shown in FIG. 12B, A input data 101 and B input data 102
, The internal nonlinear conversion circuits 531 and 532 of the external sub-conversion processing unit 421 take time. That is, in the first cycle, the data indicated by the bold line in FIG.
The processing of the internal nonlinear conversion circuits 531 and 532 is executed.

In the next cycle, the processing shown in FIG. 12C is performed. That is, the internal nonlinear conversion circuit 533 in the external sub-conversion processing unit 421 and the second external sub-conversion processing unit 422
Time is given to processing of the internal nonlinear conversion circuit 534 in FIG. The thick broken line indicates that the data on the A input side has been transmitted.

In the next cycle, the processing shown in FIG. 12D is performed. That is, the processing time is allocated to the remaining internal nonlinear conversion circuits 535 and 536 of the second external sub-conversion processing unit 422. At the end of these three cycles, all conversion processing ends. Comparing this with the conventional sequential processing method, in the conventional method, the processing of the internal nonlinear conversion of the next stage cannot be performed unless the processing of the internal nonlinear conversion of the preceding stage is completed, so that in this example, six cycles were required. Against
The method according to the present embodiment has an effect that the processing is completed in three cycles and the operation can be speeded up.

In the above embodiment, the nested nonlinear conversion circuit in the sub-conversion processing unit has the connection configuration of the first embodiment. However, the nested nonlinear conversion circuit of the second embodiment is used as a nested nonlinear conversion circuit. The same operation is performed by using the one having the configuration, and the same effect is obtained.

Embodiment 5 Another embodiment in which a non-linear conversion circuit, which is a basic component of the data conversion device of the present invention, is applied to a non-linear conversion circuit in a conventional sub-conversion processing unit will be described.

FIG. 13 is a diagram showing the configuration and details of the non-linear conversion circuit in the sub-conversion processing unit.

In FIG. 13, a indicates the entire structure,
621 to 624 are external sub-conversion processing units; 631 to 634 are external non-linear conversion circuits;
Reference numerals 4, 741 to 744 denote exclusive OR circuits. Also, 601, 602, 701, and 702 are A1,
B1, A2, B2 input data, 603, 604, 70
Reference numeral 3,704 denotes output data after conversion, 605 to 60
8, 705 to 708 are intermediate data. FIG. 13B shows a detailed configuration of the external nonlinear conversion circuit 631.
Numerals 51 and 751 denote data after nonlinear conversion, 775 to 778 denote internal intermediate data, and 711 to 713 denote divided key parameters obtained by dividing the key parameter 111. 72
1 to 723 are internal sub-conversion processing units, and 731 to 73
Reference numeral 3 denotes an internal nonlinear conversion circuit, and reference numerals 761 to 763 denote exclusive OR circuits.

The data conversion apparatus shown in FIG.
For each of the A1 input data, the A2 input data, the B1 input data, and the B2 input data, the non-linear conversion and the exclusive logic are performed between the A1 input data and the B1 input data, and between the A2 input data and the B2 input data. Perform a sum operation to obtain B1 intermediate data and B2 intermediate data, respectively.
The B1 input data and B2 input data are directly used as A1 intermediate data and A2 intermediate data.

The other operations of the data conversion device having the above configuration are clear in the description of the third and fourth embodiments, and therefore, detailed description is omitted here. As in the third and fourth embodiments, the calculation can be speeded up.

Embodiment 6 FIG. In the present embodiment, a process executed by alternately connecting a plurality of first sub-conversion processing units 121 and second sub-conversion processing units 122 in Embodiment 1 is referred to as a first sub-conversion process. A description will be given of what is realized by the repetition processing of the processing unit including the unit 121 and the second sub-conversion processing unit 122. That is, the first sub-conversion processing unit 121 and the second sub-conversion processing unit 12 in which the arithmetic processing does not overlap
2 as one set of processing units, holding the output data of the set of second sub-conversion processing units, supplying this output data as input data of the first sub-conversion processing unit, and enabling repetitive operations By doing so, the hardware scale is reduced.

FIG. 14 is a block diagram showing the configuration. In FIG. 14, reference numerals 121 and 122 denote first and second sub-conversion processing units. 111 and 112 are first and second key parameters. The non-linear conversion circuits 131 to 132 and the exclusive OR circuits 141 to 142 are equivalent to the components of the first embodiment shown in FIG. 153 is a control unit, 154 is a repetition processing unit, 156a and 156b are data selection units, 157a and 157b are data holding units, 15
8 is a key parameter supply unit.

Next, the operation of the data converter having the above configuration will be described.

[0098] Arbitrary A input data 101 and B input data 102 are first input to the first sub-conversion processing unit 121 via the data selection units 156a and 156b. next,
The A intermediate data 105 and the B intermediate data 106 are input to the second sub-conversion processing unit 122. Here, the first and second
The operation of the sub-conversion processing unit is the same as that described in the first embodiment. However, the key parameters to be supplied to the first and second sub-conversion processing sections corresponding to the following repetition processing are supplied to the non-linear conversion circuits in the first and second sub-conversion processing sections. Is supplied by the key parameter supply unit 158. The A-intermediate data 107 and B-intermediate data 108 output from the second sub-conversion processing unit 122 are respectively processed by the repetition processing unit 154 into a data holding unit 157a.
The data are input to the first sub-conversion processing unit 121 as A input data and B input data via the data selection unit 156a, the data holding unit 157b, and the data selection unit 156b, respectively. Thereafter, after the above-described repetitive processing, the A output data 103 and the B output data 104 are output.

With this configuration, the first embodiment
For the same reason as described above, high-speed data conversion can be performed, the number of sub-conversion processing units can be reduced, and the device scale can be reduced.

In the above-described embodiment, a unit in which the first sub-conversion processing unit 121 and the second sub-conversion processing unit 122 are cascade-connected one by one is used as a unit of repetitive processing as a basic configuration. It is apparent that the same effect can be obtained by forming the first sub-conversion processing unit and the second sub-conversion processing unit as a set and alternately cascading the required number of stages as a unit of repetition processing. is there.

In the configuration shown in FIG. 14, since the first sub-conversion processing unit and the second sub-conversion processing unit are cascade-connected as a set, they are always constituted by even-numbered sub-conversion processing units. As described above, the reason for the configuration using the even-numbered sub-conversion processing units is as follows.
This is to enable appropriate data conversion even when the numbers of digits of the A input data and the B input data are different. For example, the A input data is 7 digits, the B input data is 9 digits, and the key parameter supply unit 158 supplies the 7-digit key parameter 111 to the non-linear conversion circuit 131.
It is assumed that the digit key parameter 112 is supplied to the nonlinear conversion circuit 132. The 7-digit A input data 101 is converted into a 7-digit key parameter 11 by the nonlinear conversion circuit 131.
The data is nonlinearly converted by 1 to become 7-digit B intermediate data 106 and further output as A intermediate data 107. The A intermediate data 107 becomes A input data again via the data holding unit 157a and the data selection unit 156a. In this way, in order for the 7-digit A input data to be subjected to non-linear conversion by the 7-digit key parameter 111, the sub-conversion processing unit must be in an even-numbered stage. If the sub-conversion processing unit is an odd-numbered stage, the nonlinear conversion circuit 1
In the case of 31, the 7-digit data and the 9-digit data are non-linearly converted alternately.

Although not shown, if the key parameter supply unit 158 can control the sub-conversion processing unit to alternately supply the 7-digit and 9-digit key parameters, the odd-numbered sub-conversion processing unit May be connected in cascade.

Embodiment 7 FIG. In the present embodiment, a process performed by alternately connecting a plurality of first sub-conversion processing units 161 and second sub-conversion processing units 162 in Embodiment 2 is referred to as a first sub-conversion process. A description will be given of what is realized by a repetition process of a processing unit including a unit and a second sub-conversion processing unit. That is, by providing the feedback loop described in the sixth embodiment, the intermediate data of A and B is returned to the data selector on the input side, and the operation is repeatedly performed to reduce the hardware scale.

FIG. 15 is a block diagram showing the configuration. In FIG. 15, reference numerals 125 and 126 denote first and second sub-conversion processing units. 111 and 112 are first and second key parameters. The non-linear conversion circuits 132 to 133 and the exclusive OR circuits 141 to 142 are equivalent to the components of the second embodiment shown in FIG. Control unit 15
3, repetition processing unit 154, data selection unit 156a, 1
56b, data holding units 157a and 157b, and a key parameter supply unit 158 are the same as the elements in the sixth embodiment.

Next, the operation of the data converter having the above configuration will be described.

The arbitrary A input data 101 and B input data 102 are first input to the first sub-conversion processing unit 125 via the data selection units 156a and 156b. next,
The A intermediate data 105 and the B intermediate data 106 are input to the second sub-conversion processing unit 126. Here, the first and second
The operation of the sub-conversion processing section is the same as that shown in the second embodiment. However, the key parameters to be supplied to the first and second sub-conversion processing sections corresponding to the following repetition processing are supplied to the non-linear conversion circuits in the first and second sub-conversion processing sections. Is supplied by the key parameter supply unit 158. The A intermediate data 107 and the B intermediate data 108 output from the second sub-conversion processing unit 126 are output by the repetition processing unit 154 to the data holding unit 157, respectively.
a, 157b and the data selection units 156a, 156b, are input to the first sub-conversion processing unit 125 as A input data and B input data. Thereafter, after the above-described repetitive processing, the A output data 103 and the B output data 104 are output.

With this configuration, the second embodiment can be used.
For the same reason as described above, high-speed data conversion can be performed, the number of sub-conversion processing units can be reduced, and the device scale can be reduced.

The first cascade connection of the first sub-conversion processing unit 125 and the second sub-conversion processing unit 126 has been described as a unit of repetition processing.
The fifth embodiment and the second sub-conversion processing unit 126 may be combined into a single set, and may be cascade-connected alternately by a required number of stages to form a unit of the repetitive processing, as in the sixth embodiment. Although a detailed connection configuration diagram and description of the operation are omitted, as in Embodiment 6 or Embodiment 7, even-numbered external sub-conversion processing units in Embodiment 4 or Embodiment 5 are connected. Is replaced by a unit of the repetitive processing, the number of external sub-conversion processing units can be reduced without impairing the high-speed operation. Here, it is apparent from the description of the operation of the fourth embodiment that the high-speed operability is not impaired even when an external sub-conversion processing unit connected to an even number of stages is used as a repetitive processing unit.

Although a detailed connection diagram and description of the operation are omitted, the formation of a feedback loop by combining the data selection unit and the data holding unit in the sixth or seventh embodiment is described.
The present invention can also be applied to the internal sub-conversion processing units described in the third to fifth embodiments. That is, FIG. 6, FIG.
1 internal dividing sections 351 and 551 in the external nonlinear conversion circuit
An internal data selector is provided inside or after the internal data selector to select the data input, and an internal data holding unit is provided in or before the internal fusion units 352 and 552 to form a feedback loop with the internal data selector. I do. In addition, a data selection unit is provided before the external nonlinear conversion circuit of FIG. 13 to perform switching selection of data input, and a data holding unit is provided after the external nonlinear conversion circuit to form a feedback loop between the external nonlinear conversion circuit and the data selection unit. Form. By doing so, the scale of the internal sub-conversion processing unit can be reduced without impairing high-speed operation.

Embodiment 8 FIG. In the present embodiment, a plurality of sub-conversion processing units 121 to 124 in the first embodiment are used.
Will be described in which the processing according to (1) is replaced with the basic repetition processing of the repetition processing unit. In this embodiment, arbitrary A input data 101 and B input data 10
It is assumed that the number of data digits is equal to 2. A input data 1
When the number of data digits of 01 and the B input data 102 is equal, the number of sub-conversion processing units for repetition does not necessarily have to be an even number, and a feedback loop can be formed by cascading an arbitrary number of stages.

FIG. 16 is a block diagram showing the configuration. For the sake of simplicity, a feedback loop having only one sub-conversion processing section is provided.

In the figure, reference numeral 121 denotes a sub-conversion processing unit. First key parameter 111, nonlinear conversion circuit 13
1, an exclusive OR circuit 141, an iterative processing unit 154,
Data selection units 156a and 156b, data holding unit 157
a, 157b and the key parameter supply unit 158 are the same elements as in the other embodiments.

Next, the operation of the data converter having the above configuration will be described.

The arbitrary A input data 101 and B input data 102 are first input to the sub-conversion processing unit 121 via the data selection units 156a and 156b. Here, the operation of sub-conversion processing section 121 is the same as that described in the first embodiment. However, the key parameter supplied to the non-linear conversion circuit in the sub-conversion processing unit is the key parameter supply unit 15
8 is supplied in accordance with the following repetitive processing. The A intermediate data 105 and the B intermediate data 106 output from the sub-conversion processing unit 121 are supplied to the sub-conversion processing unit 121 by the repetition processing unit 154, respectively.
Input as input data. Thereafter, after the above-described repetitive processing, the A output data 103 and the B output data 104 are output.

With this configuration, the number of nonlinear conversion circuits can be reduced, and the size of the device can be reduced.

In the above embodiment, the one-stage sub-conversion processing unit 121 has been described as a unit of repetitive processing. However, it is apparent that a plurality of stages of cascade connection may be used. In this case, the device scale can be reduced without losing high speed.

The sub-transformation processing unit according to the second embodiment
It is clear that the sub-conversion processing unit of the device shown in FIG.

Although detailed connection configuration diagrams and descriptions of operations are omitted, similar to the sixth embodiment or the seventh embodiment, the above-described embodiment is applied to the internal sub-conversion processing of the third to fifth embodiments. It is also clear that the present invention can be applied to parts.

Embodiment 9 FIG. In the present embodiment, an embodiment in which a nonlinear conversion circuit having a small circuit configuration is applied to a nonlinear conversion circuit in a conventional sub-conversion processing unit will be described.

FIG. 17 is a diagram showing a configuration of a data conversion device according to the present embodiment.

FIG. 18 is a block diagram showing a configuration of external nonlinear conversion circuit 831 (or 838) in FIG.

FIG. 19 is a block diagram showing a configuration of internal nonlinear conversion circuit 931 (or 933) in FIG.

Here, the key parameter 811 is 32 × 3
= 96 bits, the total length of key parameter 811a + key parameter 811b + key parameter 811c is 32 bits, key parameter 811d + key parameter 811e +
Key parameter 811f has a total length of 32 bits, key parameter 811g + key parameter 811h + key parameter 8
The total length of 11i is 32 bits. Further, the key parameter 811a has 16 bits, and the key parameter 811b
Is 7 bits, and the key parameter 811c is 9 bits.

FIGS. 20 and 21 show that the nonlinear conversion circuits 951 and 952a and 952b in FIG.
ead Only Memory) or RAM (Ran
6 is an example of the conversion tables S7 and S9 in the case where the conversion tables are realized by dom access memory). For example, when input data X = 0 is input to conversion table S7, output data Y = 85 is output. When input data X = 1 is input, output data Y = 95 is output. When input data X = 128 is input, output data Y = 42 is output. Also in the case of the conversion table S9, the input data X = 0, 1,. . . , 511 are input, the output data Y = 341, 310,. . . , 170 are output.

Here, the conversion table S7 is configured as follows.

A 7th-order irreducible polynomial, x ⁷ + x ⁵ + x ⁴ + x ³ +
When the root of 1 = 0 is α, the input base is a normal base {α, α ² , α ⁴ , α ⁸ , α ¹⁶ , α ³² , α ⁶⁴ }, and the output base is a normal base {α ³² , α ⁴ , α ² , α ⁶⁴ , α ¹⁶ , α,
Let α ⁸に 対 し て be an expression of X ¹⁷ with respect to the input X which is an element on the Galois field GF (2 ⁷ ) with respect to this basis, and 55h
XOR (exclusive OR) of (hexadecimal) is output. FIG. 20 shows a table in which the input and output are expressed in decimal numbers. Here, as for the input / output, the left side is LSB (least significant bit).

The conversion table S9 is configured as follows.

A ninth-order irreducible polynomial, x⁹+ X⁸+ X⁷+ X⁶+
x^Four+ X^ThreeWhen the root of + 1 = 0 is α, the input base is positive
Normal basis ｛α, α^Two, Α^Four, Α⁸, Α¹⁶, Α³², Α⁶⁴,
α¹²⁸, Α ²⁵⁶｝, Base of output is normal basis ｛α⁶⁴, Α, α
¹⁶, Α⁸, Α²⁵⁶, Α^Two, Α¹²⁸, Α^{Three Two}, Α^Fourこ の and this
The Galois field GF (2⁹) Input X which is the element above
For X^Five155h (hexadecimal)
XOR (exclusive OR) is output. this
FIG. 21 shows a table in which inputs and outputs are expressed in decimal numbers.
Here, the left and right of the input and output are LSB (least significant bit).
You.

Note that a Galois field is expressed by a vector expression using a polynomial basis, a normal basis, or the like.

A typical example is a vector expression using a polynomial basis. The vector representation by the polynomial basis is GF (2
The primitive element of ^m ) is α, and an arbitrary element of GF (2 ^m ) is represented by a vector expression using polynomial bases {1, α, α ² ,..., α ^m-1 }.

An advantage of the polynomial basis is that GF (2 ^m )
Can be realized by bitwise addition (exclusive OR operation). That is, in the case of realization by hardware, it can be realized by m two-input exclusive OR operation circuits. However, in vector representation using a polynomial basis, multiplication is generally more difficult to realize with hardware than addition, and is generally realized with a ROM or the like.

An important basis other than the polynomial basis is a normal basis. This is m
A set consisting of the root α of the next primitive polynomial and its conjugate element,

[0133]

(Equation 1)

Is the basis.

The greatest feature of the normal basis is that when it is used, the square becomes very simple. GF (2
^When any element of ^m ) is squared, this can be realized by cyclically shifting the vector representation to the right. When this is realized by hardware, it can be realized only by changing the connection of the bits. By using this feature, an arbitrary element X can be compared with a vector expression using a normal basis.
It can be realized with less hardware scale X ⁿ circuit for. The inverse element (X ^-1 ) circuit can also be regarded as an X-n power circuit. That is, the Galois field GF
The inverse element X ^-1 of any element X in (2 ^m ) is

[0136]

(Equation 2)

This is because n may be equal to 2 ^m −2. As an example of this, the input 7 of the conversion table S7
Bits are set as ｛in0, in1, in2, in3, in4,
in5, in6}, output 7 bits to {out0, out}
1, out2, out3, out4, out5, out
FIG. 22 shows an example in which the lower 6th bit (out5) when 6｝ is realized by a logic circuit.

The operation of the data conversion device having the above configuration shown in FIG. 17 to FIG. 19 is clear from the previous embodiment, and a detailed description is omitted here.

Embodiment 10 FIG. A data conversion device which does not increase the circuit scale so much and further increases the strength of encryption will be described.

FIG. 23 is a configuration diagram of a data conversion device according to the present embodiment.

This configuration is obtained by adding data conversion units FL1 to FL10 to the device of the ninth embodiment.

FIG. 24 shows a data conversion unit FL19.
FIG. 71 is a diagram showing a detailed configuration of the F.71 (to FL10 980).

Each of the data conversion units FL1 to FL10 comprises an AND circuit 971a or an OR circuit 971b, and exclusive OR circuits 971c and 971d. The length of the key parameter KL1 is 32 bits, and the key parameter is supplied by a key parameter supply unit (not shown).
a and KL1b. For example, the key parameter KL
1a is divided into 16 bits, and the key parameter KL1b is divided into 16 bits. The logical product circuit 971a or the logical sum circuit 971b in the drawing may be either a logical product circuit or a logical sum circuit, or may be a combination of a logical sum circuit and a logical sum circuit.

The operation of the apparatus having the above configuration will be described.

Two exclusive OR circuits 971c and 971
d and two logical product circuits, two logical sum circuits, or first and second logical operation circuits each including one logical product circuit and one logical sum circuit as a data conversion unit 971, and a first sub-conversion process It is added to one or both of the A input side and the B input side of the unit.

The A input (or B input) is further divided into two AA data and AB data having an arbitrary digit length, and the key parameters are divided into corresponding A conversion key parameters 981a and B conversion key parameters 981b. A first circuit between the AA data and the A conversion key parameter 981a is calculated by an arithmetic circuit.
And outputs an exclusive OR circuit 9
71c, a first exclusive OR of the first AND / ORed output data and the AB data is obtained, and the first exclusive ORed output data is converted into AB data. Output data. The second logical operation circuit calculates a second logical product or logical sum of the first exclusive logical sum output and the B conversion key parameter, and obtains an exclusive logical sum circuit 971
d, a second exclusive OR of the second AND / ORed output data and the AA data is calculated.
Is output as the output data after the AA data conversion, and the output data after the AA data conversion and the output data after the AB data conversion are combined to obtain A output data (or B output data) at the subsequent stage. Output to

Data conversion units FL1 to FL1 newly provided
Since 0 is a linear function whose output changes depending on the value of the key parameter, it is possible to increase the resistance to other decryption methods other than the differential decryption method without increasing the difference probability. Since the operation of this non-linear conversion has already been described in the above embodiment, the description is omitted here.

The data conversion units FL1 to FL10
Need not necessarily be as shown in FIG. For example, the data conversion units FL1, FL3, FL5, FL7,
The FL9 may be inserted into only one of the A system (left side in the figure) and the B system (right side in the figure), or one of the first and second sub-conversion processing units forming a pair. The data conversion unit may be provided in both the A system and the B system or only one system in only the sub-conversion processing unit.

Embodiment 11 FIG. This embodiment is different from the ninth and tenth embodiments in that the nonlinear conversion circuit, which is a basic component of the data conversion device of the present invention, is nested in the conventional nonlinear conversion circuit in the sub-conversion processing unit. In contrast to the connection configuration as a circuit, the non-linear conversion circuit, which is a basic component of the data conversion device of the present invention, is replaced with a non-linear conversion circuit in the sub-conversion processing unit in the basic component of the data conversion device of the present invention. This is an example of connection configuration as a nested nonlinear conversion circuit. As shown in FIG. 25, the present embodiment has a form in which the arrangement of each component of the device of the tenth embodiment is changed. Since this operation is clear from the description of the above embodiment, a detailed description is omitted here. The positions of the data conversion units FL1 to FL10 are
The position that is not necessarily the position shown in the figure is the same as that of the tenth embodiment, and has the same effect.

FIG. 26 is a diagram summarizing the features described in the first to eleventh embodiments.

The first, second, fourth and fifth embodiments are shown in the vertical direction, and the third, sixth, seventh, eighth, ninth and tenth embodiments combined with the first, second, fourth and fifth embodiments are shown in the horizontal direction. , 11 are shown. Embodiments 1 and 2 describe the features of the sub-conversion processing unit. In FIG. 26, the configuration of the sub-conversion processing unit shown in FIG. Further, the configuration of the sub-conversion processing unit shown in FIG. Further, the third embodiment is characterized in that the sub-conversion processing units are nested, and an external sub-conversion processing unit and an internal sub-conversion processing unit are provided. Also, in order to distinguish from the internal sub-conversion processing unit of the third embodiment, FIG.
1 and 3 which do not have a nested structure are positioned as external sub-transformation processing units. In FIG. 26, when a combination is shown in any of the figures, the figure number is written in parentheses. For example, (FIG. 1) indicates that the type 1 sub-conversion processing unit is illustrated in FIG. FIG. 6 shows an example in which the external sub-conversion processing unit according to the third embodiment is a type 1 sub-conversion processing unit and the internal sub-conversion processing unit is also a type 1 sub-conversion processing unit. It shows what is shown. Also, FIG.
In the figure, it indicates that any one of a plurality of items described in parentheses can be arbitrarily selected. For example,
In the third embodiment, it is indicated that the sub-conversion processing unit used as the internal sub-conversion processing unit may be either type 1 or type 2. As can be seen from the figures, Embodiments 1, 2, 4, 5 and Embodiments 3, 6,
The features shown in 7, 8, 9, 10, 11 can all be combined. Further, the present invention is not limited to the combination shown in FIG. 26, and may be used in combination with other features. In addition, the present invention is not limited to the case of combination, but may be the case of using only each feature of each embodiment.

Next, an application example of the data converter according to the present invention will be described.

FIG. 27 shows a configuration of a personal computer or a workstation as an application example of the data conversion device according to the present invention.

The data conversion device 60 includes a display unit 61, a keyboard 62, a mouse 63, a mouse pad 64, a system unit 65, and a compact disk device 100.

The data converter according to the present invention is for inputting data from the compact disk device 100, transferring the data to the system unit 65, and displaying the data on the display unit 61, as shown in FIG.
Alternatively, the data displayed on the display unit 61 is output to the compact disk device 100. It converts data and transmits information via a line (not shown). However, the data conversion device according to the present invention is not limited to the personal computer or workstation shown in FIG. 27, and may be of any type. For example, instead of the compact disc device 100, a video player may be used as an input device, or data from a network may be input. The input data may be analog data or digital data.

Further, the data conversion apparatus of the present invention has a structure shown in FIG.
As shown in, it may be present in a separate housing,
As shown in FIG. 28, the printer 66, the scanner 68, the facsimile device 69, and other peripheral devices may be housed in the housing of the peripheral device. In addition, the present invention may be a case where it exists as a part of a system board such as a television camera, a measuring machine, and a computer. Although not shown in FIG. 28, each device shown in FIG. 28 may be connected via a local area network to transmit mutually encoded information. Further, a case in which information encoded using a wide area network such as ISDN is transmitted and received may be used.

[0157]

As described above, in the data conversion apparatus according to the present invention, the configuration of the sub-conversion processing unit is changed so that the input data can be partially processed in parallel. It is useful as an encryption device of an information processing device or a data communication device.

Further, since the same element is repeatedly used by providing a feedback loop in the circuit, it is suitable for high-speed processing by reducing the circuit scale of an encryption device or the like.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a data conversion device according to a first embodiment.

FIG. 2 is a configuration diagram illustrating an example of a nonlinear conversion circuit.

FIG. 3 is a configuration block diagram of a data conversion device according to a second embodiment.

FIG. 4 is a diagram showing the identity of the data conversion apparatuses according to the first and second embodiments.

FIG. 5 is a diagram showing another example of the same configuration as the data conversion devices of the first and second embodiments.

FIG. 6 is a diagram illustrating a part of a basic configuration of a data conversion device according to a third embodiment and a configuration of a nonlinear conversion circuit in a sub-conversion processing unit;

FIG. 7 is a connection configuration diagram of the entire sub-conversion processing unit of the data conversion device according to the third embodiment;

FIG. 8 is a view for explaining the data conversion order of the connection device of FIG. 7;

FIG. 9 is a view for explaining a data conversion order of the connection device of FIG. 7;

FIG. 10 is a view for explaining the data conversion order of the connection device of FIG. 7;

FIG. 11 is a diagram illustrating a part of a basic configuration of a data conversion device according to a fourth embodiment and a configuration of a non-linear conversion circuit in a sub-conversion processing unit;

FIG. 12 is a view for explaining connection of some sub-conversion processing units of the data conversion apparatus according to the fourth embodiment and the data conversion order;

FIG. 13 is a diagram showing a basic configuration of a data conversion device according to a fifth embodiment and a configuration of a nonlinear conversion circuit in a sub-conversion processing unit.

FIG. 14 is a configuration block diagram of a data conversion device according to a sixth embodiment.

FIG. 15 is a configuration block diagram of a data conversion device according to a seventh embodiment.

FIG. 16 is a configuration block diagram of a data conversion device according to an eighth embodiment.

FIG. 17 is a block diagram illustrating a configuration of a data conversion device according to a ninth embodiment;

FIG. 18 is a diagram showing a configuration of an external nonlinear conversion circuit in the data conversion device according to the ninth embodiment.

FIG. 19 is a diagram showing a configuration of an internal nonlinear conversion circuit in an internal nonlinear conversion circuit in the data conversion device according to the ninth embodiment;

FIG. 20 is a diagram showing an example of a non-linear element (conversion table) in an internal non-linear conversion circuit in the data conversion device according to the ninth embodiment;

FIG. 21 is a diagram showing an example of a non-linear element (conversion table) in an internal non-linear conversion circuit in the data conversion device according to the ninth embodiment.

FIG. 22 is a diagram showing an example in which the non-linear processing elements in the internal non-linear conversion circuit of FIG. 19 are configured by normal bases using an n-th power circuit on a Galois field.

FIG. 23 is a configuration block diagram of a data conversion device according to the tenth embodiment.

FIG. 24 is a diagram showing a detailed configuration of a data conversion unit in FIG. 23.

FIG. 25 is a configuration block diagram of another data conversion device according to the eleventh embodiment.

FIG. 26 is a diagram summarizing the features of Embodiments 1 to 11;

FIG. 27 is a diagram showing an application example of the data conversion device of the present invention.

FIG. 28 is a diagram showing an application example of the data conversion device of the present invention.

FIG. 29 is a diagram showing a configuration of a conventional data conversion device.

[Explanation of symbols]

121, 122, 123, 124 Sub-conversion processing means, 1
31, 132, 133, 134 Nonlinear conversion circuit, 14
1, 142, 143, 144 exclusive OR, 151
Exclusive OR, 152 Galois field inverse circuit, 153 control means, 154 repetition processing means, 156a, 156b
Data selection means, 157a, 157b Data holding means, 158 Key parameter supply means, 161, 162,
163, 164 sub-conversion processing means, 221, 222, 2
23,224 Sub-conversion processing means, 231,232,23
3,234 Non-linear conversion circuit, 321,322,32
3,324 Internal sub-conversion processing means, 331, 332, 3
33,334 Internal nonlinear conversion circuit, 341,342,
343, 344 Exclusive OR, 351 Internal division means, 352 Internal fusion means, 421, 422 Sub-conversion processing means, 431, 432 Non-linear conversion circuit, 441, 4
42 exclusive OR, 521, 522, 523 internal sub-conversion processing means, 531, 532, 533 internal nonlinear conversion circuit, 541, 542, 543 exclusive OR, 551
Internal division means, 552 Internal fusion means, 621, 62
2,623,624 Sub-conversion processing means, 631,63
2,633,634 Nonlinear conversion circuit, 641,64
2,643,644 Exclusive OR, 721,722,
723 Internal sub-conversion processing means 731, 732, 733
Internal nonlinear conversion circuit, 741, 742, 743, 74
4 Exclusive OR, 761,762,763 Exclusive OR, 831,832,833,834,835,83
6,837,838 External nonlinear conversion means, 841,8
42,843,844,845,846,847,84
8 Exclusive OR, 931, 923, 933 Internal nonlinear conversion means, 941, 942, 943, 944, 945
Exclusive OR, 951 S7 nonlinear transformation, 952a, 9
52b S9 nonlinear transformation, 961, 962, 963, 9
64 Exclusive OR, 971, 972, 973, 97
4,975,976,977,978,979,980
Data converter 971a, 971b Logical product or logical sum, 971c, 971d Exclusive logical sum, 991, 9
92,993,994,995,996,997,99
8 Exclusive OR.

Claims (31)

[Claims] 1. A first non-linear transformation of any two A input data (101) and B input data (102) with a first key parameter (111),
A configuration in which an exclusive OR of the first non-linearly converted output data and the B input data (102) is output as B intermediate data, and the B input data is output as A intermediate data as it is; The data is subjected to a second non-linear transformation using a second key parameter, and the exclusive-OR of the second non-linear transformed output data and the B intermediate data is output as the next B intermediate data. A data conversion device comprising a configuration for outputting data as it is as the next A intermediate data, and cascade-connecting the above configuration to convert the final A intermediate data and B intermediate data into converted output data (103 and 104). 2. A first non-linear conversion circuit (131) and an exclusive OR circuit (141) existing from an input side of a first non-linear conversion to an input side of a second non-linear conversion are converted into a first sub-conversion. A second nonlinear conversion circuit (132) existing between the input side of the second nonlinear conversion and the input side of the next first nonlinear conversion, and an exclusive OR circuit (14)
2) as a second sub-conversion processing unit (122); and an exclusive OR circuit (141) existing from the output side of the first nonlinear conversion to the output side of the second non-linear conversion. Of the non-linear conversion circuit (132) of the first sub-conversion processing unit (16).
1), and an exclusive OR circuit (1) existing from the output side of the second nonlinear conversion to the output side of the next first nonlinear conversion
42) and a case where the first non-linear conversion circuit (133) is used as a second sub-conversion processing unit (162). The first sub-conversion processing unit (121 or 161) The second sub-conversion processing unit (122 or 162) is alternately connected to the required number of stages, and the last stage converts A intermediate data and B intermediate data output from either the first or second sub-conversion processing unit. 2. The data conversion device according to claim 1, wherein the output data is used as output data. 3. When performing the first or second nonlinear conversion,
A input data (10) to the sub-conversion processing unit (221)
A1 input to the A1 input side by dividing 1) by an arbitrary number of digits
The input data (301) and the A2 input data (302) input to the A2 input side are used.
1) is also divided by an arbitrary number of digits into a first divided key parameter or an n-th divided key parameter (311 to 313), and the A1 input data (301) obtained by dividing the A input data (101) is converted to the first divided key parameter. An internal non-linear conversion is performed using the split key parameter (311), and an exclusive OR of the output data subjected to the internal non-linear conversion and the A2 input data (302) is output as first A2 internal intermediate data (306). A2
A first internal sub-conversion processing unit (321) that outputs the input data (302) as it is as first A1 internal intermediate data (305), and a first A1 of the first internal sub-conversion processing unit (321) The internal intermediate data (305) is subjected to internal nonlinear conversion with the second split key parameter (312) as A1 input data, and the output data subjected to the internal nonlinear conversion and the first A2 internal intermediate data (306) are converted to A2 input data. The exclusive OR with the A2 input data is output as the second A2 internal intermediate data (308), and the first A2 internal intermediate data (306) is directly used as the second A1 internal intermediate data (3).
07), the second internal sub-conversion processing unit (32)
2), the first internal sub-conversion processing unit (321) and the second internal sub-conversion processing unit (322) are connected alternately in n stages, and the final A1 internal intermediate data (303) 3. The data conversion apparatus according to claim 2, wherein a non-linear conversion is performed to convert the A2 internal intermediate data (304) into a conversion result (109). 4. In the non-linear conversion in each sub-conversion processing unit, A input data to the sub-conversion processing unit (221) is divided into an arbitrary number of digits to obtain A1 input data and A2 input data. Are also divided by an arbitrary number of digits into a first divided key parameter or an n-th divided key parameter, and the A1 input data obtained by dividing the A input data is subjected to an internal nonlinear conversion using the first divided key parameter. A first internal sub-transformation processing unit that outputs the output data obtained as the first A2 internal intermediate data, and outputs the exclusive OR of the A1 input data and the A2 input data as the first A1 internal intermediate data; The first A1 internal intermediate data of the first internal sub-transformation processing section is subjected to internal non-linear conversion with the second divided key parameter as A1 input data, and is output as second A2 internal intermediate data. A second internal sub-transformation processing unit that performs an exclusive OR operation on the first A1 internal intermediate data and the first A2 internal intermediate data as A1 input data and A2 input data and outputs the result as second A1 internal intermediate data; The first internal sub-transformation processing unit and the second internal sub-transformation processing unit are connected alternately in n stages, and the final stage A1 internal intermediate data and A2 internal intermediate data are combined into a non-linear conversion result. 3. The data conversion device according to claim 2, wherein the data conversion is performed. 5. An arbitrary B input data (1) for any two A input data (101) and B input data (102).
02) with the first key parameter (111), and outputs the exclusive OR of the converted result (451) and the A input data (101) as B intermediate data (462). , And the B input data (1
02) as the A intermediate data (461) as it is, provided with a sub-conversion processing unit (421), and requires a sub-conversion processing unit based on each key parameter using the A intermediate data and B intermediate data as A input data and B input data. A data conversion device having a configuration in which the number of stages is connected and combining the intermediate data of the last stage and the intermediate data of B to obtain output data after conversion. And the B input data to the internal sub-conversion processing unit (521) is divided into an arbitrary number of digits to obtain B1 input data (501) and B2 input data (502). , And the key parameter (11
1) is also divided into an arbitrary number of digits to be a first divided key parameter or an n-th divided key parameter (511-523), and the B1 input data (501) obtained by dividing the B input data (102) is converted to a first divided key parameter. The first in the split key parameter (511)
And outputs the exclusive OR of the output data subjected to the first internal non-linear conversion and the B2 input data (502) as first B2 internal intermediate data (506). (502) is converted to the first B
A first internal sub-conversion processing unit (521) for outputting as one internal intermediate data (505); and a first B1 internal intermediate data (505) of the first internal sub-conversion processing unit (521) as B1 input data. The second non-linear conversion is performed by the second divided key parameter (512), and the output data subjected to the non-linear non-linear conversion and the first B2 internal intermediate data (506) are set as B2 input data, and the exclusive B2 input data is used. The logical sum is output as the second B2 internal intermediate data (508), and the first B2 internal intermediate data (506) is directly used as the second B1 internal intermediate data (5).
07), the second internal sub-conversion processing section (52)
2), the first internal sub-conversion processing unit and the second internal sub-conversion processing unit are connected alternately in n stages, and the final B1 internal intermediate data (503) and B2 internal intermediate data (504) ) Are combined to obtain a conversion result (451) after the non-linear conversion. 6. A position where the exclusive OR operation is performed in each internal sub-transformation processing unit is changed, and an internal nonlinear conversion is performed on the B1 input data to obtain a B2 internal intermediate data output.
The exclusive OR of the 2-input data and the B1 input data is expressed as B1
6. The data converter according to claim 5, wherein the data is output as internal intermediate data. 7. For each of four arbitrary A1 input data (601), A2 input data (701), B1 input data (602), and B2 input data (702), the A1 input data And B1 input data, and between the A2 input data and the B2 input data, a nonlinear conversion and an exclusive OR operation are performed to obtain B1 intermediate data (606) and B2 intermediate data (706), respectively. The A1 intermediate data (6
The data conversion device according to claim 5 or 6, wherein the data conversion device (5) and the A2 intermediate data (705) are used. 8. The method according to claim 1, wherein the A input data and the B input data and the A intermediate data and the B intermediate data are equally divided so that A and B have the same number of digits. The data conversion device according to any one of claims or claim 5. 9. A first step (S1) of outputting B input data as it is as first A intermediate data with respect to any two A input data and B input data; A second step (S2) of performing an exclusive OR of the output data after the non-linear conversion and the B input data and outputting it as first B intermediate data; And a third step (S3) of inputting the first A intermediate data and performing non-linear conversion with the second key parameter, and outputting the output data after the non-linear conversion. And the first B intermediate data, and the second B
A fourth step (S4) of outputting as intermediate data, and repeating the first to fourth steps (S1 to S4),
End with the second or fourth step,
A data conversion method using final A intermediate data and B intermediate data as conversion data. 10. A first step of outputting an exclusive OR of A input data and B input data as first A intermediate data with respect to any two A input data and B input data (S11).
A second step (S12) of non-linearly converting the A input data with a first key parameter and outputting output data after the non-linear conversion as first B intermediate data; A third step (S13) of outputting an exclusive OR with the first B intermediate data as second A intermediate data, and inputting the first A intermediate data and performing non-linear conversion with a second key parameter And a fourth step (S14) of outputting the output data after the non-linear conversion as second B intermediate data. The first to fourth steps (S11 to S14) are repeated, and the second or fourth step is finally performed. A data conversion method in which the steps A and B are completed, and the final A intermediate data and B intermediate data are converted data. 11. The first non-linear conversion circuit (131) and the exclusive OR circuit (141) existing from the input side of the first non-linear conversion to the input side of the second non-linear conversion are converted into a first sub-conversion. The processing unit (121) is a processing unit (121) that includes a second nonlinear conversion existing from the input side of the second nonlinear conversion to the input side of the next first nonlinear conversion.
(132) and the exclusive OR circuit (14)
2) as a second sub-conversion processing unit (122); and an exclusive OR circuit (141) existing from the output side of the first nonlinear conversion to the output side of the second non-linear conversion. Of the non-linear conversion circuit (132) of the first sub-conversion processing unit (16).
1), and an exclusive OR circuit (1) existing from the output side of the second nonlinear conversion to the output side of the next first nonlinear conversion
42) and a configuration in which the first non-linear conversion circuit (133) is used as a second sub-conversion processing unit (162). The first sub-conversion processing unit and the second sub-conversion processing unit The necessary number of stages are alternately connected to the conversion processing unit, a data selection unit (156a and 156b) is added to the input side of the first first sub-conversion processing unit, and one of the last first and second conversion units is added. A data holding unit (157a and 157b) is added to the output side of the sub-conversion processing unit, and a key parameter supply unit (158) is added. First, any two A input data and B input data are selected by the above data selection. Section (156a and 156b), and when the selection is completed, the data holding section (15
7a and 157b) are connected in a feedback manner so as to be selectively inputted, and the conversion process is repeated as many times as necessary. At this time, the key parameter supply unit (158) responds to the repetition conversion process by 2. A key parameter is supplied to the A and B intermediate data output from the data holding units (157a and 157b) in the last round as converted output. Data converter. 12. The method according to claim 1, wherein the arbitrary two A input data and the B input data have the same number of digits, and the first non-linear conversion existing from the input side of the first non-linear conversion to the input side of the second non-linear conversion. The conversion circuit (131) and the exclusive OR circuit (14
1) and an exclusive OR circuit (141) existing from the output side of the first nonlinear transformation to the output side of the second nonlinear transformation.
One of the first and second non-linear conversion circuits (132) as a sub-conversion processing unit, the above-mentioned sub-conversion processing units are connected in a required number of stages, and the data selection units (156a and 156b) , A data holding unit (157a and 157b) is added to the output side of the last sub-conversion processing unit, and a key parameter supply unit (158) is added. Is selected and input by the data selection units (156a and 156b), and when the selection input is completed, the data holding units (157a and 15
7b) is connected in a feedback manner so as to select and input the output, and repeatedly performs the conversion process a required number of times. At that time, the key parameter supply unit (158) transmits the key parameter to each sub-conversion processing unit in response to the repetition conversion process. 2. The data conversion method according to claim 1, wherein the A intermediate data and the B intermediate data output from the data holding units (157a and 157b) are output as converted output data at the last time. apparatus. 13. At the time of the first or second nonlinear conversion, A input data to the sub-conversion processing unit is divided into an arbitrary number of digits to be A1 input data and A2 input data, and a key parameter is also arbitrary. The first divided key parameter or the n-th divided key parameter is divided by the number of digits, and the A1 input data obtained by dividing the A input data is internally nonlinearly transformed by the first divided key parameter. A first internal sub-conversion processing unit that outputs an exclusive OR of data and the A2 input data as first A2 internal intermediate data, and outputs the A2 input data as it is as first A1 internal intermediate data; The first A1 internal intermediate data of the first internal sub-transformation processing unit is internally nonlinearly transformed with the second divided key parameter as A1 input data, and the internally nonlinearly transformed output data and The first A2 internal intermediate data is output as A2 input data, an exclusive OR with the A2 input data is output as second A2 internal intermediate data, and the first A2 internal intermediate data is directly output to the second A1. A second internal sub-conversion processing unit that outputs as internal intermediate data, the first internal sub-conversion processing unit, and the second internal sub-conversion processing unit are connected alternately in n stages. An internal data selection unit is added to the input side of the internal sub-conversion processing unit, and an internal data holding unit is added to the output side of one of the last first and second internal sub-conversion processing units. A key parameter supply unit is added. First, A1 input data and A2 input data are selected and input by the internal data selection unit. When the selection input is completed, feedback is performed so that the output of the internal data holding unit is selected and input next time and thereafter. Connect as many times as needed Repeat internal conversion process,
At this time, the internal key parameter supply unit repeatedly supplies the divided key parameters to each internal sub-conversion processing unit in response to the internal conversion process, and the last time the A1 intermediate data and the A2 intermediate data output from the internal data holding unit are output. A after conversion
3. The data conversion device according to claim 2, wherein the data conversion device performs nonlinear conversion as output data. 14. When nonlinear conversion is performed in each sub-conversion processing unit, A input data to the sub-conversion processing unit is divided by an arbitrary number of digits into A1 input data and A2 input data.
The key parameter is also divided by an arbitrary number of digits into a first divided key parameter or an n-th divided key parameter, and the A1 input data obtained by dividing the A input is subjected to an internal nonlinear conversion using the first divided key parameter. A first internal sub-conversion processing unit that outputs the converted output data as first A2 internal intermediate data, and outputs an exclusive OR of the A1 input data and the A2 input data as first A1 internal intermediate data The first A1 internal intermediate data of the first internal sub-conversion processing section is subjected to internal non-linear conversion as A1 input data with a second divided key parameter, and is output as second A2 internal intermediate data; The exclusive OR of the A1 internal intermediate data and A2 internal intermediate data of A1 input data and A2 input data and outputting the result as second A1 internal intermediate data
, The first internal sub-conversion processing unit, and the second internal sub-conversion processing unit are connected alternately in n stages, and the input side of the first first internal sub-conversion processing unit , An internal data holding unit is added to the output side of the last one of the first and second internal sub-conversion processing units, and an internal key parameter supply unit is added. First, A1 input data and A2 input data are selected and input by the internal data selection unit, and when the selection input is completed, a feedback connection is performed so that the output of the internal data holding unit is selectively input from the next time onward. The internal key parameter supply unit repeatedly supplies the divided key parameter to each internal sub-conversion processing unit in response to the internal conversion process, and outputs the divided key parameter from the internal data holding unit the last time. A1 intermediate data and A2 Data conversion apparatus claims second term, wherein to the non-linear transformation to fit the data and converted the A output data. 15. A conversion to a non-linear conversion in each sub-conversion processing unit
14. The method according to claim 13, wherein the input data is equally divided so as to have the same number of digits, and only the first internal sub-conversion processing unit is connected to a required number of stages.
The data converter according to any one of claims 4 to 7. 16. The first internal sub-conversion processing unit and the second internal sub-conversion processing unit are connected alternately to the required number of stages, and the first first
, An internal data selection unit is added to the input side of the internal sub-conversion processing unit, and an internal data holding unit is added to the output side of the last one of the first and second internal sub-conversion processing units. An internal key parameter supply unit is added. First, B1 input data and B2 input data are selected and input by the internal data selection unit. When the selection input is completed, the output of the internal data holding unit is selected and input next time and thereafter. The internal sub-transformation process is repeated as many times as necessary by making a feedback connection, and at this time, the internal key parameter supply unit repeatedly supplies the divided key parameter to each internal sub-transformation processing unit corresponding to the internal sub-transformation process, The B1 intermediate data and the B2 intermediate data output from the internal data holding unit are combined to obtain the converted B intermediate data in the final round, and the converted B intermediate data is set in the final round. No words A data conversion device according to claim 1. 17. The method of dividing B input data to an internal sub-conversion processing unit in each sub-conversion processing unit is equally divided so as to have an equal number of digits, and only the first internal sub-conversion processing unit is connected to a required number of stages. 17. The data conversion device according to claim 16, wherein: 18. An even-numbered sub-conversion processing section for each key parameter is connected, and a data selection section (156a)
156b), a data holding unit (157a and 157b) at the output side of the last sub-conversion processing unit, and a key parameter supply unit (158). A input data and B input data are selected and input by the data selectors (156a and 156b),
When the selection input is completed, the data holding unit (1
57a and 157b) are connected in a feedback manner so as to be selectively input, and the sub-conversion processing is repeated as many times as necessary. At this time, the key parameter supply unit (158) performs each sub- Supplies key parameters to the
7. The method according to claim 5, wherein in the last round, the A intermediate data and the B intermediate data output from the data holding units (157a and 157b) are converted output data. Data converter. 19. The data according to claim 1, wherein at least one of said non-linear conversion circuits is an n-th power circuit of an element X on a Galois field. Conversion device. 20. The data conversion apparatus according to claim 19, wherein the n-th power circuit of the element X on the Galois field is constituted by a normal basis. 21. At least a part of the nonlinear conversion circuit includes R
6. The data conversion device according to claim 1, wherein an ead only memory is used. 22. At least a part of the nonlinear conversion circuit includes R
The data conversion device according to claim 1 or 5, wherein the data conversion device uses an random access memory. 23. At least a part of the nonlinear conversion circuit includes L
The data converter according to any one of claims 1 to 5, wherein the data conversion device uses an optical circuit. 24. Two exclusive OR circuits (971c and 971d) and two logical operation circuits (971a and 971b) each comprising one of an AND circuit and an OR circuit,
As the data conversion unit (971), the data is added to at least one of the A input side and the B input side of the first sub-conversion processing unit, and the input data to the data conversion unit (971) is converted into two data having an arbitrary digit length. AA data and AB data, the key parameters are divided into corresponding A conversion key parameters (981a) and B conversion key parameters (981b), and the AA data and the A conversion key parameters (981a)
a), a first exclusive OR of the first logically operated output data and the AB data is obtained, and the first exclusive ORed output is obtained. Data A
A second logical operation of the first exclusive ORed output data and the B conversion key parameter is performed as output data after the B data conversion, and the second logically operated output data is A second exclusive OR with the AA data is taken, and the second exclusive ORed output data is used as the output data after the AA data conversion, and the output data after the AA data conversion and the output data after the AB data conversion are obtained. 3. The data conversion device according to claim 2, wherein the data conversion device outputs the combined output data. 25. Data of first and second systems (A and B)
In the data conversion device which inputs the data and performs the non-linear conversion process using the key parameters (111 to 114) and outputs the first and second data (A and B) subjected to the non-linear conversion process, A nonlinear conversion circuit (131-134) for performing a non-linear conversion process on the data (A) using the key parameter, and an exclusive logic for calculating an exclusive OR of the data (A and B) of the first and second systems And a sub-conversion processing unit (121-124 or 161-16) having a sum circuit (141-144).
4), the first sub-conversion processing unit (121 or 161) and the second sub-conversion processing unit (122 or 16)
2), the first and second systems of data (A and B) output from the first sub-conversion processing unit (121 or 161) are output to the second sub-conversion processing unit (122 or 162). 2 and data of the first system (B and A), and the nonlinear conversion circuits (131 and 132 or 132 and 133) of the first and second sub-conversion processing units (121 and 122 or 161 and 162). A) a data conversion device for simultaneously executing the non-linear conversion processes of (a). 26. The data conversion device according to claim 1, wherein the A input data (101) and the B input data (102) are inputted as the first and second systems of data, and the A output data (103) and the B
While outputting the output data (104), the first sub-transformation processing unit (121) performs the first non-linear conversion of the A input data with a first key parameter, and performs the first non-linear conversion. Outputting an exclusive OR of the converted data and the B input data as B intermediate data;
The B input data is output as it is as A intermediate data. The second sub-transformation processing unit (122) receives the A intermediate data, performs a second non-linear conversion with a second key parameter, and (2) outputting the exclusive OR of the converted data subjected to the non-linear conversion and the B intermediate data as B intermediate data, outputting the B intermediate data as it is as A intermediate data, Unit (121) and the second sub-conversion processing unit (122) are connected alternately, and the A intermediate data output from one of the first and second sub-conversion processing units (121 or 122) B intermediate data, A output data and B
26. The data conversion device according to claim 25, wherein the data is output as output data. 27. The data conversion device receives A input data (101) and B input data (102) as first and second data, and outputs A output data (103) and B output data ( 104), and the first sub-transformation processing unit (161) performs a first nonlinear transformation of the A input data with a first key parameter,
Is output as B intermediate data, the exclusive OR of the B input data and the A input data is output as A intermediate data, and the second sub-conversion processing unit (162) ) Receives the A intermediate data, performs a second non-linear conversion with a second key parameter, outputs the second non-linearly converted data as B intermediate data, and outputs the first sub data. Conversion processing unit (16
The B intermediate data output from 1) is input, and the input B
The exclusive OR of the intermediate data and the A intermediate data is output as A intermediate data, and the first sub-conversion processing unit (161) and the second sub-conversion processing unit (162) are alternately connected. Then, A intermediate data and B intermediate data output from one of the first and second sub-conversion processing units (161 or 162) are converted into A output data (1
26. The data conversion device according to claim 25, wherein the data conversion device outputs the data (03) and the B output data (104). 28. The first sub-conversion processing unit (121 or 161 or 125) and the second sub-conversion processing unit (122)
Or 162 or 126), a repetition processing unit (154) for repeating the nonlinear conversion by the basic configuration a predetermined number of times, and a non-linear conversion process and a non-linear conversion process of the first sub-conversion processing unit. A key parameter supply unit (158) for supplying key parameters corresponding to the number of repetition processes as the first key parameter and the second key parameter supplied to the non-linear conversion process of the second sub-conversion processing unit; A intermediate data after the predetermined number of repetitions (107)
And B intermediate data (108) and A output data (103)
26. The data conversion apparatus according to claim 25, wherein the data is output as B and output data (104). 29. Data of first and second systems (A and B)
, And performs nonlinear conversion using the key parameter, and outputs first and second systems of data (A and B) that have been nonlinearly converted. And B), and a non-linear conversion circuit (131) for performing non-linear conversion processing of the first system data (A) using key parameters, and an exclusive OR of the first and second system data. A sub-conversion processing unit (1) having an exclusive-OR circuit (141)
21) and the first and second system data (A and B) output from the sub-conversion processing unit (121),
And a repetition processing unit (1) for repeatedly inputting data as the second system data (A and B) and performing a predetermined number of repetition processes
54) and a key parameter supply unit (158) for supplying a key parameter corresponding to the repetition processing as a key parameter to the nonlinear conversion circuit of the sub-conversion processing unit. 30. The non-linear conversion circuit (231) for internally dividing the input first system data (A) into two first and second divided data (A1 and A2) with an arbitrary number of digits. A division unit (351), and a key parameter supply unit (1) that divides the key parameter into divided key parameters by an arbitrary number of digits and supplies the divided key parameters.
58), and inputs the first and second divided data (A1 and A2), and converts the first divided data (A1) into divided key parameters (311).
To 313), and an internal exclusive OR circuit (341) for calculating the exclusive OR of the first and second divided data (A1 and A2). To 343), the first internal sub-conversion processing unit (321) and the second internal sub-conversion processing unit (321).
The first and second divided data (A1 and A2) output from the first internal sub-conversion processing unit are provided as internal sub-conversion processing units (322) of the second internal sub-conversion processing unit. Inputting as the first divided data (A2 and A1) and simultaneously executing the nonlinear conversion processes of the internal nonlinear conversion circuits (331 and 332) of the first and second internal sub-conversion processing units (321 and 322) 26. The data conversion device according to claim 25, wherein: 31. Data of first and second systems (B and A)
And a non-linear conversion using the key parameter, and outputs the non-linearly converted first and second systems of data (B and A). A sub-conversion processing unit (4) including a non-linear conversion circuit (431) for performing non-linear conversion processing using parameters, and an exclusive-OR circuit (441) for calculating an exclusive OR of data of the first and second systems;
21), and the nonlinear conversion circuit (431) divides the input first-system data (B) into two pieces of first and second divided data (B1 and B2) with an arbitrary number of digits. Internal division part (551)
And a key parameter supply unit (1) that divides the key parameter into divided key parameters by an arbitrary number of digits and supplies the divided key parameters.
58), inputting the first and second divided data (B1 and B2), and performing an nonlinear conversion process on the first divided data (B1) using the divided key parameter. 53
3) and at least two internal sub-conversion processing units (521 to 523) each having an exclusive OR circuit (541 to 543) for calculating an exclusive OR of the first and second divided data. The first internal sub-conversion processing unit (521) includes a first internal sub-conversion processing unit (521) and a second internal sub-conversion processing unit (522).
And the second divided data (B1 and B2) as the second and first divided data (B2 and B1) of the second internal sub-conversion processing unit (522), and input the first and second internal sub-data. Internal nonlinear conversion circuits (531 and 5) of the conversion processing units (521 and 522)
32) A data conversion device, wherein the non-linear conversion process is simultaneously performed.