JP2002044046A - Transmission system, transmitter, reciever, and method for transmission - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology which enables transmission of DS3 signals by a VC-2 path or the like. SOLUTION: A transmitter comprises a generating means which generates the information about the frame division of a received DS3 signal; a dividing means which divides the frame into a plurality of data; a means which adds the information about the frame division to each of the data divided by the dividing means, and then stores the information-added data in different paths; and a means which multiplexes the paths to generate STM-n signals, and then outputs them to the SDH network, On the other hand, a receiver comprises a separating means which receives the STM-n signals outputted from the transmitter through the SDH network, and then separates the paths from the received STM-n signals; and a regenerating means which detects the information about the division from the paths separated by the separating means, and based on the detected information, regenerates the frame from the data stored in the paths.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a technology for transmitting a DS3 signal, and more particularly to a technology for accommodating a DS3 signal in an SDH network.

[0002]

2. Description of the Related Art FIG. 4 shows an SDH (Synchronous Digital).
1 is a configuration diagram of a Hierarchy) transmission system.

[0003] For example, an SDH transmission device 401
Considering the transmission route to the transmission device 403, the route 40
5. SD via the SDH transmission device 402 and the path 406
A route transmitted to the H transmission device 403, a route 408,
Two routes, a route transmitted via the SDH transmission device 404 and a route 407, are conceivable.

Here, conventionally, DS3 (Digital Signal)
Level 3) When accommodating a signal (44.736 Mbps) in the SDH network, the SDH transmission devices 401 to S
Each line setting unit of the DH transmission device 404 is a VC-3 (Virt
ual Container-3) Path switching was performed in units. Therefore, there is no need to consider the transmission delay in the network.

[0005]

Incidentally, there is an SDH transmission apparatus having only a VC function in units of VC-2 and a time division demultiplexing function.

[0006] Therefore, it is convenient if the DS3 signal can be divided and transmitted by the VC-2 path.

However, the DS3 signal is divided into VC
In the case of transmission by the -2 path, if the transmission path is different for each VC-2 path, a transmission delay occurs. For this reason, it was not possible to accurately reproduce the DS3 signal.

Therefore, an object of the present invention is to solve the above-mentioned problems and to provide a technique capable of transmitting a DS3 signal through a VC-2 path or the like.

[0009]

An object of the present invention is to provide a system for accommodating a DS3 signal in an SDH network, the system having a transmitting device and a receiving device, wherein the transmitting device receives the received DS3 signal. Generating means for generating information relating to division of a signal frame; dividing means for dividing the frame into a plurality of data; and adding information relating to the division generated by the generating means to each of the plurality of data divided by the dividing means. Means for storing in different paths,
Means for generating an STM-n signal by multiplexing the path and outputting the generated STM-n signal to the SDH network, wherein the receiving apparatus outputs an STM-n signal from the transmitting apparatus via the SDH network. Said STM-
n signal, and separating means for separating the path from the received STM-n signal; detecting information on the division from the path separated by the separating means; And reproduction means for reproducing the frame from the data stored in the transmission system.

[0010] With this configuration, it is possible to absorb the difference in delay of the transmission path.

In particular, the means for adding information on the division generated by the generation means to each of the plurality of data divided by the division means and storing the data in different paths includes:
A means for storing information on the division in the payload of the path.

[0012] The reproducing means may be a detecting means for detecting the information on the division from the payload of the path separated by the separating means, and the data having the same information on the division detected by the detecting means may be in the same frame. Means for processing as

[0013] Further, the transmitting apparatus has means for receiving a DS3 signal, and the reproducing means has means for outputting the reproduced frame as a DS3 signal.

In particular, said path is a VC-2 path,
The dividing means is means for dividing the frame into seven data.

Alternatively, the path is a VC-11 path, and the dividing means is means for dividing the frame into 30 pieces of data.

Further, the information on the division is frame identification information.

Further, the DS3 signal is a signal defined by ANSI.

Alternatively, the above-mentioned problem is solved by converting the DS3 signal into an STM signal.
A transmitting device for converting the received DS3 signal into a plurality of data, a generating device configured to generate information regarding division of a frame of the received DS3 signal, a dividing device configured to divide the frame into a plurality of data, Means for adding information about the division generated by the generation means to each of the plurality of data divided by the means, and storing the information in different paths,
Means for multiplexing the path to generate an STM-n signal and outputting the generated STM-n signal to the SDH network.

Another problem is that the frame of the DS3 signal is divided and stored in different paths together with information on the division, and the path is multiplexed from the multiplexed STM-n signal into the D signal.
A receiving apparatus for reproducing an S3 signal, comprising: separating means for separating the path from an STM-n signal received via the SDH network; and detecting information on the division from the path separated by the separating means. Based on the detected information, the frame is reproduced from the data stored in the path, and the reproduced frame is
And a reproducing unit that outputs the signal as an S3 signal.

Another object of the present invention is to provide a method of transmitting a DS3 signal via an SDH network using a transmitting device and a receiving device, wherein the transmitting device receives the received DS3 signal.
Dividing the three-signal frame into a plurality of data, the transmitting device generating information on the division of the frame, and the transmitting device adds information on the division to each of the plurality of data; Storing the data in different paths, and the transmitting apparatus multiplexes the paths to generate an STM-n signal.
Outputting an M-n signal to the SDH network; and the receiving device receiving the STM-n signal output from the transmitting device via the SDH network, and receiving the STM-n signal from the received STM-n signal. Separating a path, and the receiving apparatus detecting information on the division from the separated path, and reproducing the frame from the data stored in the path based on the detected information. And a transmission method characterized by having the following.

With these steps, it is possible to absorb the difference in delay of the transmission path.

[0022]

Next, an embodiment of the present invention will be described.

FIG. 1 shows an SDH (Synchronou) according to the present invention.
FIG. 1 is a configuration diagram of a (Digital Hierarchy) transmission system. FIG. 2 is a diagram showing a mapping structure according to the present invention. FIG. 3 is a flowchart according to the present invention.

In FIG. 1, reference numerals 1 and 5 denote DS3 (Digital Sig).
nal Level 3) a terminal device and a DS3 signal (44.7
36 Mbps).

The DS3 signal is an ANSI (American)
National Standard).

Reference numeral 2 denotes a transmitting device, which is a DS3 terminal device 1
Convert the DS3 signal transmitted from the STM-n signal,
Output. The transmission device 2 is incorporated in the SDH transmission device.

Reference numeral 3 denotes an SDH network, which is an STM
A network for transmitting data by the -n signal.

Reference numeral 4 denotes a receiving device, which receives the STM-n signal output from the transmitting device 2 via the SDH network 3, reproduces the DS3 signal from the received STM-n signal, and sends it to the DS3 terminal device 5. Output. The receiving device 4 is incorporated in the SDH transmission device.

The SDH transmission device according to the present invention includes a transmission device 2 and a reception device 4.

Next, the details of the transmission device 2 will be described.

The transmitting device 2 includes a DS3 dividing circuit 21, a multi-frame adding circuit 22, and a VC-2 mapping unit 2.
3, a line setting unit 24, a multiplex conversion unit 25, and a multiplex conversion unit 26.

The DS3 dividing circuit 21 is used for the DS3 terminal 1
Is divided into seven divided data (divided data D ₁ to D ₇ ) and output to the multi-frame adding circuit 22.

The multi-frame addition circuit 22 uses the DS3
Divided data D output from the dividing circuit 21 ₁~ Division data D₇
The same multi-frame information is generated and added to
is there.

Here, the multi-frame information is frame identification information.

For example, when transmitting 7 multiframes, it is composed of 3 bits. In this case, the multi-frame adding circuit 22 generates the multi-frame information of “001 (binary number)” and adds it to the divided data D ₁ to D _{7 of the first} frame. Further, the multi-frame adding circuit 22 generates multi-frame information of “010 (binary number)” and adds it to the divided data D ₁ to D ₇ of the second frame. Further, the multi-frame adding circuit 22 generates multi-frame information “011 (binary number)” and adds the generated multi-frame information to the divided data D ₁ to D ₇ of the third frame. Also, a multi-frame addition circuit 2
2 generates multi-frame information of “100 (binary number)” and adds it to the divided data D ₁ to D ₇ of the fourth frame. Also, the multi-frame addition circuit 22
Generates multi-frame information of “101 (binary number)” and generates divided data D ₁ to D D of the fifth frame.
₇ is added. In addition, the multi-frame addition circuit 22
Generate multi-frame information of “110 (binary number)”,
Is added to the divided data D _{1 ~} divided data D ₇ of sixth frame. Further, the multi-frame adding circuit 22 outputs “1”
Generates multi-frame information 11 (binary number) ", is added to the divided data D _{1 ~} divided data D ₇ of seventh frame.

That is, in the present invention, based on the multi-frame information, the divided data D ₁ to D ₇ are concatenated (concatenated) to reproduce a frame.

The VC-2 mapping unit 23 is a multi-frame
Data D to which frame information is added ₁~ Division data D₇
To the information bit area (path) of the VC-2 path (frame).
Overhead area and fixed stuff bit area
(Excluding the area).

The line setting unit 24 performs line switching for each VC-2 path in order to efficiently accommodate the line in the VC-2.

The multiplex converter 25 and the multiplex converter 26 add a path overhead (VC-2 PO) to each VC-2 path.
H) to form a VC-2, and further perform multiplexing processing to insert a section overhead (STM-N SOH) to generate an STM-n signal.
It sends the Mn signal to the SDH network.

Next, the details of the receiving device 4 will be described.

The receiving apparatus 4 includes a demultiplexing unit 41, a demultiplexing unit 42, a line setting unit 43, and VC-2 demapping unit 44, a multi-frame detecting circuit 45 ₁ ~ multiframe detecting circuit 45 _7, a frame aligner 46 _1-frame aligner 46 _7, constituted by a DS3 reproduction circuit 47.

The demultiplexing unit 41 and the demultiplexing unit 42
It demultiplexes the STM-n signal received via the DH network and performs a demultiplexing process for extracting a VC-2 path by identifying a path overhead (VC-2 POH). Then, the demultiplexing unit 41 and the demultiplexing unit 42 output the extracted VC-2 path to the line setting unit 43.
Is output to

The line setting unit 43 edits the VC-2 path output by the demultiplexing unit 41 and the demultiplexing unit 42 in VC-2 path units, and converts the VC-2 path edited by the VC-2 path into a VC-2 data. Output to the mapping unit 44.

The VC-2 demapping unit 44 extracts the information stored in the information bit area from the VC-2 path output from the line setting unit 43, and
5 and outputs ₁ to the multi-frame detecting circuit 45 _7.

The multi-frame detecting circuit 45 ₁ ~ multiframe detecting circuit 45 _7, VC-2 demapping section 44
Detects the multi-frame information embedded in the information stored in the information bit area output by the controller, and detects the detected multi-frame information and the information stored in the information bits output by the VC-2 demapping unit 44. the and outputs the frame aligner 46 _1-frame aligner 46 _7.

The frame aligner 46 _1-frame aligner 46 ₇ writes information multiframe detecting circuits 45 ₁ to the multi-frame detecting circuit 45 ₇ is stored in the information bits and outputs to the memory. The frame aligner 46 _1-frame aligner 46 _7, multi-frame detecting circuit 45 ₁ ~ multiframe detection circuit 45
₇ is based on the multi-frame information output, reads information multiframe detecting circuits 45 1 _to the multi-frame detecting circuit 45 ₇ is stored in the information bits output from the memory, outputs the information to DS3 reproducing circuit 47 Is what you do.

[0047] For example, the frame aligner 46 _1-frame aligner 46 _7, at the stage of inputting the same multi-frame information, the multi-frame detecting circuit from the memory 45 ₁
Reads the information-multi-frame detecting circuit 45 ₇ is stored in the information bits output, DS3 reproducing circuit 47
Output to That is, the frame aligner 46 _1-frame aligner 46 _7, and absorbs the difference of the transmission path delay generated in the SDH network.

The DS3 reproducing circuit 47, the divided data _{D 8-divided} data _{D 14} of frame aligner 46 _1-frame aligner 46 ₇ has output reproduced frame of DS3 signal, and sent to the DS3 terminal 2. That is, D
The S3 reproduction circuit 47 performs the division data D ₈ to the division data D
₁₄ are sequentially output to the DS3 terminal device 5 at a transmission rate of 44.736 Mbps (transmission rate of the DS3 signal).

Next, the mapping structure of the DS3 signal onto the VC-2 frame will be described with reference to FIG.

One frame of the STM-n signal is transmitted 8000 times per second. That is, the cycle of one frame is 125 μS.

The bit rate of the DS3 signal is 44.736.
Mbps, a data area of 5592 bits is required for 125 μS, which is the basic frame period for multiplexing.

This 5592 bits are divided by 7, and each divided data will contain about 798.85... Bits.

In other words, it is sufficient that there is an area of 799 bits (rounded up below the decimal point) per DS3 signal divided data.

On the other hand, a VC-2 one-pass frame is composed of a path overhead (VC-2 POH), fixed stuff bits (R), and information bits (I).

The number of information bits is 848 bits (106 bytes).

That is, the number of information bits (848 bits) of the VC-2 path is larger than the number of divided data (799 bits) obtained by dividing the DS3 signal into seven.

That is, in the information bit area of the VC-2 path, there are 49 unused information bits (848 bits−799 bits = 49 bits).

Therefore, in the present invention, the DS3 signal can be transmitted by the VC-2 path by embedding the multi-frame information in the 49 unused information bits.

Next, the operation of the present invention will be described.

First, the DS3 terminal 1 outputs a DS3 signal to be transmitted to the DS3 terminal 5 to the transmitter 2.

[0061] The DS3 dividing circuit 21
The frame of the DS3 signal received from is divided into seven pieces of divided data (divided data D ₁ to D ₇ ) (step 101) and output to the multi-frame adding circuit 22.

The multi-frame addition circuit 22 uses the DS3
Divided data D output from the dividing circuit 21 ₁~ Division data D₇
To generate the same multi-frame information (step 1)
02).

The multi-frame adding circuit 22 converts the multi-frame information generated in step 102 into divided data D ₁
Each was added to ~ divided data _{D 7,} and outputs the VC-2 mapping unit 23. The VC-2 mapping unit 23 converts the divided data D ₁ to D ₇ to which the multi-frame information is added into an information bit area (a path overhead area) and a fixed stuff bit area of a (frame of) a VC-2 path. (Area excluding) (step 10)
3).

Next, the line setting unit 24 performs line switching for each VC-2 path in order to efficiently accommodate the line in the VC-2. Then, the multiplex conversion unit 25 and the multiplex conversion unit 2
6 is a path overhead (VC-2) for each VC-2 path.
POH) to form a VC-2, and further perform multiplexing processing to insert a section overhead (STM-N SOH) to generate an STM-n signal, and transfer the generated STM-n signal to the SDH network. It is sent (step 104).

The demultiplexing unit 41 and the demultiplexing unit 42
The STM-n signal received via the DH network is demultiplexed, and a demultiplexing process for extracting a VC-2 path by identifying a path overhead (VC-2 POH) is performed. The demultiplexing unit 41 and the demultiplexing unit 42
Outputs the extracted VC-2 path to the line setting unit 43 (step 105).

The line setting unit 43 edits the VC-2 path output by the demultiplexing unit 41 and the demultiplexing unit 42 in VC-2 path units, and converts the VC-2 path edited by the VC-2 path into a VC-2 data. Output to the mapping unit 44.

The VC-2 demapping unit 44 extracts the information stored in the information bit area from the VC-2 path output from the line setting unit 43, and
5 and outputs ₁ to the multi-frame detecting circuit 45 _7.

Then, the multi-frame detecting circuits 45 ₁ to 45 ₁
Multi-frame detecting circuit 45 ₇ detects multiframe information embedded in the information which the VC-2 demapping unit 44 have been stored in the information bit region outputted, and multi-frame information detection, VC-2 de and outputs the information mapping unit 44 is stored in the information bits and outputs a frame aligner 46 _1-frame aligner 46 _7.

[0069] frame aligner 46 _1-frame aligner 46 ₇ writes information multiframe detecting circuits 45 ₁ to the multi-frame detecting circuit 45 ₇ is stored in the information bits and outputs to the memory. The frame aligner 46 _1-frame aligner 46 _7, multi-frame detecting circuit 45 ₁ ~ multiframe detection circuit 45
₇ is based on the multi-frame information output, reads information multiframe detecting circuits 45 1 _to the multi-frame detecting circuit 45 ₇ is stored in the information bits output from the memory, outputs the information to DS3 reproducing circuit 47 I do.

[0070] For example, the frame aligner 46 _1-frame aligner 46 _7, at the stage of inputting the same multi-frame information, the multi-frame detecting circuit from the memory 45 ₁
Reads the information-multi-frame detecting circuit 45 ₇ is stored in the information bits output, DS3 reproducing circuit 47
Output to

[0071] DS3 reproducing circuit 47, the divided data _{D 8-divided} data _{D 14} of frame aligner 46 _1-frame aligner 46 ₇ has output reproduced frame of DS3 signal, and sent to the DS3 terminal 2. That is, D
The S3 reproduction circuit 47 performs the division data D ₈ to the division data D
₁₄ are sequentially output to the DS3 terminal device 5 at a transmission speed of 44.736 Mbps (transmission speed of the DS3 signal) (step 106).

Although the above description has been made on the assumption that reproduction is made into DS3 frames using multi-frame information, the present invention is not limited to this information.

For example, the multi-frame adding circuit 22 can be replaced by a so-called time stamp circuit (not shown). More specifically, the same time information is divided by the time stamp circuit into divided data D ₁ to D _7.
, The concatenation of VC-2 can be established.

In the above description, the divided data D ₁
Having described the ~ divided data _{D 7} as storing the VC-2 path, the present invention is not limited to the VC-2 path, it may be a VC11 path or VC-1 path.

For example, the present invention can be applied to a case where the mapping is replaced with mapping to a VC-11 path.

That is, the configuration is such that the DS3 signal is distributed to 30 divided data.

5592 bits (DS per 125 μS
(3 data areas) is divided by 30 to store about 186.4 bits per divided data.

Here, since the number of information bits per pass of the VC-11 is 200 bits, 13 unused information bits can be used. Therefore, a configuration is adopted in which concatenation information is embedded in this area.

[0079]

[Effect] The DS3 signal is transferred to the VC-2 path, the VC-11 path,
It can be transmitted on the VC-1 path. A DS3 signal can be transmitted even in an SDH transmission device having only a VC-2 unit time division multiplexing / demultiplexing function.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an SDH transmission system according to the present invention.

FIG. 2 is a diagram showing a mapping structure according to the present invention.

FIG. 3 is a flowchart according to the present invention.

FIG. 4 is a configuration diagram of an SDH transmission system.

[Explanation of symbols]

 1,5 terminal device 2 transmitting device 3 SDH network 4 receiving device

Claims (11)

[Claims] 1. A system for accommodating a DS3 signal in an SDH network, the system including a transmitting device and a receiving device, wherein the transmitting device generates information on division of a frame of the received DS3 signal. A dividing unit that divides the frame into a plurality of data; a unit that adds information about the division generated by the generating unit to each of the plurality of data divided by the dividing unit and stores the information in different paths. Means for generating an STM-n signal by multiplexing the path, and outputting the generated STM-n signal to the SDH network, wherein the receiving device receives a signal from the transmitting device via the SDH network. The output STM-n signal is received, and the received ST
Separating means for separating the path from the Mn signal; detecting information related to the division from the path separated by the separating means; based on the detected information, determining the data stored in the path; A transmission system comprising: a reproducing unit that reproduces a frame. 2. A means for adding information on division generated by the generation means to each of a plurality of data divided by the division means and storing the data and information on the division in different paths. The transmission system according to claim 1, wherein the transmission system stores the data in a payload. 3. The reproducing means comprises: detecting means for detecting the information on the division from the payload of the path separated by the separating means; and the same frame having the same information on the division detected by the detecting means. The transmission system according to claim 1, further comprising: means for performing processing. 4. The transmission apparatus according to claim 1, wherein the transmitting device has a unit for receiving a DS3 signal, and the reproducing unit has a unit for outputting the reproduced frame as a DS3 signal. The transmission system according to any one of the above. 5. The apparatus according to claim 1, wherein said path is a VC-2 path, and said dividing means is means for dividing said frame into seven data. Transmission system. 6. The apparatus according to claim 1, wherein said path is a VC-11 path, and said dividing means is means for dividing said frame into 30 pieces of data. Transmission system. 7. The transmission system according to claim 1, wherein the information on division is frame identification information. 8. The transmission system according to claim 1, wherein the DS3 signal is a signal defined by ANSI. 9. A transmitting apparatus for converting a DS3 signal into an STM-n signal and outputting the STM-n signal to an SDH network, comprising: generating means for generating information on frame division of a received DS3 signal; Division means for dividing into a plurality of data; means for adding information about the division generated by the generation means to each of the plurality of data divided by the division means; and storing the information in different paths. And a means for outputting the generated STM-n signal to the SDH network. 10. A receiving apparatus for dividing a frame of a DS3 signal and storing the divided frame together with information on the division on a different path, and reproducing the DS3 signal from an STM-n signal in which the path is multiplexed. Separating means for separating the path from the STM-n signal received via the path, detecting information on the division from the path separated by the separating means, and storing the information in the path based on the detected information. Playing the frame from the data,
A reproducing unit for outputting the reproduced frame as a DS3 signal. 11. A DS and DS using a transmitting device and a receiving device.
A method of transmitting three signals via an SDH network, wherein the transmitting device divides a received DS3 signal frame into a plurality of data, and the transmitting device generates information on the division of the frame. The transmitting device adds the information about the division to each of the plurality of data, and stores the information in different paths. The transmitting device multiplexes the paths to generate an STM-n signal, Outputting the generated STM-n signal to the SDH network; and the receiving device receives the STM-n signal output from the transmitting device via the SDH network,
Separating the path from the received STM-n signal; and the receiving device detects information related to the division from the separated path, and stores the information in the path based on the detected information. Reproducing the frame from the data.