JP2002043368A - Electric circuit device and manufacturing method therefor - Google Patents
Electric circuit device and manufacturing method thereforInfo
- Publication number
- JP2002043368A JP2002043368A JP2000224061A JP2000224061A JP2002043368A JP 2002043368 A JP2002043368 A JP 2002043368A JP 2000224061 A JP2000224061 A JP 2000224061A JP 2000224061 A JP2000224061 A JP 2000224061A JP 2002043368 A JP2002043368 A JP 2002043368A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- multilayer printed
- bga
- bump
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、ボールグリッドア
レイを実装する多層プリント基板の構造と、その多層プ
リント基板を用いた電気回路装置とその製造方法に関す
る。The present invention relates to a structure of a multilayer printed circuit board on which a ball grid array is mounted, an electric circuit device using the multilayer printed circuit board, and a method of manufacturing the same.
【0002】[0002]
【従来の技術】パソコンや高速デジタル・データ処理を
行う各種機器で用いられているLSIパッケージでは、
多ピン化と高速化が進展している。そのため、従来のQ
FP(quad flat packege)タイプか
らボールグリッドアレイ(以下、BGAと称す)に移行
しつつある。2. Description of the Related Art LSI packages used in personal computers and various devices for performing high-speed digital data processing include:
Increasing the number of pins and speeding up are progressing. Therefore, the conventional Q
The FP (quad flat package) type is shifting to a ball grid array (hereinafter referred to as BGA).
【0003】このBGAを用いた実装構造体は、例えば、
図13に、多層プリント基板にBGAを実装した断面図
で示すような構造である。A mounting structure using this BGA is, for example,
FIG. 13 shows a structure as shown in a sectional view in which a BGA is mounted on a multilayer printed circuit board.
【0004】BGA102は球形状のはんだボール電極
107(単に、はんだボールとも称することがある)を
半導体素子の下面に有している。多層プリント基板10
1は、下層より導体層103と絶縁層104を交互に積
み重ねたもので、下層の導体層103と上層の導体層1
03とは、同じく導体層であるスルホールビア105で
接続されている。導体層103は、主に銅メッキにより
配線や電極として形成されたものである。多層プリント
基板101の表面に位置する導体層103で、BGA1
02や他の電子部品とのはんだ接合に使用される導体層
103を特に電極と呼んでいる。The BGA 102 has a spherical solder ball electrode 107 (sometimes simply referred to as a solder ball) on the lower surface of a semiconductor element. Multilayer printed circuit board 10
Numeral 1 denotes a structure in which conductor layers 103 and insulating layers 104 are alternately stacked from the lower layer. The lower conductor layer 103 and the upper conductor layer 1
03 is connected by a through-hole via 105 which is also a conductor layer. The conductor layer 103 is formed as a wiring or an electrode mainly by copper plating. The conductor layer 103 located on the surface of the multilayer printed board 101
The conductor layer 103 used for soldering with the electronic component 02 and other electronic components is particularly called an electrode.
【0005】この電極103(導体層)は多層プリント
基板101に平行に設けられており、それ以外の多層プ
リント基板101の表面に位置する導体層103(つま
り配線)は、ソルダレジスト106によりコーティング
されており、配線の断線やショートを防止している。The electrode 103 (conductor layer) is provided in parallel with the multilayer printed board 101, and the other conductor layer 103 (ie, wiring) located on the surface of the multilayer printed board 101 is coated with a solder resist 106. To prevent disconnection and short circuit of the wiring.
【0006】この多層プリント基板101上の電極10
3に、BGA102の有する球形状のはんだボール電極
107を位置合わせして搭載し、リフロー炉などを用い
て高温雰囲気に晒すことにより、BGA102が有する
球形状のはんだボール電極107が溶融し、多層プリン
ト基板101上の電極103(配線)と接合する。The electrode 10 on the multilayer printed circuit board 101
3, the spherical solder ball electrode 107 of the BGA 102 is positioned and mounted, and is exposed to a high-temperature atmosphere using a reflow furnace or the like, so that the spherical solder ball electrode 107 of the BGA 102 is melted and multilayer printed. It is bonded to the electrode 103 (wiring) on the substrate 101.
【0007】[0007]
【発明が解決しようとする課題】しかしながら上述の技
術では、以下に示すような課題が存在する。すなわち、
BGA102を実装した多層プリント基板101を、通
電と切断を繰り返したり、温度変化の激しい環境下に晒
すと、BGA102や、多層プリント基板101は熱膨
張と熱収縮を繰り返す。However, the above-described technology has the following problems. That is,
When the multilayer printed circuit board 101 on which the BGA 102 is mounted is repeatedly energized and cut, or exposed to an environment where the temperature changes drastically, the BGA 102 and the multilayer printed circuit board 101 repeat thermal expansion and thermal contraction.
【0008】その際の熱膨張と熱収縮については、図1
3に示したように、矢印A(矢印108)は、BGA1
02の熱膨張と熱収縮の大きさと方向を示し、一方、矢
印Bは、多層プリント基板101の熱膨張と熱収縮の大
きさと方向を示している。つまり、多層プリント基板1
01の熱膨張や熱収縮は、BGA102より一般的に大
きい傾向が示されている。FIG. 1 shows the thermal expansion and thermal contraction at that time.
As shown in FIG. 3, arrow A (arrow 108) points to BGA1
02 indicates the magnitude and direction of thermal expansion and thermal contraction, while arrow B indicates the magnitude and direction of thermal expansion and thermal contraction of the multilayer printed circuit board 101. That is, the multilayer printed circuit board 1
01 has a tendency to be generally larger than the BGA 102 in thermal expansion and thermal contraction.
【0009】図14は、図13の球形状のはんだボール
電極の一つの周辺を拡大した図である。矢印Cは、図1
3で示したBGA102と多層プリント基板101との
熱膨張差を示しており、多層プリント基板101はBG
A102に対しBGA102の中心より外側に伸び縮み
する。これを繰り返すうちに、多層プリント基板101
上の電極103とBGA102の有する球形状のはんだ
ボール電極107との接合端部(交線)に亀裂111が
入ることにより、最終的には電極103とBGAが破断
してしまい、オープン不良を引き起こすという問題があ
った。FIG. 14 is an enlarged view of the periphery of one of the spherical solder ball electrodes of FIG. Arrow C corresponds to FIG.
3 shows a difference in thermal expansion between the BGA 102 and the multilayer printed board 101 shown in FIG.
It expands and contracts outside the center of BGA 102 with respect to A 102. While repeating this, the multilayer printed circuit board 101
When a crack 111 is formed at a joint end (intersecting line) between the upper electrode 103 and the spherical solder ball electrode 107 of the BGA 102, the electrode 103 and the BGA eventually break, causing an open defect. There was a problem.
【0010】近年、BGAの球形状のはんだボール電極
のピッチは0.5mm以下という狭ピッチ化の傾向にあ
り、そのため球形状のはんだボール電極の接合面積は益
々小さくなる傾向にあり、オープン不良が多発する事が
予測される。[0010] In recent years, the pitch of the spherical solder ball electrodes of BGA tends to be as narrow as 0.5 mm or less, so that the bonding area of the spherical solder ball electrodes tends to be further reduced, and open defects are reduced. It is expected to occur frequently.
【0011】また、ノート型パソコンに使用される中央
演算装置等は、BGAの形態をとって高密度に実装され
ているものが多く、その性能は数ヶ月毎に向上してい
る。そのためより性能がより優れた中央演算装置に取り
替えようとしても、中央演算装置に用いられているBG
Aは、高密度に実装されているため、それを取り外して
付け替えるリペアが困難であった。In addition, many of the central processing units and the like used in notebook type personal computers are mounted in high density in the form of BGA, and the performance thereof is improving every few months. Therefore, even if it is attempted to replace the central processing unit with a higher performance, the BG used in the central processing unit
Since A is mounted at a high density, it is difficult to remove and replace it.
【0012】本発明はこれらの事情にもとづいてなされ
てもので、多層プリント基板の電極にBGAを実装する
際に、電極とBGAとの界面破断を防止して高信頼性を
実現し、また、BGAのリペアを容易に行える電気回路
装置とその製造方法を提供することを目的としている。The present invention has been made in view of these circumstances. Therefore, when mounting a BGA on an electrode of a multilayer printed circuit board, it is possible to prevent interface breakage between the electrode and the BGA to realize high reliability. An object of the present invention is to provide an electric circuit device capable of easily repairing a BGA and a method of manufacturing the same.
【0013】[0013]
【課題を解決するための手段】請求項1の発明による手
段によれば、電極を有する配線基板と、バンプを介して
電気的に接続されるよう配置された半導体素子とを有す
る電気回路装置において、前記バンプの表面と前記電極
の表面とがなす交線を含む仮想平面に対して前記電極の
表面が斜交していることを特徴とする電気回路装置であ
る。According to the first aspect of the present invention, there is provided an electric circuit device having a wiring substrate having electrodes and a semiconductor element arranged to be electrically connected via bumps. An electric circuit device, wherein the surface of the electrode is obliquely formed with respect to an imaginary plane including a line of intersection between the surface of the bump and the surface of the electrode.
【0014】また請求項2の発明による手段によれば、
電極を有する配線基板と、バンプを介して電気的に接続
されるよう配置された半導体素子とを有する電気回路装
置において、少なくとも前記電極の表面と前記バンプの
表面とにより形成される接合端部がなす境界線を含む仮
想平面に対して前記電極の表面が斜交していることを特
徴とする電気回路装置である。According to the second aspect of the present invention,
In an electric circuit device having a wiring board having electrodes and a semiconductor element arranged to be electrically connected via bumps, at least a joint end formed by the surface of the electrodes and the surface of the bumps An electric circuit device, wherein a surface of the electrode is oblique to a virtual plane including a boundary line to be formed.
【0015】また請求項3の発明による手段によれば、
前記電極は、配線基板の主面に対して凹形状の表面を有
する電極であり、バンプは、前記凹形状を覆うように配
置されていることを特徴とする電気回路装置である。According to the third aspect of the present invention,
The electric circuit device is characterized in that the electrode is an electrode having a concave surface with respect to the main surface of the wiring board, and the bump is arranged to cover the concave shape.
【0016】また請求項4の発明による手段によれば、
前記配線基板の表面に設けられた電極上にバンプを配置
し、前記バンプを加熱することにより前記バンプと前記
電極とを接合させ、前記バンプの表面と前記電極の表面
とがなす交線を含む仮想平面に対して前記電極の表面が
斜交するよう構成する工程を具備することを特徴とする
電気回路装置の製造方法である。According to the means of the invention of claim 4,
A bump is arranged on an electrode provided on the surface of the wiring substrate, and the bump and the electrode are joined by heating the bump, and a crossing line formed between the surface of the bump and the surface of the electrode is included. A method for manufacturing an electric circuit device, comprising a step of configuring the surface of the electrode to be oblique to a virtual plane.
【0017】また請求項5の発明による手段によれば、
前記配線基板の表面に設けられた電極上にバンプを具え
る電気部品を配置し、前記電気部品を前記配線基板に対
して押圧保持することにより前記バンプと前記電極との
接合を保持させ、前記バンプの表面と前記電極の表面と
がなす交線を含む仮想平面に対して前記電極の表面が斜
交するよう構成する工程を具備することを特徴とする電
気回路装置の製造方法である。According to the fifth aspect of the present invention,
Placing an electrical component having a bump on an electrode provided on the surface of the wiring board, holding the bump and the electrode by pressing and holding the electrical component against the wiring board, A method for manufacturing an electric circuit device, comprising a step of configuring the surface of the electrode so as to obliquely intersect with a virtual plane including a line of intersection between the surface of the bump and the surface of the electrode.
【0018】[0018]
【発明の実施の形態】以下に、本発明の実装方法とその
実装構造体の構造について、図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The mounting method of the present invention and the structure of the mounting structure will be described below with reference to the drawings.
【0019】図1は本発明の多層プリント基板とBGA
の構造の側断面で、多層プリント基板にBGAを位置合
わせをして搭載しようとした際の側面断面図である。FIG. 1 shows a multilayer printed circuit board and a BGA according to the present invention.
FIG. 3 is a side cross-sectional view of the structure of FIG. 1 when a BGA is aligned and mounted on a multilayer printed circuit board.
【0020】多層プリント基板1はエポキシ樹脂を用い
たもので、下層より導体層である配線3と絶縁層4とを
交互に積層したもので、下層の配線3と上層の配線3と
は、導体であるスルホールビア5で接続されている。そ
して、多層プリント基板1の表面には、BGA2の多層
プリント基板1側に形成しているバンプである球形状の
はんだボール電極7と、はんだ接合するために設けられ
た表面電極8が形成されている。The multilayer printed circuit board 1 is made of epoxy resin, and is formed by alternately laminating wirings 3 as conductor layers and insulating layers 4 from the lower layer. The lower wiring 3 and the upper wiring 3 are made of a conductor. Are connected by through-hole vias 5. On the surface of the multilayer printed board 1, a spherical solder ball electrode 7 as a bump formed on the multilayer printed board 1 side of the BGA 2 and a surface electrode 8 provided for solder bonding are formed. I have.
【0021】この表面電極8は、多層プリント基板1の
内側に、バンプであるボール電極7の表面と表面電極8
の表面とがなす交線を含む仮想平面に対して表面電極8
の表面が斜交して形成されている。つまり、表面電極8
は、多層プリント基板1の中央に対して先細の円錐面を
形成している。そのため、多層プリント基板1の中央面
に対しての平行面は有していない。この円錐面がBGA
2に形成された、はんだボール電極7と接続するように
なっている。The surface electrode 8 is provided on the inside of the multilayer printed board 1 with the surface of the ball electrode 7 as a bump and the surface electrode 8.
Surface electrode 8 with respect to an imaginary plane including the line of intersection of
Are formed obliquely. That is, the surface electrode 8
Forms a tapered conical surface with respect to the center of the multilayer printed circuit board 1. Therefore, the multilayer printed circuit board 1 does not have a plane parallel to the center plane. This conical surface is BGA
2 and is connected to the solder ball electrode 7.
【0022】なお、それ以外個所の多層プリント基板1
の表面に形成されている導体層である配線3は、多層プ
リント基板1の底面に対して平行に形成され、ソルダレ
ジスト6によりコーティングされて、配線3の断線やシ
ョートを防止している。また、配線3や表面電極8は、
主に銅めっきにより形成されている。The multi-layer printed circuit board 1 at other locations
The wiring 3, which is a conductor layer formed on the surface of the wiring 3, is formed parallel to the bottom surface of the multilayer printed circuit board 1 and is coated with a solder resist 6 to prevent the wiring 3 from being disconnected or short-circuited. In addition, the wiring 3 and the surface electrode 8
It is mainly formed by copper plating.
【0023】BGA2は、BGA基板31上に半導体素
子32が搭載され、半導体素子32上の電極33がBG
A基板31の表面側電極34と金ワイヤ35により接合
されている。また、BGA基板31の表面側電極34は
スルホールビア36を介して裏面側電極37と接合され
ており、この裏面側電極37にははんだボール電極7が
設けられている。The BGA 2 has a semiconductor element 32 mounted on a BGA substrate 31 and an electrode 33 on the semiconductor element 32 is
It is joined to the surface side electrode 34 of the A substrate 31 by the gold wire 35. The front-side electrode 34 of the BGA substrate 31 is joined to the back-side electrode 37 via a through-hole via 36, and the back-side electrode 37 is provided with the solder ball electrode 7.
【0024】なお、はんだボール電極7が接合されてい
る裏面側電極37は、はんだボール電極7が接合されて
いないソルダーレジスト37´より薄く形成されてい
る。また、半導体素子37は、エポキシ樹脂等の封止材
38で封止されている。The back surface electrode 37 to which the solder ball electrode 7 is joined is formed thinner than the solder resist 37 'to which the solder ball electrode 7 is not joined. The semiconductor element 37 is sealed with a sealing material 38 such as an epoxy resin.
【0025】これらの構成により、図2に示すように、実
装装置(不図示)により、多層プリント基板1上の表面
電極8に、BGA2の有する球形状のはんだボール電極
7を位置合わせした後に密接させて搭載する。With these configurations, as shown in FIG. 2, a spherical solder ball electrode 7 of the BGA 2 is aligned with the surface electrode 8 on the multilayer printed circuit board 1 by a mounting apparatus (not shown), and then closely contacted. Let it be mounted.
【0026】また、上述の実施の形態では、ソルダーレ
ジスト6の構造を図1に示したようにクリアランス構
造、すなわち、多層プリント基板1の上に形成された
(BGAのはんだボール電極と接合するための)表面電
極8に掛からないようにソルダーレジスト6が形成され
ているが、ソルダーレジストの構造は、図3に示すよう
に、オーバーレジスト構造、すなわち、多層プリント基板
1の上に形成された表面電極8に一部が掛かるようにソ
ルダーレジスト6´を形成してもよい。なお、その際の
接合後の形状は、図4に示したような形状になる。な
お、図3及び図4においては、図1及び図2と同一部分
には同一符号を付して個々のその説明を省略する。In the above-described embodiment, the structure of the solder resist 6 is a clearance structure as shown in FIG. 1, that is, a structure formed on the multilayer printed circuit board 1 (for bonding with a solder ball electrode of BGA). 3) The solder resist 6 is formed so as not to cover the surface electrode 8. The solder resist has an over-resist structure as shown in FIG. 3, that is, the surface formed on the multilayer printed circuit board 1. The solder resist 6 ′ may be formed so as to partially cover the electrode 8. In this case, the shape after the joining is as shown in FIG. In FIGS. 3 and 4, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and their description is omitted.
【0027】また、多層プリント基板1の絶縁層4にエ
ポキシ樹脂を用いたが、フェノール樹脂等を適宜使用す
ることができる。また、導体層の配線3として無電解銅
めっきを使用したが、電解銅めっきや金スパッタ等を適
宜使用することができる。Although the epoxy resin is used for the insulating layer 4 of the multilayer printed board 1, a phenol resin or the like can be used as appropriate. Further, although electroless copper plating is used as the wiring 3 of the conductor layer, electrolytic copper plating, gold sputtering, or the like can be used as appropriate.
【0028】次に、図5に示すように、図1及び図2で
示した、BGA2を搭載した多層プリント基板1を、リ
フロー炉(不図示)等を用いて高温雰囲気に晒す。それ
により、BGA2に形成されているはんだボール電極7
が溶融し、多層プリント基板1上の円錐状の表面電極8
の内部の壁面に密接して充填される。その後、常温で所
定時間を経過させて、はんだボール電極7と表面電極8
とを固着接合して実装構造体を形成する。Next, as shown in FIG. 5, the multilayer printed circuit board 1 on which the BGA 2 shown in FIGS. 1 and 2 is mounted is exposed to a high-temperature atmosphere using a reflow furnace (not shown) or the like. Thereby, the solder ball electrode 7 formed on the BGA 2
Is melted, and the conical surface electrode 8 on the multilayer printed circuit board 1 is melted.
The inner wall is filled closely. Then, after a predetermined time has passed at room temperature, the solder ball electrode 7 and the surface electrode 8
Are fixedly joined to form a mounting structure.
【0029】図6は、このようにBGA2を実装した多
層プリント基板1を、通電と切断とを繰り返したり、温
度変化の激しい環境下にさらした際の球形状のはんだボ
ール電極7の一つを、模式的に拡大した拡大図である。
なお、図2と同一個所には同一符号を付して個々の説明
を省略する。FIG. 6 shows one of the spherical solder ball electrodes 7 when the multi-layer printed circuit board 1 on which the BGA 2 is mounted is repeatedly subjected to energization and cutting, or exposed to an environment where temperature changes drastically. It is the enlarged view which expanded typically.
The same parts as those in FIG. 2 are denoted by the same reference numerals, and their description is omitted.
【0030】矢印10は、BGA2と多層プリント基板
1との熱膨張差のベクトルを示している。多層プリント
基板1はBGA2に対しBGA2の中心より外側に伸び
縮みする。つまり、矢印10の方向に熱応力が生じる。
しかしながらBGA2のはんだボール電極7と多層プリ
ント基板1上の表面電極8との接合界面の剪断方向は矢
印11で示すように、熱応力の方向10とは平行ではな
い。そのため、多層プリント基板1上の電極3とBGA
2に設けられた、はんだボール電極7との界面に亀裂が
入りにくくなり、界面破断を防止する効果がある。An arrow 10 indicates a vector of a difference in thermal expansion between the BGA 2 and the multilayer printed circuit board 1. The multilayer printed board 1 expands and contracts with respect to the BGA 2 outside the center of the BGA 2. That is, thermal stress occurs in the direction of arrow 10.
However, the shearing direction of the bonding interface between the solder ball electrode 7 of the BGA 2 and the surface electrode 8 on the multilayer printed board 1 is not parallel to the direction 10 of the thermal stress, as indicated by the arrow 11. Therefore, the electrode 3 on the multilayer printed circuit board 1 and the BGA
2 has an effect of preventing a crack from being easily formed in the interface with the solder ball electrode 7 and preventing the interface from being broken.
【0031】次に、本発明の多層プリント基板の製造方
法について説明する。Next, a method of manufacturing a multilayer printed board according to the present invention will be described.
【0032】図7は、多層プリント基板のスルーホール
ビアの製造方法の概要を示す模式図である。FIG. 7 is a schematic view showing an outline of a method of manufacturing a through-hole via of a multilayer printed circuit board.
【0033】まず、多層プリント基板1は、下層よりエ
ポキシ樹脂等の絶縁層4の上に、レジスト膜(不図示)
を形成して、無電解銅めっきにより、厚さ約0.018
mmの導体層の配線3を形成し、レジスト膜を除去した
後、その上から厚さ約0.06mm絶縁層4を積層す
る。これを数回繰り返すことにより最表層部以外を形成
する。下層の配線3と上層の配線3とは、約φ0.15
mmのスルホールビア5を形成することにより電気的な
導通を得ている。First, the multilayer printed circuit board 1 is formed by forming a resist film (not shown) on the insulating layer 4 such as an epoxy resin from the lower layer.
To a thickness of about 0.018 by electroless copper plating.
After forming a wiring 3 of a conductor layer having a thickness of 2 mm and removing the resist film, an insulating layer 4 having a thickness of about 0.06 mm is laminated thereon. This is repeated several times to form portions other than the outermost layer. The lower wiring 3 and the upper wiring 3 have a diameter of about φ0.15.
By forming the through-hole via 5 mm, electrical continuity is obtained.
【0034】このスルホールビア5はレーザ加工装置等
で上層の配線3から絶縁層4に孔を明け下層の導体層の
配線3まで貫通させ、貫通孔の内壁に細めっきで導体層
を形成している。The through-hole via 5 is formed by making a hole from the upper wiring 3 to the insulating layer 4 and penetrating the lower conductive layer wiring 3 by a laser processing device or the like, and forming a conductive layer on the inner wall of the through hole by fine plating. I have.
【0035】なお、レーザ加工装置は、レーザ発振器1
2から出力されたレーザ光13を、孔形状を整えるため
のパターンマスク14、プリズム15(又は反射鏡)や
上下に移動するフォーカスレンズ16等で形成した光学
系により導き、導体層の配線3の所定個所に照射して絶
縁層4に所定の貫通孔の加工を行なっている。It should be noted that the laser processing apparatus uses a laser oscillator 1
2 is guided by an optical system formed by a pattern mask 14 for adjusting a hole shape, a prism 15 (or a reflecting mirror), a focus lens 16 moving up and down, and the like. By irradiating a predetermined portion, a predetermined through hole is formed in the insulating layer 4.
【0036】なお、多層プリント基板1上のスホールビ
ア5を形成する際に、レーザ加工装置を用いずに、ドリ
ル等による機械加工によっても、同様な均一形状を得る
ことができ、それらを適宜することが使用できる。In forming the through-hole vias 5 on the multilayer printed circuit board 1, a similar uniform shape can be obtained by machining with a drill or the like without using a laser machining apparatus. Can be used.
【0037】また、図8は、多層プリント基板の表面に
形成する表面電極の断面形状の範囲の説明図である。な
お、各パラメータを以下の通りに定めている。FIG. 8 is an explanatory diagram of the range of the cross-sectional shape of the surface electrode formed on the surface of the multilayer printed circuit board. In addition, each parameter is defined as follows.
【0038】球形状のはんだボール電極の半径:R 絶縁層の厚さ:Z レーザで開ける円錐型の孔の最表層の直径:H レーザで開けた円錐型の孔の頂点からはんだボール電極
の中心までの距離:L レーザで開けた円錐型の孔の中心を通る中心線と孔の表
面との角度:α はんだボール電極のピッチ:P 最表層における配線と配線との間の絶縁層の最小間隔:
S 次に、これらを用いて適正な断面形状の範囲を求める。Radius of spherical solder ball electrode: R Thickness of insulating layer: Z Diameter of outermost layer of conical hole formed by laser: H Center of solder ball electrode from apex of conical hole formed by laser Distance to: L Angle between the center line passing through the center of the conical hole formed by the laser and the surface of the hole: α Pitch of solder ball electrode: P Minimum spacing of the insulating layer between wirings on the outermost layer :
S Next, a range of an appropriate cross-sectional shape is obtained using these.
【0039】まず、tanα=(H/2)/Z…(1)
の関係が成立する。First, tan α = (H / 2) / Z (1)
Is established.
【0040】また、sinα=R/L…(2)の関係が
成立する。Further, the relationship of sin α = R / L (2) is established.
【0041】そこで、レーザで明けた円錐型の孔の中心
を通る中心線と孔の表面との角度(α)の範囲を求め
る。レーザで開ける円錐型の孔の最表層の直径の最大値
をHmaxとすると、H≦Hmax=P−S…(3)の
関係が成立する。αの最大値をαmaxとして、(3)
を(1)に代入して、tanα≦tanαmax=(H
max/2)/Z…(4)のように変形する。(4)を
解くことにより、αの最大値(αmax)が求まる。Therefore, the range of the angle (α) between the center line passing through the center of the conical hole formed by the laser and the surface of the hole is obtained. Assuming that the maximum value of the diameter of the outermost layer of the conical hole formed by the laser is Hmax, the relationship of H ≦ Hmax = PS (3) holds. Let αmax be the maximum value of α, (3)
Is substituted into (1), and tanα ≦ tanαmax = (H
max / 2) / Z... (4) By solving (4), the maximum value of α (αmax) is obtained.
【0042】α≦αmax…(5) 一方、球形状のはんだボール電極7は、多層プリント基
板1上の表面電極8と接しなければならないので、L≦
R+Z…(6)の関係を満たす必要があり、(2)より
L=R/sinα…(7)と変形でき、レーザで明けた
円錐型の孔の中心を通る中心線と孔の表面との最小角度
をαminとすると、L=R/sinα≦R/sinα
min=R+Z…(8)と表せる。Α ≦ αmax (5) On the other hand, since the spherical solder ball electrode 7 must be in contact with the surface electrode 8 on the multilayer printed circuit board 1, L ≦ αmax
It is necessary to satisfy the relationship of R + Z (6). From (2), L = R / sin α (7) can be deformed. When the minimum angle is αmin, L = R / sinα ≦ R / sinα
min = R + Z (8)
【0043】(8)を変形すると、sinαmin=R
/(R+Z)…(9)が求まる。(9)を解くことによ
り、αの最小値(αmin)が求まる。By transforming (8), sinαmin = R
/ (R + Z) (9) is obtained. By solving (9), the minimum value of α (αmin) is obtained.
【0044】αmin≦α…(10) (5)と(10)より、αmin≦α≦αmax…(1
1)が求まる。Αmin ≦ α (10) From (5) and (10), αmin ≦ α ≦ αmax (1
1) is obtained.
【0045】次に、具体例として具体的な数値で計算し
てみると、例えば、以下のような値の場合においてαを
求める。Next, as a specific example, when calculation is performed using specific numerical values, for example, in the case of the following values, α is obtained.
【0046】R=0.15mm Z=0.1mm H=0.3mm P=0.5mm S=0.075mm (3)より、Hmax=0.5mm−0.075mm=
0.425mm (4)より、tanαmax=(0.425mm/2)
/0.1mm 従ってαmax=64.8°となる。R = 0.15 mm Z = 0.1 mm H = 0.3 mm P = 0.5 mm S = 0.075 mm From (3), Hmax = 0.5 mm−0.075 mm =
0.425 mm From (4), tan αmax = (0.425 mm / 2)
/0.1mm Therefore, αmax = 64.8 °.
【0047】(9)より、sinαmin=0.15m
m/(0.15mm+0.1mm) 従って、αmin=36.9°となる。According to (9), sinαmin = 0.15 m
m / (0.15 mm + 0.1 mm) Therefore, αmin = 36.9 °.
【0048】よってαは、36.9°≦α≦64.8°
…(10)の範囲内に形成すればよい。Therefore, α is 36.9 ° ≦ α ≦ 64.8 °
.. May be formed in the range of (10).
【0049】上述の具体例の場合、よりtanα=
(0.3mm/2)/0.1mm したがって、α=56.3°となる。これは(10)を
満たしており、照射して出来る孔形状は、はんだボール
電極に接することができる。In the case of the above specific example, tan α =
(0.3 mm / 2) /0.1 mm Therefore, α = 56.3 °. This satisfies (10), and the shape of the hole formed by irradiation can be in contact with the solder ball electrode.
【0050】なお、上述の場合、Zを絶縁層の厚さと規
定したが、図9に示すように、多層プリント基板1a上
の表面電極8aの形状を、球形状のはんだボール電極7
aに接続する表面電極8aと下層の電極3aと接続する
ための導体層であるスルホールビア5aとで構成しても
よい。なお、図9では、図5と同一部分には同一符号に
aを付して個々の説明を省略している。In the above case, Z is defined as the thickness of the insulating layer. However, as shown in FIG. 9, the shape of the surface electrode 8a on the multilayer printed circuit board 1a is
a and a through-hole via 5a which is a conductor layer for connecting to the lower electrode 3a. In FIG. 9, the same parts as those in FIG.
【0051】その際、ZおよびLの値は、図10の中
で、距離Z´、および、距離L´として示される部分の
値を使用する。At this time, as the values of Z and L, the values of the parts shown as distance Z 'and distance L' in FIG. 10 are used.
【0052】図11(a)から(d)は、上述の多層プ
リント基板の最表層部の製造プロセスを示す模式図であ
る。なお、図7と同一部分には同一符号を付して個々の
説明を省略する。FIGS. 11A to 11D are schematic views showing a manufacturing process of the outermost layer portion of the above-mentioned multilayer printed circuit board. The same parts as those in FIG. 7 are denoted by the same reference numerals, and the description thereof will not be repeated.
【0053】この例の場合は、アディティブ法によって
いるので、図11(a)に示すように、図7で示した最
表層部の所定個所に円錐状の窪み加工が施されている多
層プリント基板1に、レジスト膜17(めっきレジス
ト)を形成する。In this example, since the additive method is used, a multi-layer printed circuit board in which a conical recess is formed at a predetermined portion of the outermost layer shown in FIG. 7 as shown in FIG. 1, a resist film 17 (plating resist) is formed.
【0054】次に、図11(b)に示すように、このレ
ジスト膜17を形成した多層プリント基板1に、無電解
銅めっきを施して、BGA2のはんだボール電極7と接
合するための表面電極8およびスルホールビア5を形成
する。Next, as shown in FIG. 11 (b), the multilayer printed circuit board 1 on which the resist film 17 is formed is subjected to electroless copper plating to form a surface electrode for bonding to the solder ball electrode 7 of the BGA 2. 8 and through-hole vias 5 are formed.
【0055】次に、図11(c)に示すように、溶剤に
より多層プリント基板1の表面からレジスト膜17を取
り除く。Next, as shown in FIG. 11C, the resist film 17 is removed from the surface of the multilayer printed board 1 with a solvent.
【0056】さらに、図11(d)に示すように、多層
プリント基板1にソルダレジスト6を形成する。Further, as shown in FIG. 11D, a solder resist 6 is formed on the multilayer printed circuit board 1.
【0057】これらの工程により、本発明の電極構成を
有する多層プリント基板を製造することができる。Through these steps, a multilayer printed circuit board having the electrode configuration of the present invention can be manufactured.
【0058】なお、上述のようなアディティブ法を用い
なくて、サブトラクティブ法を用いることもできる。The subtractive method can be used instead of the additive method as described above.
【0059】次に本発明の実装構造体の応用例について
説明する。Next, an application example of the mounting structure of the present invention will be described.
【0060】図12は、本発明の実装構造体の応用例の
側面断面図である。なお、図1と同一部分には同一符号
にcを付して個々の説明を省略する。FIG. 12 is a side sectional view of an application example of the mounting structure of the present invention. 1 are denoted by the same reference numerals as in FIG.
【0061】この場合は、多層プリント基板1cの表面
電極8cと、BGA2cのはんだボール電極7cとをは
んだの溶融による接続を用いず、固定具による加圧力で
接続して固定している。In this case, the surface electrode 8c of the multilayer printed circuit board 1c and the solder ball electrode 7c of the BGA 2c are connected and fixed by the pressing force of the fixing tool without using the connection by melting the solder.
【0062】多層プリント基板1c上の表面電極8c
に、BGA2cに形成した球形状のはんだボール電極7
cを位置合わせして搭載する。BGA2cの上にシリコ
ン樹脂の中に金属粒子を混入した厚さ約2mmの伝熱シ
ート19をおき、その上からマグネシウムを加工した固
定具20で抑え、多層プリント基板1cと固定治具20
とを固定ねじ18で締結して固定する。Surface electrode 8c on multilayer printed circuit board 1c
And a spherical solder ball electrode 7 formed on the BGA 2c.
c is aligned and mounted. A heat transfer sheet 19 having a thickness of about 2 mm in which metal particles are mixed in a silicone resin is placed on the BGA 2c, and the heat transfer sheet 19 is pressed from above with a fixing tool 20 made of magnesium.
Are fixed with the fixing screw 18.
【0063】これにより、BGA2cのはんだボール電
極7cと多層プリント基板1cの表面電極8cは密接状
態で押圧されて接続されて電気的な導通がえられる。ま
た、伝熱材料を介してヒートシンクと一体に固定してい
るので良好な放熱効果が得られる。Thus, the solder ball electrode 7c of the BGA 2c and the surface electrode 8c of the multilayer printed circuit board 1c are pressed and connected in close contact with each other, so that electrical continuity is obtained. In addition, since it is fixed integrally with the heat sink via the heat transfer material, a good heat radiation effect can be obtained.
【0064】さらに、固定手段が固定ねじ18による締
結であるので、固定ねじ18を緩めたり締めたりするこ
とにより、BGA2cの着脱が容易になり、必要に応じ
て不良品を交換することができる。Further, since the fixing means is fastening by the fixing screw 18, by loosening or tightening the fixing screw 18, the attachment / detachment of the BGA 2c becomes easy, and a defective product can be replaced as needed.
【0065】なお、固定具20の材料としてマグネシウ
ムを使用したが、アルミニウム合金等適宜に使用でき
る。また伝熱シート19として、シリコン樹脂に金属粒
子を混入させたものを使用したが、金属粉末や炭素等を
混入させた天然ゴムやエラストマ等も適宜に使用するこ
とができる。Although magnesium is used as the material of the fixture 20, an aluminum alloy or the like can be used as appropriate. Further, as the heat transfer sheet 19, a material in which metal particles are mixed in a silicon resin is used, but natural rubber or an elastomer in which metal powder, carbon, or the like is mixed may be used as appropriate.
【0066】[0066]
【発明の効果】本発明によれば、BGAを実装する多層
プリント基板に実装する際に、高い実装信頼性が得られ
る。According to the present invention, high mounting reliability can be obtained when mounting a BGA on a multilayer printed circuit board.
【0067】また、BGAの取り替えの簡易化を実現す
ることができる。Further, simplification of BGA replacement can be realized.
【図1】本発明の多層プリント基板にBGAを搭載しよ
うとした際の側面断面図。FIG. 1 is a side sectional view when a BGA is to be mounted on a multilayer printed board according to the present invention.
【図2】接合の際のはんだボール電極周辺の側面断面
図。FIG. 2 is a side cross-sectional view around a solder ball electrode during bonding.
【図3】図1の変形例を示す側面断面図。FIG. 3 is a side sectional view showing a modification of FIG. 1;
【図4】図3の接合の際のはんだボール電極周辺の側面
断面図。FIG. 4 is a side sectional view of the vicinity of a solder ball electrode at the time of joining in FIG. 3;
【図5】本発明の多層プリント基板にBGAを搭載した
実装構造体の側面断面図。FIG. 5 is a side sectional view of a mounting structure in which a BGA is mounted on a multilayer printed board according to the present invention.
【図6】接合後にはんだボール電極にかかる応力の説明
図。FIG. 6 is an explanatory diagram of stress applied to a solder ball electrode after joining.
【図7】多層プリント基板のスルホールビアの製造方法
の概要を示す模式図。FIG. 7 is a schematic view showing an outline of a method of manufacturing a through-hole via of a multilayer printed circuit board.
【図8】多層プリント基板の表面に形成する表面電極の
断面形状の範囲の説明図。FIG. 8 is an explanatory diagram of a range of a cross-sectional shape of a surface electrode formed on a surface of a multilayer printed circuit board.
【図9】本発明の多層プリント基板にBGAを搭載した
応用例の側面断面図。FIG. 9 is a side sectional view of an application example in which a BGA is mounted on a multilayer printed board according to the present invention.
【図10】図7の際の、表面電極の断面形状の範囲の説
明図。FIG. 10 is an explanatory diagram of the range of the cross-sectional shape of the surface electrode in FIG. 7;
【図11】(a)から(d)は、多層プリント基板の最
表層部の製造プロセスを示す模式図。FIGS. 11A to 11D are schematic diagrams showing a manufacturing process of an outermost layer portion of a multilayer printed circuit board.
【図12】本発明の実装構造体の応用例の側面断面図。FIG. 12 is a side sectional view of an application example of the mounting structure of the present invention.
【図13】従来の多層プリント基板にBGAを実装した
実装構造体の断面図。FIG. 13 is a cross-sectional view of a mounting structure in which a BGA is mounted on a conventional multilayer printed circuit board.
【図14】従来の球形状のはんだボール電極の一つの周
辺を拡大した拡大図。FIG. 14 is an enlarged view in which one periphery of a conventional spherical solder ball electrode is enlarged.
1…多層プリント基板、2…BGA、3…配線、4…絶
縁層、5…スルホールビア、7…はんだボール電極、8
…表面電極DESCRIPTION OF SYMBOLS 1 ... Multilayer printed circuit board, 2 ... BGA, 3 ... wiring, 4 ... Insulating layer, 5 ... Through-hole via, 7 ... Solder ball electrode, 8
… Surface electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 3/46 H05K 3/46 Z Fターム(参考) 5E319 AA03 AB05 AC02 AC11 BB04 CC33 CD57 5E336 AA04 BB15 BC25 BC34 CC34 CC42 EE03 GG01 5E338 AA16 BB04 BB19 BB25 CC01 CD01 CD05 EE01 5E346 AA15 AA43 BB01 BB16 FF45 HH07 HH21 5F044 KK02 KK13 KK17 KK19 LL01──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H05K 3/46 H05K 3/46 Z F-term (Reference) 5E319 AA03 AB05 AC02 AC11 BB04 CC33 CD57 5E336 AA04 BB15 BC25 BC34 CC34 CC42 EE03 GG01 5E338 AA16 BB04 BB19 BB25 CC01 CD01 CD05 EE01 5E346 AA15 AA43 BB01 BB16 FF45 HH07 HH21 5F044 KK02 KK13 KK17 KK19 LL01
Claims (5)
て電気的に接続されるよう配置された半導体素子とを有
する電気回路装置において、 前記バンプの表面と前記電極の表面とがなす交線を含む
仮想平面に対して前記電極の表面が斜交していることを
特徴とする電気回路装置。1. An electric circuit device comprising: a wiring board having electrodes; and a semiconductor element arranged to be electrically connected via bumps, wherein an intersection line formed between a surface of the bumps and a surface of the electrodes. The surface of the electrode is oblique to a virtual plane including:
て電気的に接続されるよう配置された半導体素子とを有
する電気回路装置において、 少なくとも前記電極の表面と前記バンプの表面とにより
形成される接合端部がなす境界線を含む仮想平面に対し
て前記電極の表面が斜交していることを特徴とする電気
回路装置。2. An electric circuit device having a wiring substrate having electrodes and a semiconductor element arranged to be electrically connected via bumps, wherein the electric circuit device is formed by at least a surface of the electrodes and a surface of the bumps. An electric circuit device, wherein the surface of the electrode is oblique to an imaginary plane including a boundary line formed by the joining ends.
形状の表面を有する電極であり、バンプは、前記凹形状
を覆うように配置されていることを特徴とする請求項1
または2に記載の電気回路装置。3. The electrode according to claim 1, wherein the electrode has a concave surface with respect to a main surface of the wiring board, and the bump is arranged to cover the concave shape.
Or the electric circuit device according to 2.
にバンプを配置し、前記バンプを加熱することにより前
記バンプと前記電極とを接合させ、前記バンプの表面と
前記電極の表面とがなす交線を含む仮想平面に対して前
記電極の表面が斜交するよう構成する工程を具備するこ
とを特徴とする電気回路装置の製造方法。4. A bump is arranged on an electrode provided on a surface of the wiring substrate, and the bump is heated and the bump is bonded to the electrode, so that the surface of the bump and the surface of the electrode are separated from each other. A method for manufacturing an electric circuit device, comprising a step of configuring a surface of the electrode so as to be oblique to a virtual plane including a line of intersection.
にバンプを具える電気部品を配置し、前記電気部品を前
記配線基板に対して押圧保持することにより前記バンプ
と前記電極との接合を保持させ、前記バンプの表面と前
記電極の表面とがなす交線を含む仮想平面に対して前記
電極の表面が斜交するよう構成する工程を具備すること
を特徴とする電気回路装置の製造方法。5. An electric component having a bump is disposed on an electrode provided on a surface of the wiring board, and the bump is connected to the electrode by pressing and holding the electric component against the wiring board. And manufacturing the electric circuit device, wherein the surface of the electrode is obliquely formed with respect to a virtual plane including a line of intersection between the surface of the bump and the surface of the electrode. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000224061A JP2002043368A (en) | 2000-07-25 | 2000-07-25 | Electric circuit device and manufacturing method therefor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000224061A JP2002043368A (en) | 2000-07-25 | 2000-07-25 | Electric circuit device and manufacturing method therefor |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2002043368A true JP2002043368A (en) | 2002-02-08 |
Family
ID=18718084
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000224061A Pending JP2002043368A (en) | 2000-07-25 | 2000-07-25 | Electric circuit device and manufacturing method therefor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2002043368A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112010005175T5 (en) | 2010-01-25 | 2012-10-31 | Murata Manufacturing Co., Ltd. | Electronic module and communication device |
-
2000
- 2000-07-25 JP JP2000224061A patent/JP2002043368A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112010005175T5 (en) | 2010-01-25 | 2012-10-31 | Murata Manufacturing Co., Ltd. | Electronic module and communication device |
US8797759B2 (en) | 2010-01-25 | 2014-08-05 | Murata Manufacturing Co., Ltd. | Electronic module and communication apparatus |
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