JP2002033722A - Decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that conventionally a decoder that requires a complicated circuit for a header analysis to detect a VBV delay parameter and results in increased circuitry scale, because VBV delay registers, counters and coincident detection sections whose number is equal to number of presentation time stamps(PTS) stored in a PTS register are required. SOLUTION: Reproduction start time information is stored with a write address, when coded data are transferred to a buffer; and when the stored write address is coincident with a read address in the case that the coded data are read from the buffer, a decoded frame is subjected to reproduction control, on the basis of the stored reproduction start time information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a decoding device,
In particular, the present invention relates to an apparatus for controlling reproduction synchronization by associating reproduction start time information with a frame obtained by decoding encoded data.

[0002]

2. Description of the Related Art There is the MPEG2 standard as a method for encoding video data, encoding audio data, and multiplexing video encoded data and audio encoded data. MPE
As shown in FIG. 2, a decoder for a system stream multiplexed according to the G2 standard includes a demultiplexer 20, a video buffer memory 13, a video decoder 15, and a display controller 1.
9, an audio buffer memory 23, an audio decoder 24, and a reproduction control unit 25.

[0003] When a system stream in which coded video data and coded audio data are multiplexed is input, a separating unit 20 separates the coded data into coded video data, coded audio data, and control information and outputs the separated data. The encoded video data is input to the video decoder 15 through the video buffer memory 13, and the encoded audio data is input to the audio decoder 24 through the audio buffer memory 23. The control information includes a reproduction start time (PTS: Presentation) of encoded data.
Time Stamp) is used for synchronizing the reproduction of the decoded video frame and audio frame.

However, the video buffer memory 13
Contains several frames of information, a time lag occurs between the PTS output from the separator 20 and the video frame output from the video decoder 15, and as a result, the video data Playback cannot be synchronized. In order to achieve reproduction synchronization, it is necessary to delay the PTS by a time equal to the buffer memory delay time of the encoded video data. In the MPEG video standard,
A parameter (VBVdelay) representing a buffer memory delay time of the video encoded data is defined,
Can be used for PTS delay.

As shown in FIG. 3, a first conventional example for controlling video playback synchronization is a header analysis unit 30, a VB
Vdelay register 31, write control unit 10, PT
S write control unit 11, counter unit 32, match detection unit 1
6, PTS register 17, PTS read control unit 18,
It comprises a video buffer memory 13, a read control unit 14, a video decoder 15, and a display control unit 19.

[0006] The encoded video data is supplied to a header analysis unit 3.
0, stored in the video buffer memory 13 through the write control unit 10. The header analysis unit 30 detects the VBV delay in the video encoded data and detects the VBV delay.
Output to register 31 and VBV delay register 31
Holds VBVdelay.

[0007] The PTS is held in the PTS register 17 through the PTS write control unit 11. The PTS write control unit 11 starts the counter 32 at the timing of writing the PTS to the PTS register 17.

The coincidence detector 16 compares the VBVdelay value output from the VBVdelay register 31 with the counter value output from the counter 32, and instructs the PTS read controller 18 to read the PTS when they match.

When the PTS read control unit 18 receives the PTS read command from the match detection unit 16, it reads the PTS from the PTS register 17 and outputs it to the display control unit 19.

The coded video data stored in the video buffer memory 13 passes through the read control unit 14 and is decoded by the video decoder 15 to become a frame image.

The display control unit 19 has an internal reference time (STC: System TimeClock) and PT
S is compared, and when they match, a decoded frame image is displayed.

By the above operation, the PTS can be delayed by the same time as the delay time of the video coded data by the video buffer memory. As a result, there is no time lag between the correspondence between the decoded frame image and the PTS. Become something.

A second conventional example for controlling reproduction synchronization is, as shown in FIG.
2, the PTS insertion unit 40, the write control unit 10, the video buffer memory 13, the read control unit 14, the video decoder 15, and the display control unit 19.

The header analysis unit 42 detects a specific position of encoded data constituting a predetermined video frame from the input encoded video data, and converts the position information together with the encoded video data into a PTS. Output to the insertion unit 40.

Here, as an example of the detection position, a head position of header information of encoded data forming a video frame is assumed. The PTS insertion unit 40 inserts a PTS into the input video encoded data at the position detected by the header analysis unit 42.

The video encoded data with the PTS inserted is stored in the video buffer memory 13 through the write control unit 10 and then read out by the read control unit 14. The header analysis unit 41 analyzes the video encoded data to which the PTS has been added according to the predetermined PTS insertion position information, extracts the PTS, and outputs the PTS to the display control unit 19.

The video decoder 15 includes a header analysis unit 41
And decodes the encoded video data output from to generate a frame image.

The display control unit 19 includes an internal STC and a PTS.
Are compared, and when they match, a decoded frame image is displayed.

By the above operation, the PTS is multiplexed with the coded video data and passed through the video buffer memory 13, so that the difference between the coded video data after passing through the buffer memory and the delay time of the PTS can be prevented.
As a result, there is no time lag between the decoded frame image and the PTS, and correct reproduction synchronization can be performed.

[0020]

In the first conventional example described above, VBVdela included in video encoded data is used.
Although a means for detecting the y value is required, since the video encoded data is composed of various header information and data obtained by performing variable length coding on the frame image, it is necessary to perform header analysis for detecting the VBV delay value. Requires a complicated circuit.

Further, since the video coded data stored in the video buffer memory 13 includes coding information for several frames, when reproducing a system stream to which PTS is added to all video frames, the PTS
Since a plurality of PTS values are held in the register 17 at the same time, the VBV delay register 31, the counter 32, and the coincidence detecting unit 16 are required by the number of PTSs held in the PTS register 17, resulting in an increase in circuit scale. .

Further, when the video encoded data has a variable bit rate, VBV delay is set to FFFF different from the delay time of the video buffer memory.
The delay cannot be used for the delay time of the PTS.

In the second conventional example, the PTS
Although there is no limit on the number of headers, a header analysis for detecting the position where the PTS is inserted in the previous stage of the video buffer memory,
The header analysis for extracting the PTS from the video coded data into which the PTS has been inserted at the subsequent stage of the video buffer memory requires a complicated circuit as in the first conventional header analysis.

[0024]

In order to overcome the above-mentioned problems, the present invention is obtained by separating reproduction time information from encoded data in which reproduction time information is embedded, and decoding the encoded data. A decoding device that controls the reproduction timing of the decoded frame based on the reproduction time information, a unit that holds separated reproduction time information, a memory that temporarily stores encoded data, and the encoded data that corresponds to the reproduction time information. Means for holding a write address when writing to the memory; and means for comparing the read address when reading the encoded data from the memory with the held write address, wherein the read address and the held write A match with the address is detected, and the above information is stored in the decoded frame when the address matches. By associating the raw time information, the reproduction time information associated with the encoded data, and converting the response to the decoded frame.

Here, when a plurality of means for holding the reproduction time information and a plurality of means for holding the write address to the memory are provided, the encoded data for a plurality of frames is stored in the memory. However, the reproduction time information is converted.

When the number of pieces of reproduction time information to be held simultaneously exceeds a predetermined number, the following reproduction time information is not held.

[0027]

FIG. 1 is a block diagram showing a first embodiment of the present invention.
A write control unit 11, a write address register 12,
Video buffer memory 13, read control unit 14, video decoder 15, match detection unit 16, PTS register 1
7, a PTS read control unit 18 and a display control unit 19.

The write control unit 10 transfers the encoded video data when the video buffer memory 13 has an empty area, and counts up the value of the write address. Further, it outputs the value of the write address to the video buffer memory 13 to the write address register 12.

When the PTS separated from the system stream is input, the PTS write control unit 11
Is written to the PTS register 17 and the input of the PTS is notified to the write address register 12.

The write address register 12 has a PTS
When notified that the PTS has been input from the write control unit 11, the value of the write address input from the write control unit 10 is held in an internal register.

The read control unit 14 reads data when video encoded data is stored in the video buffer memory 13 and transfers the data to the video decoder 15. Further, it outputs the value of the read address of the video buffer memory 13 managed internally to the coincidence detecting unit 16.

The coincidence detector 16 compares the value of the write address input from the write address register 12 with the value of the read address input from the read controller 14.

When the values match, PT
The PTS register 17 sends the PTS
Is read.

When receiving the PTS read command from the coincidence detector 16, the PTS read controller 18 reads the PTS from the PTS register 17 and transfers it to the display controller 19.

The video decoder 15 includes a header control unit 14
And decodes the encoded video data output from to generate a frame image.

The display control unit 19 has an internal STC and PTS
Are compared, and when they match, a decoded frame image is displayed.

By the above operation, the write address of the video buffer memory when the PTS is separated from the system stream is held, and the match between the held write address and the read address of the video buffer memory is detected. It is possible to know the delay time when the encoded data passes through the video buffer memory.

As a result, it is possible to prevent time lag between the PTS and the frame image included in the encoded video data, and correct reproduction synchronization is performed.

FIG. 5 is a block diagram showing a second embodiment of the present invention. The write control unit 10, the PTS write control unit 11, the write address register 50, the video buffer memory 13, the read control unit 14, the video decoder 15, match detector 16, PTS register 51, PTS
It comprises a read control unit 18 and a display control unit 19.

The configuration of FIG. 5 is different from the first embodiment in that the number of addresses held in the write address register 50 and the number of PTSs held in the PTS register 51 are limited.

Here, the write address register 50 and the PTS register 51 shown in FIG. 5 can hold three values, but this is only an example, and the present invention is not limited to three.

In this configuration, the operation when the number of PTSs held in the PTS register 51 is less than three is the same as that of the first invention, but the number of PTSs held in the PTS register 51 reaches the limit value of three. If a new PTS is acquired at this time, the PTS write control unit 11 discards the new PTS value and does not update the values held in the PTS register 51 and the write address register 50.

As a result, all the input PTSs cannot be used for controlling the reproduction synchronization, but the numbers of the PTS registers 51 and the write address registers 50 can be freely set.

In the above, the case where the present invention is applied to MPEG video encoded data has been described. However, the present invention can be generally used for data whose reproduction time is controlled, such as audio encoded data.

According to the above-described embodiment, the present invention holds the reproduction synchronization information of a video when the reproduction synchronization information of the video is obtained in the reproduction of the encoded video data. The write address stored in the video buffer memory is held, and a read address when reading video encoded data from the video buffer memory is compared with the held write address. By extracting the synchronization information and using it for controlling the display timing of the video frame after decoding the video encoded data, the decoded frame of the video encoded data can be associated with the PTS with a simple circuit.

The present invention does not require a means for analyzing video encoded data, as compared with the first conventional example and the second conventional example. In order to analyze video coded data that has been subjected to variable-length coding according to the MPEG2 standard, a complicated circuit is required. Therefore, by using the present invention, a large number of circuits can be reduced.

In comparison with the first conventional example, VBVde
Because there is no need for a counter to delay by lay,
Circuits for forming the counter can be reduced.

According to the present invention, a plurality of write address registers and PTS registers are required depending on the number of PTSs simultaneously held as compared with the second conventional example, but the number of circuits is slightly increased.

As described above, by using the configuration of the present invention, it is possible to reduce the number of circuits as compared with the conventional method.

[0050]

As described above, according to the present invention, the reproduction time information is associated with the decoded frame by a simple circuit configuration such as a register holding the reproduction start time information and the write address, a register control unit, and a comparator. This eliminates the need for a complicated circuit such as a counter used in the conventional example and a header analysis of encoded data.

Further, according to the present invention, by preparing a plurality of registers for holding reproduction time information and a plurality of registers for holding write addresses, a plurality of reproduction start time information are simultaneously held and converted to correspond to a plurality of decoded frames. be able to.

Further, according to the present invention, a limit is set on the number of pieces of reproduction time information to be held at the same time, and when a piece of reproduction time information exceeding the set number is obtained, it is not stored. The number of registers holding the write address can be freely set.

Thus, the decoding device of the present invention can reduce the number of circuits as compared with the conventional device.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a configuration diagram of a general decoder.

FIG. 3 is a configuration diagram of a conventional reproduction synchronization control.

FIG. 4 is a configuration diagram of a conventional reproduction synchronization control.

FIG. 5 is a configuration diagram showing another embodiment of the present invention.

[Explanation of symbols]

 10 Write Control 11 PTS Write Control 12, 50 Write Address Register 13 Video Buffer Memory 14 Read Control 15 Video Decoder 16 Match Detection 17, 51 PTS Register 18 PTS Read Control 19 Display Control 20 Separator 23 Audio Buffer Memory 24 Audio Decoder 25 Playback Control 30, 41, 42 Header analysis 31 VBV delay register 32 Counter 40 PTS insertion

Continuation of the front page (72) Inventor Hitoshi Ishihara 22-22 Nagaikecho, Abeno-ku, Osaka City, Osaka F-term (reference) 5C059 KK32 MA00 ME01 RC04 UA05 UA34 UA35 UA36 5K047 AA16 AA18 DD02 HH54

Claims (3)

[Claims] 1. A decoding device for separating reproduction time information from encoded data in which reproduction time information is embedded and controlling the reproduction timing of a decoded frame obtained by decoding the encoded data by the reproduction time information. Means for holding separated playback time information; memory for temporarily storing encoded data; means for holding a write address when writing encoded data corresponding to playback time information to the memory; and code from the memory. Means for comparing a read address when reading encrypted data with the held write address, and detects a match between the read address in the memory and the held write address, and decodes the frame when the addresses match. By associating the held playback time information with the encoded data, Decoding apparatus characterized by converting the reproduction time information associated with the response to the decoded frame with. 2. A plurality of means for holding the reproduction time information and a plurality of means for holding a write address to the memory, so that even when encoded data for a plurality of frames is stored in the memory. 2. The decoding device according to claim 1, wherein conversion of the reproduction time information is performed. 3. The decoding apparatus according to claim 2, wherein when the number of pieces of reproduction time information held simultaneously exceeds a predetermined number, the subsequent reproduction time information is not stored.