JP2002033655A - Frequency divider - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency divider that can selectively output a fundamental wave without increasing number of signal lines for frequency divider control. SOLUTION: The frequency divider is provided with a frequency divider integrated circuit 1 that frequency-divides an input signal with a frequency division ratio on the basis of a combination of received control signals and provides an output, an AND gate 5 that provides an output of an H level when receiving control signals only with a combination among combinations of control signals to allow the frequency divider integrated circuit 1 to provide an output of the same frequency division ratio, and an inverter 6 that receives the output of the AND gate 5. The output of the AND gate on the basis of the control signals with one combination allows the frequency divider integrated circuit 1 to provide an output of its input signal in place of the frequency division output of the frequency divider integrated circuit 1 and the output from the inverter 6 on the basis of the control signals with one combination shuts off the input signal given to the frequency divider integrated circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency divider which can be used for a local oscillator of a radio communication device, and more particularly, selectively receives an input signal (also referred to as a fundamental wave in this specification) as it is. It relates to a frequency divider that can output.

[0002]

2. Description of the Related Art As shown in FIG. 5, for example, a conventional frequency divider has a terminal SW1 connected to a frequency divider integrated circuit 1 constituting a frequency divider.
And a terminal SW2, and a terminal SW1 and a terminal SW2
Based on the H level and L level of the control signal applied to
As shown in FIG. 6, there is a type in which the frequency division ratio can be switched to 、, ４, １ ／. One of such frequency divider integrated circuits 1 is, for example, an MC12 manufactured by Motorola.
093. In FIG. 5, a terminal SB is a terminal for a standby mode, a terminal IN is an input terminal, and a terminal Vc
c is a power supply terminal, terminal GND is a ground terminal, terminal OU
T indicates an output terminal, and symbols C1 and C2 are coupling capacitors.

By using such a frequency divider as a part of a frequency synthesizer constituting a local oscillator or the like of a wireless communication device, it is possible to narrow the oscillation frequency range of a voltage controlled oscillator constituting a part of the frequency synthesizer. Will be possible.

However, the frequency divider integrated circuit 1 receives the input signal, that is, the fundamental wave as it is (frequency division ratio 1 /
In the case where a frequency divider that does not have the function of outputting in 1) and also wants to selectively output a fundamental wave is configured, as shown in FIG. A changeover switch circuit 3 for selectively inputting the oscillation output of the control oscillator 2 to the frequency divider integrated circuit 1 and the oscillation output of the voltage control oscillator 2 selectively in place of the frequency division output of the frequency divider integrated circuit 1 A switching switch circuit 4 for output is provided, and terminals SW1 and SW of the frequency divider integrated circuit 1 are provided.
2 and a control signal 1 and a control signal 2, respectively.
The control signal 3 is supplied to the changeover switch circuit 3 by the inverter 6.
To switch the changeover switch circuit 3,
The control signal 3 is directly supplied to the changeover switch circuit 4 to switch the changeover switch circuit 4.

With this configuration, as shown in FIG. 8, based on a combination of the H level and the L level of the control signals 1 and 2 when the control signal is at the L level,
In addition to the output signals having the division ratios of 1/2, 1/4, and 1/8, the output signal having the division ratio of 1/1 when the control signal 3 is at the H level regardless of the levels of the control signals 1 and 2, ie, A fundamental wave is transmitted. In FIG. 8, x indicates that the signal may be at either the H or L level.

[0006]

However, in the conventional frequency divider as described above, since there is no control for outputting the fundamental wave in the control of the frequency divider integrated circuit, a changeover switch for selectively passing the fundamental wave is provided. There is a problem that a circuit is provided and a control signal for switching control of the changeover switch circuit is required.

For this reason, there is a problem that the number of signal lines for control increases.

An object of the present invention is to provide a frequency divider that can selectively output a fundamental wave without increasing the number of signal lines for frequency divider control.

[0009]

A frequency divider according to the present invention is a frequency divider integrated circuit that frequency-divides an input signal at a frequency division ratio based on a combination of input control signals and outputs the frequency-divided signal. First switching means for selectively cutting off an input signal supplied to the frequency divider integrated circuit; second switching means for selectively transmitting the input signal instead of the output of the frequency divider integrated circuit; The first switching means is controlled to be in the cut-off state based on only one of a plurality of control signals of the control signals for causing the frequency divider integrated circuit to output the same frequency division ratio, and the second switching is performed. And control means for controlling the means to a conductive state.

According to the frequency divider of the present invention, only one of a plurality of combinations of control signals for causing the frequency divider integrated circuit to output the same frequency division ratio is supplied to the control means. In this case, the first switching means is controlled to the cutoff state, the supply of the input signal to the frequency divider integrated circuit is cut off, and the second switching means is controlled to the conductive state, and the frequency division of the frequency divider integrated circuit is performed. Since the input signal is output as it is in place of the output, the input signal having a division ratio of 1/1 can be transmitted as it is without increasing the number of control signals for frequency division. Further, when a control signal of a combination other than the control signal of the one combination is supplied to the frequency divider integrated circuit, the input signal divided by the frequency division ratio based on the combination of the supplied control signals is It is output as the output signal of the frequency divider.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A frequency divider according to the present invention will be described below with reference to an embodiment.

FIG. 1 is a block diagram showing a configuration of a frequency divider 10 according to an embodiment of the present invention. In FIG. 1, the same components as those shown in FIGS. Reference numerals are used, and description of each terminal of the frequency divider integrated circuit 1 is omitted.

A frequency divider 10 according to an embodiment of the present invention
Is a switch circuit 3 for selectively inputting the oscillation output of the voltage-controlled oscillator 2 which is an input signal generation source to the frequency-divider integrated circuit 1 outside the frequency-divider integrated circuit 1 and the voltage-controlled oscillator 2 A changeover switch circuit 4 for selectively outputting an oscillation output instead of the frequency division output of the frequency divider integrated circuit 1, an AND gate 5 for inputting a signal obtained by inverting the control signal 1 and the control signal 2, and an AND gate 5 and an inverter 6 for inverting the output of the frequency-divider integrated circuit 1.
Control signal 1 and control signal 2 are respectively connected to W1 and terminal SW2.
And the output of the AND gate 5 is supplied to the changeover switch circuit 3 via the inverter 6 to switch the changeover switch circuit 3, and the changeover switch circuit 4
, The output of the AND gate 5 is directly supplied to switch the changeover switch circuit 4.

Here, the changeover switch circuit 3 corresponds to the first changeover means, and the changeover switch circuit 4 corresponds to the second changeover means.
, And the AND gate 5 and the inverter 6 correspond to the control means.

In the frequency divider 10 configured as described above, when both the control signal 1 and the control signal 2 are at L level, the output of the AND gate 5 is at L level, and the changeover switch circuit 4 is turned off. The oscillating output of the voltage controlled oscillator 2 is cut off and not output from the frequency divider 10 by the switched switch circuit 4 which is controlled and controlled to the OFF state, the output of the inverter 6 is at the H level, and The oscillation output of the voltage-controlled oscillator 2 is supplied to the frequency divider integrated circuit 1 via the changeover switch circuit 3 controlled to the ON state and controlled to the ON state, and the frequency divided output of the frequency divider integrated circuit 1 is divided. It is sent out as the output of the divider 10. On the other hand, since the control signals 1 and 2 at L level are supplied to the terminals SW1 and SW2 of the frequency divider integrated circuit 1, the frequency division ratio of the frequency divider 10 is 1/1, as shown in FIG.
It becomes 8.

When control signal 1 is at H level and control signal 2 is at L level, the output of AND gate 5 is at H level, the output of inverter 6 is at L level,
The changeover switch circuit 3 is controlled to the off state, the oscillation output of the voltage controlled oscillator 2 is cut off by the changeover switch circuit 3 controlled to the off state and is not supplied to the frequency divider integrated circuit 1, and the changeover switch circuit 4 The switch circuit 4 controlled to the ON state and controlled to the ON state
The oscillation output of the voltage-controlled oscillator 2 is sent out as it is as the output of the frequency divider 10 via. That is, the frequency division ratio of the frequency divider 10 is 1/1 as shown in FIG.

When the control signal 1 is at the L level and the control signal 2 is at the H level, the output of the AND gate 5 is at the L level, and the changeover switch circuit 4 is controlled to the off state and controlled to the off state. Changeover switch circuit 4
As a result, the oscillation output of the voltage controlled oscillator is cut off and is not output from the frequency divider 10, the output of the inverter 6 is at the H level, the changeover switch circuit 3 is controlled to the ON state, and the changeover switch controlled to the ON state The oscillation output of the voltage controlled oscillator 2 is supplied to the frequency divider integrated circuit 1 via the circuit 3 and the frequency division output of the frequency divider integrated circuit 1 is divided by the frequency divider 10.
Is sent out. On the other hand, an L level control signal 1 is supplied to a terminal SW1 of the frequency divider integrated circuit 1, and an H level control signal 2 is supplied to a terminal SW2 of the frequency divider integrated circuit 1.
Is supplied, the frequency division ratio of the frequency divider 10 becomes 1/4 as shown in FIG.

When both the control signal 1 and the control signal 2 are at the H level, the output of the AND gate 5 is at the L level, the changeover switch circuit 4 is controlled to the off state, and the changeover switch circuit controlled to the off state. 4, the oscillation output of the voltage controlled oscillator is cut off and is not output from the frequency divider 10, the output of the inverter 6 is at the H level, the switch circuit 3 is controlled to the ON state, and the switching controlled to the ON state is performed. The oscillation output of the voltage controlled oscillator 2 is supplied to the frequency divider integrated circuit 1 via the switch circuit 3,
The divided output of the divider integrated circuit 1 is sent out as the output of the divider 10. On the other hand, since an H level control signal is supplied to the terminals SW1 and SW2 of the frequency divider integrated circuit 1, the frequency division ratio of the output of the frequency divider 10 is 1 as shown in FIG.
/ 2.

As described above, according to the frequency divider 10, the changeover switch circuit 3 for selectively cutting off the input signal supplied to the frequency divider integrated circuit 1, and the input signal of the frequency divider integrated circuit 1 A selector switch circuit 4 for selectively transmitting an output instead of an output, wherein the frequency divider integrated circuit 1 uses two combinations of control signals for transmitting an output having the same frequency division ratio, and The changeover switch circuits 3 and 4 are controlled by the control signal of one of
The input signal is replaced with the frequency divider 1 instead of the frequency divider integrated circuit 1 output.
Since the output is 0, the divided output by the frequency divider integrated circuit 1 and the input signal bypassing the frequency divider integrated circuit 1 can be selectively transmitted without increasing the number of control signals.

Next, another embodiment of the frequency divider according to the present invention will be described.

FIG. 3 is a block diagram showing a configuration of a frequency divider 20 according to another embodiment of the present invention.

The frequency divider 20 is connected to the terminal S of the frequency divider integrated circuit 1.
Control signal 1 and control signal 2 for W1 and terminal SW2 respectively
To selectively output the frequency-divided output from the terminal OUT of the frequency divider integrated circuit 1 as the frequency-divided output of the frequency divider 20 via the coupling capacitor C4.

On the other hand, a resistor R5 and a diode D5 are connected to the base of the transistor Q2 whose power supply voltage is supplied to the emitter.
1, a control signal 1 is applied through a series circuit of the first and second transistors, and a diode D1 is turned on and off based on the control signal 1. A transistor Q2 is turned on and off based on the on / off of the diode D1.
On / off control.

Further, the base of the transistor Q2 is grounded through a series circuit of the resistor R5 and the transistor Q1, a control signal 2 is applied to the base of the transistor Q1, and the transistor Q1 is turned on / off based on the control signal 2. Under the control, the transistor Q2 is turned on / off based on the turning on / off of the transistor Q1.

The collector of the transistor Q2 is connected to the terminals Vcc and SB of the frequency divider integrated circuit 1 to apply the power supply voltage Vcc to the terminals Vcc and SB of the frequency divider integrated circuit 1 via the transistor Q2. , Power supply voltage Vc output through the collector of transistor Q2
c to the input terminal IN of the frequency divider integrated circuit 1 via the resistor R1.
And the anode of the diode D2. Resistance R1
Of the power supply voltage Vcc through the diode D2
Is turned on, and an input signal supplied via the coupling capacitor C1 and the diode D2 is applied to the terminal IN of the frequency divider 20.

On the other hand, the power supply voltage Vcc is divided by the resistors R3 and R4, and the cathode of the diode D2 is connected to the resistor R2.
And a resistor R1 through a diode D2.
The power supply voltage Vcc is divided by the resistor R2 and the resistor R2.
The voltage divided by the resistor 3 and the resistor R4 is supplied to the anode of the diode D3, the voltage divided by the resistor R1 and the resistor R2 is applied to the cathode of the diode D3, and based on the voltage divided by the resistors R1 and R2. The on / off control of the diode D3 allows the input signal supplied via the coupling capacitor C1 to be selectively transmitted as the output of the frequency divider 20 via the diode D3 and the coupling capacitor C3.

Here, when the transistor Q2 is on, the voltage divided by the resistors R1 and R2 is equal to the resistance of the resistor R3.
On the contrary, when the transistor Q2 is off, the divided voltage by the resistors R1 and R2 is lower than the divided voltage by the resistors R3 and R4. , Resistors R1, R2, R3, R
The resistance value of 4 is selected.

Here, the diode D2 corresponds to the first switching means, the diode D3 corresponds to the second switching means, and the transistors Q1 and Q2 and the diode D
1. The resistors R1 to R4 substantially correspond to the control means.

In the frequency divider 20 configured as described above, when the control signal 1 and the control signal 2 are both at the L level, the transistor Q1 is controlled to be off and the diode D1 is controlled to be on. The transistor Q2 is turned on, and the power supply voltage Vcc is applied to the terminal SB, the terminal Vcc, and the resistor R1 of the frequency divider integrated circuit 1. Therefore, the diode D2 is controlled to be turned on, and the diode D2 is controlled by the divided voltage by the resistors R1 and R2.
3, the input of the frequency divider 20 is supplied to the terminal IN of the frequency divider integrated circuit 1 via the diode D2 to divide the frequency, and the frequency division output of the frequency divider integrated circuit 1 is divided. Periodic device 2
It is transmitted as a divided output of 0. In this case, since the control signal 1 and the control signal 2 are both at the L level, the frequency division ratio of the output is 1/8 as shown in FIG.

When control signal 1 is at H level and control signal 2 is at L level, both diode D1 and transistor Q1 are controlled to be off, transistor Q2 is turned off, and power supply voltage Vcc is reduced. It is not applied to the terminal SB, the terminal Vcc and the resistor R1 of the peripheral integrated circuit 1. Therefore, the diode D2 is controlled to the off state, and the diode D3 is controlled to the on state by the divided voltage by the resistors R3 and R4, and the input of the frequency divider 20 is divided by the diode D3 and the coupling capacitor C3. It is sent as it is as the output of the device 20. That is, in this case, the output of the frequency divider 20 becomes 1 as shown in FIG.
/ 1.

When control signal 1 is at L level and control signal 2 is at H level, diode D1 is controlled to be on, transistor Q1 is also controlled to be on, and transistor Q2 is turned on. Power supply voltage Vc
c is applied to the terminal SB, the terminal Vcc, and the resistor R1 of the frequency divider integrated circuit 1. Therefore, the diode D2 is controlled to be turned on, and the diode D3 is controlled to be turned off by the divided voltage by the resistors R1 and R2.
The input of the frequency divider 20 is supplied to the terminal IN of the frequency divider integrated circuit 1 via the diode D2 to divide the frequency, and the frequency divided output of the frequency divider integrated circuit 1 is transmitted as the frequency divided output of the frequency divider 20. Is done. In this case, since the control signal 1 is at the L level and the control signal 2 is at the H level, the frequency division ratio of the output is 1/4 as shown in FIG.

When control signal 1 and control signal 2 are both at H level, diode D1 is controlled to be off, but transistor Q1 is controlled to be on, transistor Q2 is turned on and power supply voltage Vcc Is applied to the terminal SB, the terminal Vcc, and the resistor R1 of the frequency divider integrated circuit 1. Accordingly, the diode D2 is controlled to be turned on, and the diode D3 is controlled to be turned off by the voltage divided by the resistors R1 and R2, so that the frequency divider 20
Is supplied to the terminal IN of the frequency divider integrated circuit 1 via the diode D2 to be frequency-divided, and the frequency-divided output of the frequency-divider integrated circuit 1 is sent out as the frequency-divided output of the frequency divider 20. In this case, since the control signal 1 and the control signal 2 are both at the H level, the frequency division ratio of the output becomes 1/2 as shown in FIG.

As described above, according to the frequency divider 20,
A diode D2 for selectively blocking an input signal supplied to the frequency divider integrated circuit 1;
And a diode D3 for selectively transmitting the output of the frequency divider. The frequency divider integrated circuit 1 uses two combinations of the control signals for transmitting the output of the same frequency division ratio. The diodes D2 and D3 are controlled by the control signal of one of the combinations, and the input signal is output from the frequency divider 20 instead of the output from the frequency divider integrated circuit 1, so that the selection signal can be selected without increasing the number of control signals. Specifically, it is possible to transmit the frequency divided output by the frequency divider integrated circuit 1 and the input signal obtained by bypassing the frequency divider integrated circuit 1.

[0034]

As described above, according to the frequency divider of the present invention, it is possible to selectively output the fundamental wave without increasing the number of signal lines for controlling the frequency divider. The effect is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a frequency divider according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining an operation of the frequency divider shown in FIG. 1;

FIG. 3 is a block diagram showing a configuration of a frequency divider according to another embodiment of the present invention.

FIG. 4 is an explanatory diagram for explaining the operation of the frequency divider shown in FIG. 3;

FIG. 5 is a block diagram for explaining a frequency divider integrated circuit;

FIG. 6 is an explanatory diagram for explaining an operation of the frequency divider integrated circuit shown in FIG. 5;

FIG. 7 is a block diagram showing a configuration of a conventional frequency divider.

FIG. 8 is an explanatory diagram for explaining an operation of the frequency divider integrated circuit shown in FIG. 7;

[Explanation of symbols]

 1 Divider integrated circuit 3 and 4 Switching switch circuit 5 AND gate 6 Inverter 10 and 20 Divider D1 to D3 Diode Q1 and Q2 Transistor

Claims (3)

[Claims] A frequency divider integrated circuit that divides an input signal by a frequency division ratio based on a combination of input control signals and outputs the divided signal, and selectively inputs an input signal supplied to the frequency divider integrated circuit. First switching means for interrupting, second switching means for selectively transmitting the input signal instead of the output of the frequency divider integrated circuit, and the frequency divider integrated circuit outputs an output having the same frequency division ratio. Control means for controlling the first switching means to be in the cut-off state and controlling the second switching means to be in the conducting state based only on the control signal of one of a plurality of combinations of the control signals to be transmitted. A frequency divider characterized by the above-mentioned. 2. The frequency divider according to claim 1, wherein the control means receives an input of one of the control signals and controls the second switching means to be conductive by an output, and an AND gate of the AND gate. A frequency divider, comprising: an inverter having an output as an input and controlling the first switching means to be in an interrupted state by the output. 3. The frequency divider according to claim 1, wherein the first switching means is a first diode, the second switching means is a second diode, and the control means receives a control signal of one combination. A frequency divider characterized by a control means for controlling the first diode to be in an off state and the second diode to be in an on state when being performed.