JP2002033458A - Semiconductor device and its fabricating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, and its fabricating method, in which high integration is realized by aligning microelements on the surface and rear of a basic body with high accuracy. SOLUTION: The semiconductor device 10 has an epitaxial layer formed on a reinforcing substrate 108. Alignment marks 11, 12 are put on the epitaxial layer 104 and used as alignment marks 11A, 12A when the first element of an element forming layer 105 is formed on the first face 104A, and as alignment marks 11B, 12B when the second element of an element forming layer 111 is formed on the second face 104B. The first and second elements are connected electrically through through holes 113X, 113Y made in the epitaxial layer 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having elements formed on a front surface and a back surface of a substrate on which the elements are formed, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, there has been proposed a semiconductor device in which elements are formed on both a front surface and a back surface of a semiconductor substrate as a base on which elements are formed, such as a micromachine such as an acceleration sensor. In forming elements on both the front and back surfaces of the semiconductor substrate, first, an element (first element) is formed on one surface (first surface), and then the other surface (second surface) is formed.
Another element (second element) is formed on the surface).

In this case, the first element on the first surface and the second element on the second surface are electrically connected to each other, so that the first element has a predetermined positional relationship with the semiconductor substrate interposed therebetween. The element and the second element are aligned with respect to each other. The front surface (first surface) and the back surface (second surface) of the semiconductor substrate
In aligning the first element and the second element formed on each surface (surface) with each other, an alignment mark is first formed on one surface (first surface) of the semiconductor substrate. A first element is formed on the first surface by the alignment described above, and then, while detecting the same alignment mark from the second surface side, a second element is formed on the second surface by the alignment based on this. An element was formed.

When elements are formed on the front surface (first surface) and the back surface (second surface) of a semiconductor substrate by performing alignment based on the alignment marks formed on the first surface as described above, usually, a "double-side aligner" is used. Is used. Using this "double-sided aligner", the second
As a method of detecting the alignment mark formed on the first surface side from the second surface side in alignment when forming the second element on the surface, first, an infrared ray transmitting device is used to detect the alignment mark formed on the first surface side.
A method of irradiating the alignment mark with infrared light from the surface side and detecting the image of the alignment mark by infrared light transmitted through the semiconductor substrate; secondly, the alignment mark formed on the first surface side through the semiconductor substrate from the second surface side Thirdly, there has been proposed a method of optically detecting an image of an alignment mark with a microscope or the like, and thirdly, a method of irradiating a laser beam from the back surface (second surface) side and detecting an image of the alignment mark with reflected light. . In the second and third methods, the obtained images are drawn on a new layer and superimposed sequentially each time the manufacturing process proceeds, and the alignment marks on the front surface (first surface) are aligned with the back surface (first surface). 2)
It is transferred to the side to maintain the accuracy of positioning.

[0005]

In the field of semiconductor manufacturing in recent years, not only micro machines such as acceleration sensors, but also semiconductor devices including fine elements such as memories and image pickup devices (CCDs) have been highly integrated. In order to realize the above, attempts have been made to form elements on both the front surface (first surface) and the back surface (second surface) of the semiconductor substrate.

In this case, as the element becomes finer, the element (first element) formed on the front surface (first surface) and the element (second element) formed on the back surface (second surface) become smaller. The alignment accuracy must be improved. For example, as shown in FIG. 14A, if the process design standard (design rule) of the element 2 on the front surface (first surface) 1A side and the element 3 on the back surface (second surface) 1B side of the semiconductor substrate 1 is large. (For example, in the figure, W
1 has a width of 2 to 3 μm), and even in the alignment using the “double-sided aligner” described above, the element 2 and the element 3 are in a predetermined positional relationship (for example, a positional relationship in which the elements 2 and 3 can be electrically connected to each other via the through hole 4) FIG. 14
As shown in (b), the surface (first surface) 1 of the semiconductor substrate 1
When the process design standard for the element 5 on the A side and the element 6 on the back surface (second surface) 1B becomes smaller (in FIG.
m or less), in the alignment using the conventional “double-sided aligner”, the alignment error is large, and the elements 5 and 6
And it is difficult to associate them with each other to have a predetermined positional relationship. This is because the “double-sided aligner” does not originally assume the production of a device (process design standard: 1.0 μm or less) with miniaturization in recent years.

For this reason, instead of the “double-sided aligner”,
Using a “stepper” suitable for forming a fine element, it is necessary to form an element on each of the front surface (first surface) and the back surface (second surface) of the semiconductor substrate.

However, if the position of the element on the front surface (first surface) and the element on the rear surface (second surface) are to be related to each other and aligned by using this “stepper”, the miniaturization of the element is required. Alignment marks that become smaller accordingly must be accurately detected from both the front surface (first surface) and the back surface (second surface). However, as in the case of the "double-sided aligner", the alignment mark formed on the first surface of the semiconductor substrate is changed to the back surface (second surface) by visible light and laser light.
Even if an attempt is made to detect the alignment mark, the reflected light of the laser light is scattered, and the diffracted light does not indicate the exact alignment mark position.

Similarly, when an infrared ray is radiated from the front surface (first surface) using an infrared transmission device and the alignment mark is detected from the rear surface (second surface) side by the infrared light transmitted through the semiconductor substrate, the alignment mark is placed on the alignment mark. Metal film for shading,
If there is a film that does not transmit infrared rays such as aluminum for wiring,
The alignment mark itself cannot be detected. As described above, since the alignment mark formed on the front surface (first surface) cannot be accurately detected from the rear surface (second surface) side by any of the methods, when forming the element on the rear surface (second surface), It has been difficult to accurately perform positioning related to the element on the front surface (first surface) side.

The present invention has been made in view of the above circumstances, and forms fine elements on the front and back surfaces of a substrate on which elements are formed by associating them with high-precision alignment, thereby achieving high integration. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor device having an epitaxial layer formed on a substrate, wherein the epitaxial layer is provided on a first surface side of the substrate on the substrate side. The first element is obtained by forming a second element on a second surface side of the epitaxial layer opposite to the substrate. This epitaxial layer
It is grown on a temporary substrate to be removed later. At this time, the impurity type (p
Type and n-type) and by varying the impurity concentration,
The temporary substrate can be easily removed selectively by wet etching or the like, and the epitaxial layer can be formed extremely thin to provide a single crystal silicon thin film layer. In this extremely thin single crystal silicon thin film layer, it is possible to observe the alignment marks formed on one surface on both surfaces.

According to a second aspect of the present invention, in the semiconductor device, the first element and the second element are electrically connected via a through hole formed in the epitaxial layer. In this case, since the thickness of the epitaxial layer is generally smaller than that of the semiconductor substrate on which the element is formed, the aspect ratio of the through hole can be reduced. Claim 3
The semiconductor device of the above, at a predetermined position of the epitaxial layer,
An alignment mark having a concave shape on the first surface side and a convex shape on the second surface side, or an alignment mark having a convex shape on the first surface side and a concave shape on the second surface side is formed. . Thereby, on both surfaces of the epitaxial layer, using a “stepper” instead of the “double-sided aligner” conventionally used, an alignment mark that is concave on the first surface side and convex on the second surface side, Alternatively, the first element and the second element can be individually formed based on the alignment mark that is convex on the first surface side and concave on the second surface side.

According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, an alignment error between the first element and the second element is 0.5 μm.
It is as follows. In other words, the conventionally used “double-sided aligner” is provided on both sides of the epitaxial layer.
Alternatively, the first and second elements can be formed using a “stepper”.

According to a fifth aspect of the present invention, in the semiconductor device, the first element and the second element are formed based on a process design standard of 1.0 μm or less. That is, as in the case of the fourth aspect, the first and second elements are formed on both surfaces of the epitaxial layer by using a "stepper" instead of the conventionally used "double-sided aligner". , Process design standard (design rule) is 1.0μ
m or less fine elements can be formed on both surfaces of the epitaxial layer.

The method of manufacturing a semiconductor device according to claim 6 is
A first step of forming a concave portion or a convex portion on the first substrate, forming an epitaxial layer on the surface of the first substrate, and transferring the concave portion or the convex portion on the first substrate to the epitaxial layer. Forming a first element on a surface (first surface) of the epitaxial layer using the alignment mark; and a second step of forming an alignment mark using the alignment mark;
A fourth step of forming a second substrate on the front side of the epitaxial layer, a fifth step of removing the first substrate while leaving the epitaxial layer, and exposing by removing the first substrate. And forming a second element on the back surface (second surface) of the epitaxial layer using the alignment mark. Thereby, an alignment mark that is concave on the front surface (first surface) side and convex on the back surface (second surface) side of the epitaxial layer, or convex on the front surface (first surface) side and has a convex shape on the front surface (first surface) side. 2)
An alignment mark that is concave on the side can be easily formed.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the first step includes a step of forming a concave portion or a convex portion in the first substrate; Or forming a silicon oxide film or a silicon nitride film on the surface of the projection. Accordingly, when the first substrate (for example, a silicon substrate) is removed by etching, the etching rate of the silicon oxide film or the silicon nitride film is made different from the etching rate of the first substrate, thereby stopping the etching. Can be easily controlled, and even the epitaxial layer can be prevented from being etched. As a result, it becomes easy to leave the shape of the alignment mark (the shape of the concave portion and the convex portion) formed on the epitaxial layer as it is.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, after the second element is formed in the sixth step, a through hole is formed in the epitaxial layer using the alignment mark. A seventh step of forming a hole, and electrically connecting the first element on the front surface (first surface) and the second element on the back surface (second surface) via the through hole. And an eighth step of forming a wiring portion to be connected to the semiconductor device. Thereby, an alignment mark that is concave on the front surface (first surface) side and convex on the back surface (second surface) side of the epitaxial layer, or convex on the front surface (first surface) side and has a convex shape on the front surface (first surface) side. The alignment error between the first element on the front surface (first surface), the second element on the back surface (second surface), and the through hole formed based on the alignment mark concave on the second surface side is small. Become.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, in the fourth step, the second substrate and the epitaxial layer are bonded to each other with an inorganic adhesive. It is like that. Usually, since the inorganic adhesive has heat resistance of 800 ° C. or higher, a treatment such as thermal diffusion can be performed while the epitaxial layer is bonded to the second substrate.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the fifth step includes the step of:
The method includes a step of polishing the first substrate to a thickness equal to or less than a certain value by chemical mechanical polishing, and a step of performing wet etching on the polished first substrate. Thereby, the time of the step of exposing the second surface of the epitaxial layer can be reduced.

According to an eleventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, in the fourth step,
As the second substrate, any one of a semiconductor substrate, a glass substrate, a ceramic substrate, and a metal substrate is bonded to the epitaxial layer by an adhesive or an anodic bonding method. Thus, even if the thickness of the epitaxial layer on which the first and second elements are formed is reduced, the strength of the entire semiconductor device is maintained.

According to a twelfth aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the first step includes:
Forming a mask having an opening corresponding to the shape of the alignment mark; selectively forming an epitaxial layer on the first substrate exposed from the mask; and removing the mask. As a result, a convex portion is formed on the semiconductor substrate, and an epitaxial layer can be further formed on the convex portion.

According to a thirteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the first step includes the steps of:
An insulating film according to the shape of the alignment mark is formed on the first substrate. This makes it possible to easily form the projection on the semiconductor substrate. Claim 1
The invention of claim 4 is the method of manufacturing a semiconductor device according to claim 6, wherein the second step is a step of stacking a polycrystalline silicon layer on the first substrate, and the stacked polycrystalline silicon layer. To form an epitaxial layer by single crystallizing. Thereby, an alignment mark which is concave on the front surface (first surface) side and convex on the back surface (second surface) side, or convex on the front surface (first surface) side, and has a concave surface on the back surface (second surface) The epitaxial layer on which the alignment mark which is concave on the side of ()) can be easily formed.

According to a fifteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourteenth aspect, in the first step, the projection on the first substrate is formed of a silicon oxide film or a silicon nitride film. And forming a polycrystalline silicon layer on the first substrate so as to cover the silicon oxide film or the silicon nitride film in the second step. Accordingly, when the first substrate (for example, a silicon substrate) is removed by etching, the etching speed of the silicon oxide film or the silicon nitride film is made different from the etching speed of the first substrate to stop the etching. It becomes easier to control the timing. As a result, it is easy to leave the shape of the alignment mark (the shape of the concave portion and the convex portion) formed on the epitaxial layer as it is, without etching even the epitaxial layer.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to the accompanying drawings. First, an outline of a semiconductor device 10 of the present embodiment will be described with reference to FIG. In the semiconductor device 10 of the first embodiment, the epitaxial layer 104 is provided as a base on which elements are formed. That is, the element formation layer 105 is formed on the first surface 104A side of the epitaxial layer 104.
Is formed, and the element formation layer 111 is formed on the second surface 104B side.

In this embodiment, the element (first element) formed on the element forming layer 105 and the element (second element) formed on the element forming layer 111 have a process of 0.5 μm in this embodiment. The first element and the second element are manufactured by a well-known semiconductor manufacturing technique according to design standards (design rules), and are electrically connected to each other by metal films (wiring portions) 115X and 115Y via through holes 113X and 113Y. Connected. FIG. 1 shows a state where the metal wirings 106X and 106Y in the element formation layer 105 and the metal wirings 110X and 110Y in the element formation layer 111 are electrically connected by metal films 115X and 115Y. The metal wirings 106X and 106Y and the epitaxial layer 104 are insulated from each other so that a short circuit does not occur.

First surface 104A of epitaxial layer 104
The first element (not shown) of the element forming layer 105 formed on the second surface 104B and the element forming layer 111 formed on the second surface 104B
(Not shown) refers to the above-described through-hole 113
It has a predetermined positional relationship that enables connection via X and 113Y. As described above, the first element formed on the first surface 104A and the second element formed on the second surface 104B can be maintained in a predetermined positional relationship when the first element is formed. The alignment marks 11A, 12A on the first surface 104A used for forming the second element and the alignment marks 1 on the second surface 104B used for forming the second element are used.
1B and 12B are the same alignment marks 11 and 1
This is because there is a relationship between the front and back of (2). Note that reference numeral 108 in the drawing denotes a reinforcing substrate (second substrate).

Here, the alignment marks 11A,
Method for manufacturing epitaxial layer 104 on which 12A, 11B, 12B are formed, and alignment mark 11
A method for manufacturing the semiconductor device 10 in which elements are formed on both surfaces of the epitaxial layer 104 using A, 12A and the alignment marks 11B, 12B will be specifically described with reference to FIGS.

(1) First, a resist film 102 is applied on a silicon substrate (first substrate) 101 in which p-type impurities are introduced at a high concentration (for example, 1 × 10 ²⁰ / cm ³ ).
Exposure and development are performed on the resist film 102 using a desired mask pattern, and alignment marks (11
A, 11B, 12A, 12B)
X and 102Y are formed. Here, the silicon substrate 101
The reason why the p-type impurity is introduced at a high concentration is to provide selectivity when the silicon substrate 101 is removed by wet etching, as described later. FIG. 2A shows the device structure obtained in the steps up to here.

(2) The silicon substrate 101 is dry-etched by using the resist film 102 as an etching mask, and recesses 101X and 101Y corresponding to the patterns 102X and 102Y are formed on the silicon substrate 101. After that, the resist film 102 is removed and wet etching is performed to make the surface of the silicon substrate 101 clean. FIG. 2 shows the device structure obtained in the steps up to this point.
(B).

(3) Epitaxy on the upper surface of the silicon substrate 101
The epitaxial layer 104 is formed by using a
Is formed. In this case, the epitaxial layer 104
P-type impurities depending on the concentration of impurities on the silicon substrate 101 side.
The substance has a low concentration (1 × 10¹⁴/ Cm ^Three). this
Sometimes the first surface (front surface) 104A of the epitaxial layer 104
To the recesses 101X and 101Y of the silicon substrate 101
The corresponding recesses (alignment marks 11A, 12A) are shaped
The silicon substrate 1 is formed on the second surface (back surface) 104B.
The protrusions (alignment) corresponding to the recesses 101X and 101Y on the 01 side.
Ment marks 11B and 12B) are formed. So far
FIG. 2C shows the device structure obtained in the step of FIG.

(4) The first surface 104A of the epitaxial layer 104 formed on the upper surface of the silicon substrate 101 is formed on the first surface 104A of the epitaxial layer 104 by using a well-known semiconductor manufacturing technique using the alignment marks 11A and 12A. MOS, bipolar, CCD with polycrystalline silicon wiring, impurity diffusion, metal wiring, etc. formed as required
Is formed. Here, the first surface 104
The layer on which the various elements on the A side are formed is referred to as an element forming layer 105. FIG. 3D shows the device structure obtained in the steps up to here.

(5) An adhesive 107 is applied to the upper surface of the element forming layer 105 of the epitaxial layer 104, and a reinforcing substrate (second substrate) 108 is bonded in this state (FIG. 3E). Here, as the reinforcing substrate 108, a substrate having a thermal expansion coefficient substantially equal to that of the epitaxial layer 104, for example, a silicon substrate, a glass substrate, or a ceramic substrate is used. As the adhesive 107, an inorganic adhesive or a resin adhesive is used. Examples of the inorganic adhesive include a ceramic adhesive (for example, “Ceramar Bond # 516 (trade name)” manufactured by Alecom), a high-temperature inorganic adhesive (for example, “Ceramar Bind 644 (trade name)” manufactured by Alecom), and a low melting point. A silicon oxide-based adhesive such as glass (for example, BPSG) is conceivable. Further, the reinforcing substrate 108 may be bonded by using an anodic bonding method instead of bonding with an adhesive. In particular, depending on the type of ceramic adhesive, 1
It has heat resistance of about 800 ° C.
When a semiconductor element is formed on the second surface 104B side, higher temperature processing can be performed.

(6) The silicon substrate 101 on the second surface 104B side of the epitaxial layer 104 is removed to expose the second surface 104B. Here, the silicon substrate 101
Is subjected to lapping and polishing by a polishing apparatus to reduce the film thickness to a certain value or less (FIG. 3).
(F)) Then, the silicon substrate 101 is completely removed by further performing wet etching (FIG. 4).
(F)). In the thinning by the above-mentioned polishing apparatus, the shorter the distance from the alignment marks 11A and 12A to the polished surface, the shorter the subsequent wet etching time is. Here, the wet etching is performed using, for example, a mixed solution of hydrofluoric acid, nitric acid, and acetic acid (silicon etching liquid). At this time, since the silicon etchant using the mixed solution of hydrofluoric acid, nitric acid, and acetic acid has selectivity depending on the impurity concentration, the etching rate decreases at the interface of the epitaxial layer 104 into which the p-type impurity is introduced at a low concentration, and the epitaxial layer 104 The alignment marks 11B and 12B transferred to the second surface 104B side are prevented from being excessively etched.

(6) Exposed epitaxial layer 10
4, a resist film 109 is formed on the second surface 104B side,
The resist film 109 is patterned based on the alignment marks 11B and 12B. FIG. 4H shows the device structure obtained in the steps up to here. (7) A metal wiring 110X, 1 is formed on the second surface 104B of the epitaxial layer 104 by using the resist film 109.
10Y are formed, and the alignment marks 11B, 1
The formation and patterning of an insulating film, polycrystalline silicon wiring, diffusion of impurities, metal wiring, and the like are formed as necessary by a well-known semiconductor manufacturing technique using 2B, and a desired element such as a MOS, a bipolar, or a CCD is formed. It is formed. Here, a layer on which various elements are formed on the first surface 104B side is referred to as an element forming layer 111. FIG. 4I shows the device structure obtained in the steps up to here.

(8) A resist film 112 is applied on the upper surface of the epitaxial layer 104 on which the element formation layer 111 is formed, and the resist film 112
Patterned using B, 12B. Dry etching is performed using the patterned resist film 112 as an etching mask, and the metal wiring 1 on the first surface 104A side is formed on the element forming layer 111 (oxide film, polycrystalline silicon film, etc.).
Through holes 113X, 113 reaching 06X, 106Y
Y is formed. Here, the metal wirings 106X and 106Y
Are formed with reference to the alignment marks 11A and 12A, and the through holes 113X and 113Y are formed with reference to the alignment marks 11B and 12B.
12B is the concave portion 10 of the silicon substrate 101 as described above.
Since these are the front and back of the alignment marks 11 and 12 formed by 1X and 101Y, they can be accurately formed in a predetermined positional relationship with each other.

(9) Through holes 113X, 113Y
An insulating film 114 is formed on the inner wall of the element and the surface of the element forming layer 111 by, for example, a CVD method (chemical vapor deposition).
The insulating film 114 is removed by photolithographic etching so that the metal wirings 106X and 106Y on the first surface 104A side are exposed. Then, the metal film is formed by the sputtering device or the like on the through holes 113X, 113Y and
It is formed on the entire surface 104B. This metal film is patterned, and a wiring portion (metal film 115X, metal film 115X, 110Y) electrically connects the metal wirings 106X, 106Y on the first surface 104A side of the epitaxial layer 104 and the metal wirings 110X, 110Y on the second surface 104B side. 115Y) is formed. Here, when an element is formed on the second surface 104B, a high-temperature heating step is required depending on the process, and therefore, it is desirable to use a high-melting-point metal (for example, tungsten or titanium) as the metal wires 106X and 106Y. Through these series of manufacturing steps, the semiconductor device 10 having the structure shown in FIG. 1 is manufactured.

In the first embodiment described above, the first
Using both the alignment marks 11A and 12A on the surface 104A and the alignment marks 11B and 12B on the second surface 104B, the first element and the second surface 1 on the first surface 104A are used.
The second element on the 04B side is formed. For example, the alignment mark 11 (11A, 11B) is
The alignment mark 12 (12A, 12B) is used only for forming the first element on the A side, and the second mark on the second surface 104B is used.
It may be used only for the formation of the element of the above. In this case, the alignment marks 11 and 12 are the same,
The alignment mark 11 is formed by the concave portions 101X and 101Y on the silicon substrate 101.
And the alignment mark 12 always have a predetermined positional relationship, and no alignment error occurs between them.

In the first embodiment, after the concave portions 101X and 101Y are formed on the silicon substrate (first substrate) 101 by dry etching, the epitaxial layer 104 is formed on the upper surface of the silicon substrate 101. (FIGS. 2B and 2C), but as shown in FIG.
A silicon oxide film 120 is formed on the upper surface of the silicon substrate 101 on which 01X and 101Y are formed by thermal oxidation or CVD (FIG. 5A), and is patterned to form a silicon oxide film 120X in the recesses 101X and 101Y. , 12
0Y may be formed (FIG. 5B), and the epitaxial layer 104 may be formed from the upper surface (FIG. 5C).

As described above, the recess 10 of the silicon substrate 101
By forming the silicon oxide films 120X and 120Y on 1X and 101Y, when removing the silicon substrate 101 by etching while leaving the epitaxial layer 104, T
By etching with the MAH solution, the etching rates of the silicon oxide films 120X and 120Y and the silicon substrate 101 can be made different, and the timing of stopping the etching can be easily controlled. As a result, the epitaxial layer 104 is not excessively etched, and therefore, the alignment marks 11A, 11B, 12 having the same shape obtained by the concave portions 101X, 101Y.
A, 12B can be formed.

Incidentally, a film as an etching stopper may be formed on the surfaces of the concave portions 101X and 101Y by using a silicon nitride film instead of the silicon oxide film 120. Further, if a projection for forming an alignment mark is formed on the silicon substrate 101, a silicon oxide film or the like as an etching stopper may be similarly formed on the surface thereof. (Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS.

The semiconductor device 20 according to the second embodiment
Indicates that the alignment marks 21A, 21B, 22A, 22B formed on the epitaxial layer 204 have the first shape.
Alignment marks 11A, 11B, 1
Different from 2A and 12B.

That is, in the semiconductor device 20, convex alignment marks 21A and 22A are formed on the first surface 204A side of the epitaxial layer 204 on which elements are formed.
On the second surface 204B side, a concave alignment mark 21B,
22B are formed. The first element formed in the element formation layer 205 of the semiconductor device 20, the element formation layer 211
In this embodiment, the second element formed in the.
The first element and the second element are manufactured by a well-known semiconductor manufacturing technique based on a process design standard (design rule) of 5 μm, and the first element and the second element are mutually connected via a metal film (wiring portion) 215X , 215Y.

In forming the first element on the element forming layer 205 side, the alignment marks 21A and 22A on the front side of the alignment marks 21 and 22 are used.
In forming the second element on the element forming layer 211 side, the alignment marks 21B and 22B on the back side of the alignment marks 21 and 22 are used to form the epitaxial layer 20.
The first and second elements respectively formed on the fourth first surface 204A and the second surface 204B are maintained in a predetermined positional relationship with each other.
Also in this case, the alignment marks 21A and 22A and the alignment marks 21B and 22B have the relationship of the front and back of the alignment marks 21 and 22.

The structure of the semiconductor device 20 other than the alignment marks 21A, 21B, 22A, and 22B is the same as that of the semiconductor device 10 of the first embodiment. Here, a method of manufacturing the epitaxial layer 204 on which the alignment marks 21A and 22A and the alignment marks 21B and 22B are formed, and a method of manufacturing the semiconductor device 20 using the alignment marks 21A and 21B and the alignment marks 22A and 22B are described. 7, FIG.
This will be described with reference to FIG.

(1) First, a thermal oxide film (silicon oxide film) 2 is formed on a silicon substrate (first substrate) 201 in which p-type impurities are introduced at a high concentration (for example, 1 × 10 ²⁰ / cm ³ ).
22 is formed, and a resist film 202 is applied thereon. Exposure and development are performed on the resist film 202 using a mask pattern, and alignment marks (21A, 2A) are formed.
1B, 22A, 22B).
02Y is formed. FIG. 7A shows the device structure obtained in the steps up to here.

(2) Using the resist film 202 as a mask, the thermal oxide film 222 on the silicon substrate 201 is etched, and patterns 222X and 222Y corresponding to the patterns 202X and 202Y are formed by the thermal oxide film 222. (FIG. 7 (b)). Then, the resist film 202 is removed, and the surface of the thermal oxide film 222 is cleaned.
The epitaxial layers 223X and 223Y are selectively formed thereon so as to have the same type and the same impurity concentration as the silicon substrate 201. FIG. 7C shows the device structure obtained in the steps up to here.

(3) The thermal oxide film 222 is removed by etching using a hydrofluoric acid-based etchant, and the surface of the silicon substrate 201 is cleaned.
01 and the epitaxial layers 204 are formed on the upper surfaces of the epitaxial layers 223X and 223Y. This epitaxial layer 204 corresponds to the epitaxial layer 1 of the first embodiment.
04, the p-type impurity has a low concentration (1 × 10 ¹⁴ / cm
³ ). This epitaxial layer 2
A convex portion (alignment mark 21A, 22A) is formed on the first surface (front surface) 204A of the substrate 04 by the epitaxial layers 223X, 223Y, and the second surface (lower surface) 204B is formed.
Then, concave portions (alignment marks 21B and 22B) are formed by the epitaxial layers 223X and 223Y.
FIG. 7D shows the device structure obtained in the steps up to here.

(4) Using the alignment marks 21A and 22A on the first surface 204A of the epitaxial layer 204 formed on the upper surface of the silicon substrate 201, formation of an insulating film, patterning, MOS, bipolar, CCD with polycrystalline silicon wiring, impurity diffusion, metal wiring, etc. formed as required
A desired element such as is formed (element formation layer 205). FIG. 8E shows the device structure obtained in the steps up to here.

(5) An adhesive 207 is applied to the upper surface of the element forming layer 205 of the epitaxial layer 204, and a reinforcing substrate (second substrate) 208 is bonded. The adhesive 207 and the reinforcing substrate 208 used at this time are the same as the adhesive 107 and the reinforcing substrate 108 of the first embodiment. FIG. 8 shows the device structure obtained in the steps so far.
(F).

(6) The silicon substrate 201 on the second surface 204B side of the epitaxial layer 204 is removed by the same method as in the first embodiment, and the epitaxial layer 204 is removed.
The second surface 204B is exposed. FIG. 8G shows the device structure obtained in the steps up to here. (6) Second surface 2 of exposed epitaxial layer 204
On the 04B side, based on the alignment marks 21B and 22B, an insulating film is formed, patterned, polycrystalline silicon wiring, impurity diffusion, metal wiring, and the like are formed as necessary by a well-known semiconductor manufacturing technique. A desired element such as a bipolar, a CCD or the like is formed (element forming layer 211).

Further, a resist film 212 is applied on the upper surface of the epitaxial layer 204 on which the element forming layer 211 is formed, and the resist film 212
B and 22B. Dry etching is performed using the patterned resist film 212 as an etching mask, and the metal wiring 2 on the first surface 204A side is formed on the element forming layer 211 (oxide film, polycrystalline silicon film, etc.).
Through holes 213X, 213 leading to 06X, 206Y
Y is formed. Note that there is no short circuit between the metal wirings 206X and 206Y and the epitaxial layer 204. Also in the second embodiment, the metal wirings 206X and 206Y are formed based on the alignment marks 21A and 22A, and the through holes 213X and 213Y are formed on the alignment mark 2A.
1B and 22B. FIG. 8H shows the device structure obtained in the steps up to here.

(7) Through holes 213X and 213Y
An insulating film 214 is formed on the inner wall of the device and the surface of the element forming layer 211, and then the metal wiring 206 on the first surface 204A side is formed.
The insulating film 214 is removed by a photolithographic etching method so that X and 206Y are exposed. After that, the metal film is formed in the through hole 213 by a sputtering device or the like.
X, 213Y and the entire surface of the second surface 204B.
This metal film is patterned and the epitaxial layer 20
No. 4 metal wirings 206X and 206Y on the first surface 204A side
And a wiring section (metal film 215X, metal film 215X,
215Y) is formed. Through these series of manufacturing steps, the semiconductor device 20 having the structure shown in FIG. 6 is manufactured.

(Third Embodiment) Next, a third embodiment of the present invention will be described.
The embodiment will be described with reference to FIGS. 9 and 10. FIG.
In the semiconductor device 30 according to the third embodiment, the alignment marks 31A, 31B, 3
The point that oxide films 323X and 323Y are previously formed on the silicon substrate 301 in forming the 2A and 32B is different from the above-described second embodiment.

The first element formed on the element forming layer 305 of the semiconductor device 30 and the second element formed on the element forming layer 311 also have a process design standard of 0.5 μm in this embodiment. The first element and the second element are electrically connected to each other by metal films (wiring portions) 315X and 315Y via through holes 313X and 313Y. Have been.

In forming the first element of the element forming layer 305, the alignment marks 31A and 31B on the front side of the alignment marks 31 and 32 are used, and in forming the second element of the element forming layer 311. By using the alignment marks 32A and 32B on the back side of the alignment marks 31 and 32, the elements are maintained in a predetermined positional relationship on the first surface 304A and the second surface 304B of the epitaxial layer 304. The semiconductor device 3
The other structure is the same as that of the semiconductor device 20 of the above-described second embodiment.

Here, the alignment marks 31A, 32
A, a method for manufacturing the epitaxial layer 304 on which the alignment marks 31B and 32B are formed, and a method for manufacturing the semiconductor device 30 using the alignment marks 31A, 31B, 32A and 32B will be described with reference to FIG. (1) First, a high concentration of p-type impurities (for example, 1 × 10 ²⁰
/ Cm ³ ) introduced silicon substrate (first substrate) 3
A thermal oxide film (silicon oxide film) is formed on the substrate 01, and this thermal oxide film is etched using a resist film (not shown) having a predetermined mask pattern, and FIG.
Thermal oxide films 332X and 332Y shown in FIG.

(2) The epitaxial layer 30 is formed on the silicon substrate 301 on which the thermal oxide films 332X and 332Y are formed.
4 are formed. The epitaxial layer 304 is not necessarily a perfect single crystal on the thermal oxide films 332X and 332Y, but does not pose a problem since no element is originally formed in a portion where an alignment mark is formed. The epitaxial layer 304 has a low concentration of p-type impurities (1 × 10 4), similarly to the epitaxial layer 204 of the second embodiment.
¹⁴ / cm ³ ). At this time, concave portions (alignment marks 31A and 32A) formed by thermal oxide films 332X and 332Y on silicon substrate 301 are formed on first surface (front surface) 304A of epitaxial layer 304, and second surface (lower surface) 304B is also formed on second surface (lower surface) 304B. Thermal oxide film 332X,
The protrusion corresponding to 332Y (the alignment mark 31B, 3
2B) is formed. FIG. 10B shows the device structure obtained in the steps up to here.

(3) An insulating film is formed or patterned on the first surface 304A of the epitaxial layer 304 formed on the upper surface of the silicon substrate 301 by well-known semiconductor manufacturing techniques using the alignment marks 31A and 32A. MOS, bipolar, CCD with polycrystalline silicon wiring, impurity diffusion, metal wiring, etc. formed as required
A desired element such as is formed (element formation layer 305). Then, an adhesive 307 is applied to the upper surface of the element formation layer 305 of the epitaxial layer 304, and a reinforcing substrate (second substrate) 308 is attached. The adhesive 307 and the reinforcing substrate 308 used at this time are the same as the adhesive 107 and the reinforcing substrate 108 of the first embodiment. FIG. 10C shows the device structure obtained in the steps up to here.

(4) The silicon substrate 301 on the second surface 304B side of the epitaxial layer 304 is removed by the same method as in the first embodiment, and the epitaxial layer 304 is removed.
The second surface 304B is exposed. Then, on the second surface 304B side of the exposed epitaxial layer 304, based on the alignment marks 31B and 32B, a known semiconductor manufacturing technique is used to form an insulating film, pattern, polycrystalline silicon wiring, impurity diffusion, metal Wiring and the like are formed as needed, and desired elements such as MOS, bipolar, CCD and the like are formed (element formation layer 311).

Further, a resist film 312 is applied on the upper surface of the element forming layer 311 and the resist film 312 is patterned using the alignment marks 31B and 32B. Dry etching is performed using the patterned resist film 312 as an etching mask to form an element forming layer 3.
11, metal wirings 306X and 306 on the first surface 304A side.
Through holes 313X and 313Y reaching Y are formed. Note that there is no short circuit between the metal wirings 306X and 306Y and the epitaxial layer 304. Also in the second embodiment, the metal wirings 306X and 306Y are formed based on the alignment marks 31A and 32A, and the through holes 313 are formed.
X and 313Y are formed with reference to the alignment marks 31B and 32B.
A, the alignment marks 31B and 32B are formed on the thermal oxide films 332X and 332Y on the silicon substrate 301 as described above.
Therefore, it is formed at the same position on the front and back of the epitaxial layer 304. FIG. 10D shows the device structure obtained in the steps up to here.

(5) Through holes 313X, 313Y
An insulating film 314 is formed on the inner wall of the element and the surface of the element forming layer 311, and then the metal wiring 306 on the first surface 304 A side is formed.
The insulating film 314 is removed by a photolithographic etching method so that X and 306Y are exposed. After that, the metal film is formed in the through hole 313 by a sputtering device or the like.
X, 313Y and the entire surface of the second surface 304B.
This metal film is patterned and the epitaxial layer 30
4 metal wirings 306X and 306Y on the first surface 304A side
And a wiring portion (metal film 315X, metal film 315X) for electrically connecting the metal wirings 310X, 310Y on the second surface 304B side to each other.
315Y) is formed. Through these series of manufacturing steps, the semiconductor device 30 having the structure shown in FIG. 9 is manufactured.

The thermal oxide film 33 is formed in the recesses of the epitaxial layer 304 that constitute the alignment marks 31B and 32B.
Even if 2X and 332Y remain, the second surface 3
Since the alignment marks 21B and 22B can be optically detected from the 04B side, the alignment work is not affected. Instead of the thermal oxide films 332X and 332Y of the third embodiment, another insulating film (for example, a silicon nitride film or a silicon oxide film deposited by CVD or the like) may be used.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described.
The embodiment will be described with reference to FIGS. The semiconductor device 40 of the fourth embodiment is described above in that a polycrystalline silicon layer is deposited on a silicon substrate 401 and heated by a laser annealing device or the like to form an epitaxial layer 404. This is different from the second embodiment.

In this embodiment, the first element formed on the element formation layer 405 and the second element formed on the element formation layer 411 of this semiconductor device 40 also have a process design standard (design) of 0.5 μm. The first element and the second element are electrically connected to each other by metal films (wiring portions) 415X and 415Y via through holes 413X and 413Y. I have.

In forming the first element on the element forming layer 405, the alignment marks 41A and 42A on the front side of the alignment marks 41 and 42 are used.
In forming the first element in the element formation layer 411,
The alignment marks 41B and 42B on the back side of the alignment marks 41 and 42 are used, and the epitaxial layer 40
In the fourth first surface 404A and the second surface 404B, the elements are maintained in a predetermined positional relationship.

Here, the alignment marks 41A, 42
A, a method for manufacturing the epitaxial layer 404 on which the alignment marks 41B and 42B are formed, and a method for manufacturing the semiconductor device 40 using the alignment marks 41A, 41B, 42A and 42B will be described with reference to FIGS. . (1) First, a high concentration of p-type impurities (for example, 1 × 10 ²⁰
/ Cm ³ ) introduced silicon substrate (first substrate) 4
01, a thermal oxide film (silicon oxide film) 422 is formed, a resist film is applied on the upper surface thereof, and alignment marks 41A and 41 are formed by a known photolithography technique.
B, resist films 402X, 40 corresponding to 42A, 42B
2Y is formed. FIG. 12A shows the device structure obtained in the steps up to here.

(2) The resist films 402X and 402
The thermal oxide film 422 is etched using Y as a mask, and the convex portions 422 corresponding to the resist films 402X and 402Y.
X, 422Y are formed. After that, the resist film 402
Is removed and the surface of thermal oxide film 422 is cleaned. FIG. 12 shows the device structure obtained in the steps so far.
(B).

(3) A polycrystalline silicon layer is formed on the upper surface of the thermal oxide film 422 on which the protrusions 422X and 422Y are formed. This polycrystalline silicon layer has the same concentration as the epitaxial layer 104 of the first embodiment (1 × 10 ¹⁴ / cm 3).
³ ) p-type impurities are introduced. At this time, heating is performed on the polycrystalline silicon layer using a laser annealing apparatus, and the polycrystalline silicon layer is monocrystallized to form an epitaxial layer 404. On the first surface 404A of the epitaxial layer 404, the projections 422X of the thermal oxide film 422,
The projections (alignment marks 41A, 4A)
2A) is formed, and the convex portions 422X,
The recesses (alignment marks 41B, 4B)
2B) is formed. FIG. 12C shows the device structure obtained in the steps up to here.

(4) The first surface 404A of the epitaxial layer 404 formed on the upper surface of the silicon substrate 401 is formed using an alignment mark 41A, 42A by a well-known semiconductor manufacturing technique to form or form an insulating film. MOS, bipolar, CCD with polycrystalline silicon wiring, impurity diffusion, metal wiring, etc. formed as required
A desired element such as is formed (element formation layer 405). Then, an adhesive 407 is applied to the upper surface of the element formation layer 405 of the epitaxial layer 404, and a reinforcing substrate (second substrate) 408 is attached. The adhesive 407 and the reinforcing substrate 408 used at this time are the same as the adhesive 107 and the reinforcing substrate 108 of the first embodiment. FIG. 13D shows the device structure obtained in the steps up to here.

(5) The silicon substrate 401 on the second surface 404B side of the epitaxial layer 404 is removed by the same method as in the first embodiment, and the thermal oxide film 422 is further removed. The two surfaces 404B are exposed. FIG. 13G shows the device structure obtained in the steps up to here. Here, by controlling the etching using the fact that the thermal oxide film (silicon oxide layer) is different from the silicon substrate (first substrate) 401 in the etching rate, the shape of the alignment mark ( Even the recesses and projections remain unchanged without being etched.

(6) Exposed epitaxial layer 40
4 with respect to the second surface 404B.
B, 42B, using a well-known semiconductor manufacturing technique,
Insulation film formation, patterning, polycrystalline silicon wiring,
Diffusion of impurities, metal wiring, etc. are formed as necessary
A desired element such as an OS, a bipolar, a CCD, etc. is formed (element formation layer 411).

Further, a resist film 412 is applied on the upper surface of the epitaxial layer 404 on which the element forming layer 411 is formed, and the resist film 412 is
B, 42B. Dry etching is performed using the patterned resist film 412 as an etching mask, and the metal wiring 4 on the first surface 404A side is formed on the element forming layer 411 (oxide film, polycrystalline silicon film, etc.).
Through holes 413X, 413 leading to 06X, 406Y
Y is formed. Note that the metal wirings 406X and 406Y and the epitaxial layer 404 are not short-circuited.

Also in the second embodiment, the metal wiring 40
6X and 406Y are formed based on the alignment marks 41A and 42A, and the through holes 413X and 413Y are formed based on the alignment marks 41B and 42B.
FIG. 13F shows the device structure obtained in the steps up to this point.
Shown in (7) An insulating film 414 is formed on the inner walls of the through holes 413X and 413Y and on the surface of the element formation layer 411, and thereafter, the metal wirings 406X and 406X on the first surface 404A side
The insulating film 414 is formed by photolithography so that 06Y is exposed.
It is removed by an etching method. Then, the metal film is formed in the through-holes 413X, 41
3Y and the entire surface of the second surface 404B. This metal film is patterned and the first layer of the epitaxial layer 404 is formed.
Wiring portions (metal films 415X and 415Y) for electrically connecting the metal wirings 406X and 406Y on the surface 404A side and the metal wiring 410 on the second surface 404B side are formed. Through these series of manufacturing steps, the semiconductor device 40 having the structure shown in FIG. 11 is manufactured.

The oxide film 422 of the fourth embodiment is used.
Instead, another insulating film (for example, a silicon oxide film or a silicon nitride film deposited by CVD or the like) may be used.

[0075]

As described above, according to the semiconductor device of the first aspect, the first element is provided on the first surface side of the epitaxial layer on the substrate side, and the first element is provided on the opposite side of the epitaxial layer from the substrate. Since the second element is formed on each of the two surfaces,
A semiconductor device in which a large number of fine elements are formed can be downsized and highly integrated.

According to the semiconductor device of the second aspect, the thickness of the epitaxial layer can be made thinner than that of a semiconductor substrate generally used as a substrate on which elements are formed. The aspect ratio of the through hole for electrical connection is reduced, and the through hole can be easily formed. According to the semiconductor device of the third aspect, a "stepper" is used on both sides of the epitaxial layer instead of the "double-sided aligner" conventionally used, and a concave shape is formed on the first surface side of the epitaxial layer. Since the first and second elements can be formed on the basis of the alignment mark that is convex on the surface side, or the alignment mark that is convex on the first surface side and concave on the second surface side, The alignment accuracy in the semiconductor manufacturing process is significantly improved, and the first and second elements can be formed with a process design standard of at least 1.0 μm or less.

According to the semiconductor device of the fourth aspect, the first and second elements are formed on both surfaces of the epitaxial layer using the "stepper", and the alignment error is reduced by 0.5 μm.
m, the first element and the second element can be finely formed and easily associated with each other (for example, electrically connected).

According to the semiconductor device of the fifth aspect, the first
And the second element are formed based on a process design standard of 1.0 μm or less, so that these fine elements can be formed on both surfaces of the epitaxial layer in a highly integrated manner in a predetermined positional relationship with each other. According to the method of manufacturing a semiconductor device of the present invention, the alignment mark is concave on the surface (first surface) side of the epitaxial layer and convex on the back surface (second surface). It is possible to easily form an alignment mark having a convex shape on the (surface) side and a concave shape on the back surface (the second surface) side. Can be formed.

According to the method of manufacturing a semiconductor device of the present invention, the silicon oxide film or the silicon nitride film is formed on the surface of the concave or convex portion formed on the first substrate, and the epitaxial layer is formed on the upper surface thereof. When the first substrate (for example, a silicon substrate) is removed by etching while leaving the epitaxial layer, the etching rate of the silicon oxide film or the silicon nitride film is reduced by the etching rate of the first substrate. By making them different, it becomes easy to control the timing of stopping the etching. As a result, the shape of the alignment mark (the shape of the concave portion and the convex portion) formed on the epitaxial layer can be left as it is, without the unnecessary etching of the epitaxial layer.
The accuracy of alignment using the alignment mark can be improved.

According to the method of manufacturing a semiconductor device of the present invention, the first element on the front surface (first surface) and the back surface (second surface) are based on the alignment mark formed on the epitaxial layer. Since the second element and the through-hole are formed, the alignment error between them is reduced, and the first element and the second element are easily electrically connected via the through-hole.

According to the method of manufacturing a semiconductor device of the ninth aspect, the second substrate and the epitaxial layer are generally bonded to each other with an inorganic adhesive having heat resistance of 800 ° C. or more. Can be subjected to a high-temperature treatment such as thermal diffusion while the substrate is bonded to the second substrate. According to the method of manufacturing a semiconductor device of claim 10,
The processing time of the step of exposing the second surface of the epitaxial layer can be reduced.

According to the method of manufacturing a semiconductor device of the present invention, any one of a semiconductor substrate, a glass substrate, a ceramic substrate, and a metal substrate is bonded on the epitaxial layer by an adhesive or an anodic bonding method. Therefore, the strength of the entire semiconductor device can be maintained even if the thickness of the epitaxial layer on which the first and second elements are formed is reduced. Since the thickness of the epitaxial layer can be reduced, the aspect ratio of a through hole formed in the epitaxial layer can be reduced, which is advantageous for forming various devices.

According to the method of manufacturing a semiconductor device of the twelfth aspect, a convex portion is formed on a semiconductor substrate, and a high-quality epitaxial layer can be formed on an upper surface thereof. According to the method of manufacturing a semiconductor device of the thirteenth aspect, it is possible to easily form a convex portion on a semiconductor substrate with an insulating film and form an epitaxial layer on an upper surface thereof. In addition, even if the insulating film remains on the epitaxial layer, the alignment mark can be optically detected from the second surface side during alignment, so that the alignment film is not affected and the alignment film is not affected. Since there is no need to remove, the manufacturing process is simplified.

According to the method of manufacturing a semiconductor device of the fourteenth aspect, the epitaxial layer on which the concave or convex alignment marks are formed can be easily formed irrespective of the material of the underlying substrate. Can be. Claim 15
According to the method of manufacturing a semiconductor device, the convex portion on the first substrate is formed of a silicon oxide film or a silicon nitride film, and a polycrystalline silicon layer is stacked on the first substrate so as to cover the silicon oxide film or the silicon nitride film. After that, since the first substrate is removed by etching, the silicon oxide film or the silicon nitride film controls the etching by utilizing the fact that the etching speed is different from that of the first substrate (silicon substrate),
Accordingly, even the shape of the alignment mark (the shape of the concave portion and the convex portion) formed on the epitaxial layer can be left as it is without being etched, and more accurate alignment can be performed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device 10 according to a first embodiment.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the semiconductor device 10 according to the first embodiment.

FIG. 3 is a sectional view illustrating a manufacturing process of the semiconductor device 10 according to the first embodiment;

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the semiconductor device 10 according to the first embodiment.

FIG. 5 is a sectional view illustrating a manufacturing process of the semiconductor device 10 according to the first embodiment.

FIG. 6 is a cross-sectional view illustrating a structure of a semiconductor device 20 according to a second embodiment.

FIG. 7 is a sectional view illustrating a manufacturing process of the semiconductor device 20 according to the second embodiment;

FIG. 8 is a sectional view illustrating a manufacturing process of the semiconductor device 20 according to the second embodiment.

FIG. 9 is a cross-sectional view illustrating a structure of a semiconductor device 30 according to a third embodiment.

FIG. 10 is a cross-sectional view showing a manufacturing process of the semiconductor device 30 according to the third embodiment.

FIG. 11 is a cross-sectional view illustrating a structure of a semiconductor device 40 according to a fourth embodiment.

FIG. 12 is a sectional view illustrating a manufacturing process of a semiconductor device 40 according to a fourth embodiment.

FIG. 13 is a sectional view illustrating a manufacturing process of the semiconductor device 40 according to the fourth embodiment;

FIG. 14 is a view showing a conventional semiconductor device in which elements are formed on both surfaces of a semiconductor substrate 1.

[Explanation of symbols]

10, 20, 30, 40 Semiconductor device 11, 12, 21, 22, 31, 32, 41, 42 Alignment mark 11A, 12A, 21A, 22A, 31A, 32A, 4
1A, 42A Alignment marks 11B, 12B, 21B, 22B, 31B, 32B, 4
1B, 42B Alignment marks 101, 201, 301, 401 Silicon substrate (first
101X, 101Y Depressions 104, 204, 304, 404 Epitaxial layers 104A, 204A, 304A, 404A First surface 104B, 204B, 304B, 404B Second surface 105, 205, 305, 405 Element formation layer 106X, 106Y, 206X, 206Y, 306X,
306Y, 406X, 406Y Metal wiring 108, 208, 308, 408 Reinforcement substrate (second substrate) 110X, 110Y, 210X, 210Y, 310X,
310Y, 410X, 410Y Metal wirings 111, 211, 311, 411 Element formation layers 113X, 113Y, 213X, 213Y, 313X,
313Y, 413X, 413Y Through holes 115X, 115Y, 215X, 215Y, 315X,
315Y, 415X, 415Y Metal film

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/027 H01L 21/30 522Z 21/3205 21/88 J 27/00 301 F-term (Reference) 5F033 GG03 HH07 JJ07 KK18 KK19 MM30 NN40 PP15 QQ01 QQ37 SS11 5F038 CA02 CA12 CA16 EZ12 EZ14 EZ15 EZ17 EZ20 5F045 AB02 AB03 AB32 AB33 AF03 CA01 CA06 DB02 GH09 HA03 HA13 HA14 HA18 5F046 EA12 EA13 FC

Claims (15)

[Claims] 1. A semiconductor device having an epitaxial layer formed on a substrate, wherein a first element is provided on a first surface side of the epitaxial layer on the substrate side, and a second element is provided on a side of the epitaxial layer opposite to the substrate. A semiconductor device, wherein a second element is formed on a surface side. 2. The method according to claim 1, wherein the first element and the second element are:
2. The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected through a through hole formed in the epitaxial layer. 3. A method according to claim 1, wherein the predetermined position of the epitaxial layer is
An alignment mark that is concave on the first surface side and convex on the second surface side, or an alignment mark that is convex on the first surface side and concave on the second surface side is formed. The semiconductor device according to claim 1, wherein: 4. The semiconductor device according to claim 1, wherein an alignment error between said first element and said second element is 0.5 μm or less. . 5. The method according to claim 1, wherein the first element and the second element are:
5. The semiconductor device according to claim 1, wherein the semiconductor device is formed based on a process design standard of 1.0 μm or less. 6. A first step of forming a concave portion or a convex portion on a first substrate, forming an epitaxial layer on a surface of the first substrate, and forming a concave portion or a convex portion on the first substrate, A second step of forming an alignment mark by transferring to an epitaxial layer; a third step of forming a first element on the surface of the epitaxial layer using the alignment mark; A fourth step of forming a second substrate, a fifth step of removing the first substrate while leaving the epitaxial layer, and a step of removing the first substrate by removing the epitaxial layer. And a sixth step of forming a second element by using the alignment mark that appears. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the first step includes forming a concave portion or a convex portion on the first substrate, and oxidizing a surface of the concave portion or the convex portion. Forming a silicon film or a silicon nitride film. 8. The method of manufacturing a semiconductor device according to claim 6, wherein after forming the second element in the sixth step, a through hole is formed in the epitaxial layer using the alignment mark. Step 7, and the first element and the second element through the through hole.
An eighth step of forming a wiring portion for electrically connecting the element to the semiconductor device. 9. The method of manufacturing a semiconductor device according to claim 6, wherein in the fourth step, the second substrate and the epitaxial layer are bonded with an inorganic adhesive. Device manufacturing method. 10. The method of manufacturing a semiconductor device according to claim 6, wherein said fifth step is a step of polishing said first substrate to a thickness equal to or less than a predetermined value by chemical mechanical polishing. Subjecting said first substrate to wet etching. 11. The method of manufacturing a semiconductor device according to claim 6, wherein in the fourth step, any one of a semiconductor substrate, a glass substrate, a ceramic substrate, and a metal substrate is used as the second substrate. A method for manufacturing a semiconductor device, comprising: bonding an epitaxial layer on an epitaxial layer by an adhesive or an anodic bonding method. 12. The method of manufacturing a semiconductor device according to claim 6, wherein the first step includes: forming a mask having an opening corresponding to a shape of the alignment mark; and forming a first mask exposed from the mask. A method of selectively forming an epitaxial layer on the substrate, and a step of removing the mask. 13. The method of manufacturing a semiconductor device according to claim 6, wherein in the first step, an insulating film according to a shape of the alignment mark is formed on the first substrate. A method for manufacturing a semiconductor device. 14. The method of manufacturing a semiconductor device according to claim 6, wherein said second step is a step of stacking a polycrystalline silicon layer on said first substrate; and said stacked polycrystalline silicon layer. Forming a epitaxial layer by monocrystallizing the semiconductor device. 15. The method of manufacturing a semiconductor device according to claim 14, wherein in the first step, a convex portion is formed on the first substrate by a silicon oxide film or a silicon nitride film; In the manufacturing method, a polycrystalline silicon layer is stacked on the first substrate so as to cover the silicon oxide film or the silicon nitride film.