JP2002033394A - Integrated circuit with double-damascene structure and capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sidewall capacitor in an integrated circuit containing double-damascene structure. SOLUTION: The integrated circuit has both the double-damascene structure and the capacitor and a metallization level. The structure is included into the metallization level, thus eliminating the need for additional treatment processes, when the different structure is formed. It should be understood that the above items mentioned and following detailed explanation are instances, and do not restrict the present invention.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to integrated circuits and, more particularly, to dual damascene structures and capacitors in integrated circuits.

[0002]

BACKGROUND OF THE INVENTION Interdigital or finger capacitors have become increasingly used in integrated circuits as the height of the metal lines within the integrated circuit has become greater than the space between the metal lines. This occurs because the dimensions of the device are reduced, and consequently the distance between the metal lines is reduced. Mutual digital or finger capacitors use sidewall capacitance. This capacitance is created between adjacent metal lines to form a capacitor.

One example of a finger capacitor is a CHIP
U.S. Patent No. 6,037,62 issued to Wilson entitled CAPACITOR Structure.
No. 1 is shown. This patent is incorporated herein by reference. The concept of forming a capacitor using sidewall capacitance is also described in Fractal Capaci
H. tors. Samavati et al., 199
8 years ISSCC, Session 16, TD: Advan
ced Radio Frequency Circuit
its, Paper FP 16.6, 256-57. This article is incorporated herein by reference. The article points out that as the distance between the plates decreases, the sidewall or fringe capacitance produces higher capacitance per unit area than conventional parallel plate capacitors.

[0004]

In addition to the reduction in device size, there is a trend to use dual damascene structures instead of single damascene structures. Single damascene is an interconnect manufacturing process for integrated circuits that forms a groove in an insulating layer and fills the groove with a conductive material to form an interconnect. Dual damascene is a multi-level interconnect process that, in addition to forming a single damascene trench, also forms conductive contact (or via) openings in the insulating layer. Conductive materials include grooves and conductive contacts (or vias)
It is formed in the opening. The inventor has recognized the need to combine these trends to provide sidewall capacitors in integrated circuits that include dual damascene structures.

[0005]

SUMMARY OF THE INVENTION The present invention is directed to an integrated circuit having a metallization level, having both a dual damascene structure and a capacitor. By including these structures within the metallization level, additional processing steps in forming these different structures may be avoided. It is to be understood that the foregoing general description and the following detailed description are exemplary and are not restrictive of the invention.

The invention is best understood from the following detailed description when read with reference to the accompanying drawings. It is emphasized that by convention in the semiconductor industry, the various features of the drawings are not drawn to scale.
On the other hand, the dimensions of the various features are arbitrarily enlarged or reduced for clarity.

[0007]

DETAILED DESCRIPTION OF THE INVENTION An exemplary embodiment of the present invention is directed to a process for forming a dual damascene structure.
The process includes forming a stack having an insulating layer and a stop layer, with two masks formed above the stack. One of the masks is used to form a via or contact opening in the insulating layer and to form an opening for the capacitor. The second mask is used to form interconnect trenches in the insulating layer. By forming openings for capacitors in forming trenches and vias for dual damascene structures, the number of processing steps and the movement of partially manufactured integrated circuits between systems may be reduced.

Here, reference is made to the drawings. Like reference numerals refer to like elements throughout the drawings. FIG.
5 is a flowchart illustrating an exemplary embodiment of the present invention. 2 to 7 are schematic diagrams illustrating successive stages in the manufacture of an integrated circuit according to the flowchart shown in FIG.

In step 10, the first insulating layer 10
5 is formed on the substrate 100. First insulating layer 105
Is, for example, densely deposited silicon oxide (eg,
SiO ₂). Alternatively, the first insulation
The layers may be borophosphosilicate glass, phosphosilicate glass, phosphorus and / or
Is tetraethylorthosilicate doped with boron
Glass, spin-on glass, xeroge
, Airgel, or polymer, fluorinated oxide and
Hydrogen silsesquioxane
Other low-k films such as uioxane). Further
Preferably, at least one of the insulating layers has a high dielectric constant.
Including multiple layers that are low dielectric constant materials formed between other layers
obtain.

The substrate 100 is, for example, a semiconductor such as silicon or a compound semiconductor such as GaAs or SiGe. Alternatively, the substrate 100 includes a dielectric, a conductor,
Or it may be an intermediate layer in an integrated circuit, such as another material.
Further, the upper surface 101 of the substrate 100 may not be flat. In this case, the first insulating layer 105 can be planarized using, for example, chemical mechanical polishing (CMP), as is well known.

In step 15, the etch stop layer 11
0 is above the first insulating layer 105 or the first insulating layer 1
05 in direct contact. In other embodiments, 1
One or more layers may be formed between the etch stop layer 110 and the first insulating layer 105. The material of the etch stop layer is the first for the selected etchant.
May be selected so as to have a higher etching resistance than the insulating layer 105. In other words, the etch stop layer 1
10 is etched at a slower rate than the first insulating layer 105 when exposed to the selected etchant. For example, the etch stop layer is first insulating layer may be a TiN when a SiO _2. Furthermore, the etch stop _{layer, Ta / TaN, Si 3 N} 4, the oxide-rich silicon, or a multilayer SiO ₂ dielectric.

In step 20, the second insulating layer 115
Is formed above or in direct contact with the etch stop layer 110. Second insulating layer 1
15 may be formed of the same materials and processes used to form first insulating layer 105. Step 2
At 5, a first patterned mask 120 is formed above or on the second insulating layer 115. The first patterned mask 120 includes openings corresponding to vias or contact openings 125 (hereinafter referred to as “openings”) for providing interconnects between different levels in the integrated circuit. Further, the first patterned mask 12
0 includes openings corresponding to openings 127 for capacitors (hereinafter referred to as “capacitor openings”). The reticle 90 is configured such that the capacitor opening 127
Has a pattern that can be formed when is formed.

In step 30, opening 125 and capacitor opening 127 are opened in first insulating layer 105, etch stop layer 110, and second insulating layer 115. The openings and capacitor openings may be opened by etching at least three different layers using conventional etching techniques or a combination of techniques. Alternatively, in step 30, the second insulating layer 1
Only 15 can be etched. In this case, step 4
At 0, the exposed portion of the etch stop layer 110 and the corresponding portion of the first insulating layer 105 below the exposed portion are etched, completing the capacitor openings 127 and 125 when the trench is etched. The capacitor openings 127 can be formed within the same metallization level, neither above nor below each other.

Illustratively, the openings are: 1) applying a layer of resist material (first patterned mask) over the second insulating layer 115, and 2) applying a resist to the energy source passing through the reticle. It is formed by exposing the material, 3) removing a region of the resist to form a pattern in the resist, and 4) etching the opening 125 and the capacitor opening 127. Energy sources are electron beam, light source,
Or any other suitable energy source.

Next, in step 35, a second patterned mask 130 is formed above or on the first patterned mask 120. Illustratively, the second patterned mask 130 has openings 125 and 1 on the first patterned mask 120.
27) apply a layer of resist material in 27, 2) reticle 95
3) exposing the resist material to an energy source passing through it and 3) removing regions of the resist to form a pattern in the resist. The energy source can be an electron beam, light source, or other suitable energy source.

The second patterned mask 130 includes an opening for forming a groove above the opening 125. The patterned mask 130 does not include a corresponding opening for the capacitor opening 127. This is because the etching of these openings has already been completed. If the capacitor opening was not completed in the previous step, as described above, then in step 35, the opening in the second patterned mask is provided so that the capacitor opening can be completed in the next process. Would have been formed.

In step 40, the second insulating layer 115
Form grooves 135 corresponding to the patterned and formed conductive runners and capacitors. Second insulating layer 1
15 can be patterned using conventional etching techniques. During etching, an etch stop layer 110 is used to define an endpoint for this etching process. The openings are provided at the boundaries 136, 138 of the groove 135.
Contained within, or at least partially contained within.
Next, in step 45, the remaining portions of the mask layers 120, 130 are stripped using known techniques, and the partially completed integrated circuit is removed using conventional processes at step 47.
Washed in.

In step 50, the conductive layer 145 is
Blanket deposited above the insulating layer 115 and within the openings, grooves and capacitor openings 127. Next, portions of the conductive layer that are outside of the capacitor openings 127 and the grooves 135 and above or above the second insulating layer are removed, completing the interconnect. This can be accomplished using a conventional chemical mechanical polishing process. The conductive layer 145 is a conductive material such as tungsten, aluminum, copper, nickel, polysilicon, or any other conductive material suitable for use as a conductor and known to those skilled in the art.

By using this process, the capacitor 17 is formed when the dual damascene structure 175 is formed.
0 is formed. As a result, finger capacitors can be introduced into the process for forming dual damascene structures without additional processing steps such as lithography processes and etching. In this way, an increase in the manufacturing cost of the integrated circuit including the finger capacitor can be avoided.

In other embodiments, one or more layers may be formed prior to depositing conductive layer 145. FIG.
Shows an exemplary barrier layer 147. These layers can be barrier layers that prevent the transfer of moisture and contaminants between the conductive layer and surrounding layers.

For example, when the conductive layer 145 is made of copper, T
A barrier layer 147 comprising layers of a and TaN may be deposited on the second insulating layer 115 and in the openings and trenches before depositing the conductive layer. When the conductive layer 145 contains Al, (1) Ti, TiN or (2) Ti, TiN, T
A barrier layer 147 including the i layer can be used. Other materials for the barrier layer include WSi, TiW, Ta, TaN,
Ti, TiN, Cr, Cu, Au, WN, TaSiN,
Or WSiN. The barrier layer 147 also
It can also act as an adhesion layer and / or nucleation layer for the subsequently formed conductive layer. Further, Si ₃ N ₄ , Ta
A capping layer such as N, TiN, or TiW can be formed on top of the conductive layer.

FIG. 8 is a top view of an exemplary finger capacitor and dual damascene structure formed using the exemplary embodiment described above. Finger condenser 170
Are the first plate 171 and the second plate 172
Having. Interconnections between the capacitors and other parts of the integrated circuit have been omitted for clarity. Those skilled in the art will be able to integrate the capacitors within the integrated circuit as needed to complete the designed circuit.

Next, the integrated circuit is completed, if necessary, by adding additional metal levels that may include interconnects formed using the processes described above and conventional processes. Integrated circuits also include transistors and other components necessary for a particular integrated circuit design. The process for manufacturing integrated circuits containing these structures is:
1-3 Wolf, Silicon, Processesi
ng for the VLSI Era, (1986)
And this document is incorporated herein by reference.

9 to 15 illustrate another embodiment of the present invention. FIG. 9 is a flowchart, and FIGS. 10 to 15 are schematic diagrams illustrating successive stages of manufacturing an integrated circuit according to the flowchart shown in FIG.

In step 210, the first insulating layer 305
Is formed on the substrate 300. The first insulating layer 305 is
The same material as described above for the first insulating layer 105. Substrate 300 is the same material as described above for substrate 100. Further, the upper surface 301 of the substrate 300 does not have to be flat. In this case, the first insulating layer 305
For example, it can be planarized using well-known chemical mechanical polishing (CMP).

In step 215, the etch stop layer 3
10 is formed above the first insulating layer 305 or in direct contact with the first insulating layer 305. In other embodiments,
One or more layers may be formed between the etch stop layer 310 and the first insulating layer 305. Etch stop layer 310 is a material such as the materials described above for first etch stop layer 110.

In step 220, the second insulating layer 315
Is formed above or in direct contact with the etch stop layer 315. Second insulating layer 3
15 may be formed of the same materials and processes used to form the first insulating layer 305. Step 22
5, the first patterned mask 320 is the insulating layer 31
5 or on the insulating layer 315. First patterned mask 320 includes an opening corresponding to a runner or groove to be formed. Further, the first patterned mask 320 has an opening 327 (hereinafter, referred to as a capacitor) for a capacitor.
(Referred to as "condenser opening"). Reticle 390 has a pattern that is transferred to the first patterned mask so that capacitor opening 327 can be formed when opening 325 is formed.

In step 230, the capacitor opening 3
27 and groove 335 are opened in second insulating layer 315. Groove 335 may be formed using conventional etching techniques. During the etch, the etch stop layer 310
Is used to define the endpoint for this etching process. Next, in step 235, the second patterned mask 330 is
0 or above the first patterned mask 320. The second patterned mask is formed such that the openings in the mask correspond to the vias or contact openings (hereinafter referred to as "openings") to be formed. further,
The second patterned mask includes openings corresponding to the capacitor openings to be formed. Portions of the second patterned mask may be formed on walls 350, 351 of groove 335. As a result, the walls 350, 351 will not be further etched while forming the openings. In contrast, portions of the second patterned layer will not be formed on the walls of the capacitor openings.

In step 240, the etch stop layer 3
10 and first insulating layer 305 are patterned to form openings 325 corresponding to the interconnects between the layers to be formed. The capacitor opening 327 is also formed by etching the etch stop layer 310 and the first insulating layer 305. Openings 325 and capacitor openings 327 may be formed by etching at least two different layers using a conventional etching technique or combination of techniques.

The openings 325 are formed by the walls 350, 3 of the groove 335.
Contained within, or at least partially contained within, the boundary defined by 51. Next, in step 245, the remaining portions of the mask layers 320, 330 are stripped using known techniques, and the partially completed integrated circuit is cleaned in step 247 using conventional processes.

In step 250, conductive layer 345 is a blanket deposited over second insulating layer 315 and within openings, trenches and capacitor openings. Next, portions of the conductive layer that are outside the capacitor openings 327 and the grooves 335 and that are above or above the second insulating layer 315 are removed. This can be accomplished using a conventional chemical mechanical polishing process. The conductive layer 345 is suitable for being used as a conductive material or a conductive material such as tungsten, aluminum, copper, nickel, or polysilicon;
Other conductive materials known to those skilled in the art.

In another embodiment, one or more layers may be formed prior to depositing conductive layer 345, as described above with respect to the first embodiment shown in FIG. These one or more layers may be referred to as a liner.
Further, a capping layer may be provided as described above with respect to the first embodiment. Next, the integrated circuit is completed, if necessary, by adding additional metal levels, which may include interconnects formed using the processes described above and conventional processes.

Although three layers are shown, including a first insulating layer, an etch stop layer, and a second insulating layer, the number of these layers may be reduced. For example, the capacitor and dual damascene structure may be formed in one or two insulating layers where openings for the capacitor and dual damascene structure are formed substantially simultaneously.

[0034]

As described above, according to the present invention, it is possible to provide a sidewall capacitor in an integrated circuit including a double damascene structure.

Although the invention has been described with reference to illustrative embodiments, the invention is not limited to these embodiments. Rather, the appended claims are to be construed to include other modifications and embodiments of the invention that may be made by those skilled in the art without departing from the true spirit and scope of the invention.

[0036]

According to the present invention, it is possible to provide a sidewall capacitor in an integrated circuit including a double damascene structure.

[Brief description of the drawings]

FIG. 1 shows a flowchart illustrating a process for manufacturing an integrated circuit according to an exemplary embodiment of the present invention.

2 is a schematic diagram of an integrated circuit in a continuous manufacturing stage using the process of FIG. 1;

FIG. 3 is a schematic diagram of an integrated circuit at successive manufacturing stages using the process of FIG. 1;

FIG. 4 is a schematic diagram of an integrated circuit at successive manufacturing stages using the process of FIG. 1;

FIG. 5 is a schematic diagram of an integrated circuit at successive manufacturing stages using the process of FIG. 1;

FIG. 6 is a schematic diagram of an integrated circuit at successive manufacturing stages using the process of FIG. 1;

FIG. 7 is a schematic diagram of an integrated circuit at successive manufacturing stages using the process of FIG. 1;

FIG. 8 is a top view of a partially fabricated integrated circuit having finger capacitors and a dual damascene structure fabricated according to the process of FIG. 1.

FIG. 9 is a flowchart illustrating a process for manufacturing an integrated circuit according to another exemplary embodiment of the present invention.

10 schematically illustrates an integrated circuit at successive manufacturing stages using the process of FIG. 9;

11 schematically illustrates an integrated circuit in a continuous manufacturing stage using the process of FIG. 9;

12 schematically illustrates an integrated circuit in a continuous manufacturing stage using the process of FIG. 9;

FIG. 13 is a schematic diagram of an integrated circuit at successive manufacturing stages using the process of FIG. 9;

FIG. 14 is a schematic diagram of an integrated circuit at successive manufacturing stages using the process of FIG. 9;

FIG. 15 is a schematic diagram of an integrated circuit at successive manufacturing stages using the process of FIG. 9;

[Explanation of symbols]

 90 reticle 95 reticle 100 substrate 101 top surface 105 first insulating layer 110 etch stop layer 115 second insulating layer 120 first patterned mask 125 via or contact opening 127 capacitor opening 130 second patterned mask 135 groove 136 Boundary 138 Boundary 145 Conductive layer 147 Barrier layer 170 Capacitor 175 Double damascene structure

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Silesh Chitti Peddi United States 18104 Pennsylvania, Allentown, Lenape Trail 308 F-term (reference) 5F033 GG01 GG02 HH04 HH07 HH08 HH11 HH13 HH17 HH18 HH19 HH21 HH23 HH28 HH31H JJ04 JJ07 JJ08 JJ11 JJ13 JJ17 JJ18 JJ19 JJ21 JJ23 JJ28 JJ31 JJ32 JJ33 JJ34 KK01 KK07 MM01 MM02 MM12 MM13 NN06 NN07 QQ08 QQ09 QQ10 QQ24 QQ25 QQ37 QQ14 RRRR RR01 RR04 RR01 RR04 RR04 AC15 EZ20

Claims (10)

[Claims] 1. A capacitor formed in a layer having a layer, a double damascene structure formed in the layer, and a first conductor and a second conductor formed in the layer. An integrated circuit comprising: 2. The integrated circuit according to claim 1, wherein said layers include at least two layers. 3. The integrated circuit according to claim 1, wherein the first conductor and the second conductor are not formed above or below each other. 4. The integrated circuit of claim 1, wherein the layer includes a stop layer, the double damascene structure includes at least a groove and a via, and a bottom of the groove includes at least a top of the stop layer. 5. The integrated circuit according to claim 4, wherein said stop layer is formed between said first conductor and said second conductor. 6. The integrated circuit according to claim 1, wherein the layer includes a stop layer, and the stop layer is formed between the first conductor and the second conductor. 7. The integrated circuit according to claim 6, wherein said first conductor and said second conductor are in contact with said stop layer. 8. The integrated circuit according to claim 7, wherein said first conductor includes a liner and a conductive material. 9. The integrated circuit according to claim 1, wherein the first conductor is a first plate of the capacitor, and the second conductor forms a second plate of the capacitor. 10. The integrated circuit according to claim 1, wherein said layer is formed on said substrate, and said layer further comprises a substrate not formed at least between said first conductor and said substrate.