JP2002032355A - Microcomputer - Google Patents

Abstract

(57) [Problem] To provide a microcomputer capable of increasing the number of operation modes without increasing the number of terminals. SOLUTION: At least two internal circuits C1 to C5 formed on one chip 1 and at least one terminal P
A microcomputer including INA to PINE, and first and second selectors 7 for selecting the internal circuits C1 to C5 connected to the terminals PINA to PINE in response to externally supplied signals SMOD and INIT. , 9
A microcomputer provided with:

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer.

[0002]

2. Description of the Related Art In recent years, a microcontroller equipped with a CPU has been required to have a high function and multi-function and a small circuit scale. The demand for is increasing.

[0003] Here, as described above, the single-chip microcomputer is highly functional and multifunctional, so that the required number of terminals exceeds the number of terminals that can be actually formed on the chip. There's a problem.

That is, first, in a conventional single-chip microcomputer, terminals are formed so as to correspond one-to-one to a mode (operation mode) adopted by the microcomputer. It is necessary to provide a large number of terminals correspondingly.

If a sufficient number of terminals are not provided, in an external bus mode in which terminals formed on the chip are connected to an external bus, free space for connecting internal circuits included in the chip is provided. There is a problem that the number of terminals is reduced.

On the other hand, if one terminal is shared for various uses, the number of modes for switching the terminal for each use increases, but the mode is determined by a signal supplied from the outside to the terminal. Therefore, the number of required terminals increases with the increase in the number of modes as described above,
As a result, there has been a problem that the number of terminals to which the internal circuit can be connected cannot be increased.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has as its object to provide a microcomputer capable of increasing the number of operation modes without adding terminals. .

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to form a CPU, at least two internal circuits,
A microcomputer including at least one terminal, wherein the microcomputer includes a selection unit that selects an internal circuit connected to the terminal in accordance with a signal supplied from the outside. Achieved. According to such a means, terminals can be easily shared in the operation by a plurality of internal circuits. Further, here, a plurality of terminals are provided, and the selecting means connects a predetermined terminal to the CPU irrespective of a signal supplied from the outside. The need for configuration changes is avoided.

Further, if the selection means always selects an internal circuit specified in advance for each terminal as an internal circuit connected to each terminal, data output from the internal circuit is always output from the same terminal. can do.

[0010] The semiconductor device further includes a plurality of first internal circuits operable by a first clock signal, and a second internal circuit operable by a second clock signal having a higher frequency than the first clock signal. The means may sequentially select the plurality of first internal circuits as internal circuits connected to the terminal according to the second clock signal. Data can be sequentially output via the terminal, and depending on the frequency of the second clock signal, data can be output from all the first internal circuits in the operation cycle.

[0011] The selecting means may select an internal circuit and a CPU as connection targets of terminals according to a signal supplied from the outside.
Are alternately selected at a predetermined cycle, the CPU
While executing the program, the data of the internal circuit can be output to the outside via the terminal.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts. [First Embodiment] FIG. 1 is a diagram showing a configuration of a microcomputer according to a first embodiment of the present invention. As shown in FIG. 1, the microcomputer according to the first embodiment is formed on one chip 1 and includes a mode switching circuit 3
, A CPU (Central Processing Unit) 5, and a first selector 7
, A second selector 9, a clock signal generation circuit 11,
A mode terminal MOD, a mode switching terminal MDCG, a clock signal input terminal TCK, a first terminal PINA, a second terminal PINB, a third terminal PINC, and a fourth terminal PI
ND, a fifth terminal PINE, a first peripheral circuit C1, a second peripheral circuit C2, a third peripheral circuit C3, a fourth peripheral circuit C4, and a fifth peripheral circuit C5.

The first to fifth peripheral circuits C1 to C
5 is an internal circuit formed inside the chip 1,
Since it is provided around the CPU 5, it is described as "peripheral circuit" in the description of the embodiment of the present invention.

In the above, the mode switching circuit 3 is connected to the mode terminal MOD and the mode switching terminal MDCG,
The CPU 5 is connected to the mode switching terminal MDCG. The first selector 7 and the second selector 9 are connected to the mode switching circuit 3, the peripheral circuits C1 to C5, and the CPU 5.

The clock signal generation circuit 11 has an input terminal connected to the clock signal input terminal TCK and an output terminal connected to the peripheral circuits C1 to C5 and the CPU 5.

Further, the first terminal PINA is connected to the first selector 7, and the second terminal PINB to the fifth terminal PINE are connected.
These four terminals are connected to the second selector 9.

The operation of the microcomputer shown in FIG. 1 having the above configuration will be described below with reference to FIGS. 2 and 3. In FIG. 2, numbers 1 to 122 are serial numbers assigned to actual pins provided on the chip 1, the first pin corresponds to a mode switching terminal MDCG, and the second pin is a mode terminal. MOD. Further, as an example, the second terminal PINB is configured by 24 pins from No. 3 to No. 26, and the third terminal PINC to the fifth terminal PINE and the first terminal P
Configure INA.

First, the microcomputer according to the first embodiment is provided with arbitrary peripheral circuits C1 to C1 according to the user's intention.
A user mode (peripheral mode) for connecting C5 to the first to fifth terminals PINA to PINE, and a storage device in which the second to fifth terminals PINB to PINE are placed outside the chip 1 via an external bus (FIG. (Not shown), and a program stored in the storage device is connected to the CPU 5.
And an external bus mode executed by

Here, the microcomputer according to the first embodiment operates in the user mode when a high-level (logical level 1) signal SMOD is supplied to the mode terminal MOD from the outside, and the microcomputer operates from the outside. A low-level (logic level 0) signal SMO is applied to the mode terminal MOD.
When D is supplied, it operates in the external bus mode.

In the user mode, the selection operation by the first selector 7 and the second selector 9 connects the second terminal PINB to the first peripheral circuit C1, as shown in FIG. The third terminal PINC is connected to the second peripheral circuit PINC, the fourth terminal PIND is connected to the third peripheral circuit C3, the fifth terminal PINE is connected to the fourth peripheral circuit C4, and the first terminal PINA is connected to the fifth peripheral circuit PINC. Each is connected to the circuit C5.

As shown in FIG. 3B, when a high-level pulse signal 13 is supplied to the mode switching terminal MDCG from the outside, the microcomputer can be switched to the mode. Then, as shown in FIG. 3A, when the signal SMOD transitions from the high level (H) to the low level (L) at the time T1, the mode switching circuit 3 sets the selection signal indicating the external bus mode which has been initialized in advance. MODSEL is supplied to the first and second selectors 7, 9, and the microcomputer shifts to the external bus mode.

FIG. 2 shows the external bus mode.
There are five modes from the first to the fifth external bus modes BM1 to BM5 shown in FIG. 2B to FIG. 2F, and the fifth external bus mode shown in FIG. BM
The case where 5 is initialized is shown as an example.

That is, the fifth external bus mode BM5
As shown in FIG. 2 (f), the first selector 7 selectively connects the first terminal PINA to the fifth peripheral circuit C5 in accordance with the supplied selection signal MODSEL, and Is the supplied selection signal MODSEL
By selectively connecting the four terminals from the second terminal PINB to the fifth terminal PINE to the CPU 5 in accordance with
The CPU 5 is connected to an external storage device (not shown) via an external bus.

After the time T1 shown in FIG. 3, the signal I supplied to the mode switching terminal MDCG is
At the so-called rising timing when the NIT transitions from the low level to the high level, as shown in FIG. 3C, the mode switching circuit 3 sequentially outputs the signals MODSEL designating new external bus modes BM1 to BM5 to the first selector 7. And to the second selector 9.

As a result, the microcomputer is switched to the first external bus mode BM1 at time T2, and thereafter at time T3, T4, T5, T6, T7.
Sequentially the second external bus mode BM2, the third external bus mode B
M3, the fourth external bus mode BM4, the fifth external bus mode BM5, and the first external bus mode BM1 are switched.

Here, in the first external bus mode BM1, as shown in FIG.
Selectively connects the first terminal PINA to the first peripheral circuit C1 in accordance with the supplied selection signal MODSEL, and the second selector 9 supplies the supplied selection signal MODSEL.
By selectively connecting the four terminals from the second terminal PINB to the fifth terminal PINE to the CPU 5 in accordance with
The CPU 5 is connected to an external storage device (not shown) via an external bus.

Similarly, in the second to fourth external bus modes BM2 to BM4, FIG. 2C to FIG.
, The second selector 9 connects the four terminals from the second terminal PINB to the fifth terminal PINE to the CPU 5 in any mode, and the first selector 7 sequentially connects the first terminal PINA to the first terminal PINA. The second peripheral circuit C2 is connected to the fourth peripheral circuit C4.

In the microcomputer shown in FIG. 1, the clock signal generation circuit 11 generates internal clock signals CLKA and CLKB according to the external clock signal CLK supplied to the clock signal input terminal TCK. The internal clock signal CLKA is supplied to the first to fifth peripheral circuits C1 to C5, respectively.
The KB is supplied to the CPU 5. The first to fifth peripheral circuits C1 to C5 supply the supplied internal clock signal CLKA.
, And the CPU 5 operates according to the supplied internal clock signal CLKB.

As described above, according to the microcomputer of the first embodiment, by changing the logic level of the signal INIT supplied to the mode switching terminal MDCG, the mode switching circuit 3 switches the operation mode, Since the selector 7 connects the first terminal PINA to a peripheral circuit selected according to each of the switched operation modes, the number of operation modes can be increased without increasing the number of terminals.

As shown in FIG. 2, according to the microcomputer of the first embodiment, in the external bus mode, the second terminal PINB is independent of the mode type.
Since the fifth terminal PINE is connected to the external bus, the effect that it is not necessary to change the setting of the interface with the external storage device in the external bus mode can be obtained. [Second Embodiment] A microcomputer according to a second embodiment has a configuration similar to that of the microcomputer according to the first embodiment shown in FIG. 1, but the functions of the first selector 7 and the second selector 9 are different. It is different. Hereinafter, differences from the microcomputer according to the first embodiment will be described.

FIG. 4 is a diagram for explaining the operation of the microcomputer according to the second embodiment. As shown in FIG. 4B, the first selector 7 according to the second embodiment
Is the first terminal PI in the first external bus mode BM1.
By selectively connecting the NA to the CPU 5, the CPU
5 is connected to an external storage device (not shown) via an external bus.

At this time, the second selector 9 selectively connects the second terminal PINB to the first peripheral circuit C1, and connects the third terminal PINC to the fifth terminal PINE to the CPU 5 in the same manner as the first terminal PINA. Connect to

Further, in the second external bus mode BM2, as shown in FIG. 4C, the first selector 7 selectively connects the first terminal PINA to the CPU 5, and the second selector 9 sets the first terminal PINA. The three terminals PINC are selectively connected to the second peripheral circuit C2, and the second terminal PINB and the fourth terminal P
The IND and the fifth terminal PINE are connected to the CPU 5 in the same manner as the first terminal PINA.

In the third external bus mode BM3, the first selector 7 selectively connects the first terminal PINA to the CPU 5 as shown in FIG.
The second selector 9 selectively connects the fourth terminal PIND to the third peripheral circuit C3, and connects the second terminal PINB and the third terminal PIN.
C and the fifth terminal PINE are connected to the CPU 5 in the same manner as the first terminal PINA.

Then, in the fourth external bus mode BM4, as shown in FIG. 4E, the first selector 7 selectively connects the first terminal PINA to the CPU 5, and the second selector 9 selects the first terminal PINA. The five terminals PINE are selectively connected to the fourth peripheral circuit C4, and the four terminals from the second terminal PINB to the fifth terminal PINE are connected to the CPU 5 similarly to the first terminal PINA.

As described above, according to the microcomputer according to the second embodiment of the present invention, the first selector 7 and the second selector 9 have their respective terminals irrespective of the user mode or the external bus mode. Is connected to a peripheral circuit specified in advance so as to correspond to the terminal on a one-to-one basis, so that characteristics (AC characteristics) in setup, hold, and the like in each peripheral circuit can be ensured regardless of the mode. [Third Embodiment] A microcomputer according to a third embodiment has a configuration similar to that of the microcomputer according to the first embodiment shown in FIG. 1, but the signal INIT shown in FIG. Instead, the internal clock signal CLKB generated in the clock signal generation circuit 11 shown in FIG. 1 is supplied to the mode switching circuit 3. Hereinafter, differences from the microcomputer according to the first embodiment will be described.

FIG. 5 is a timing chart showing the operation of the microcomputer according to the third embodiment of the present invention. As shown in FIG. 5A, the internal clock signal CLKA generated by the clock signal generation circuit 11 is a periodic signal in which one cycle is the time from time T1 to time T6. As shown, one cycle of internal clock signal CLKB is the time from time T1 to time T2, and the cycle is one cycle as compared with internal clock signal CLKA.
/ 5.

Here, the mode switching circuit 3 determines the so-called rising timing of the supplied internal clock signal CLKB, that is, the times T1, T2, T3, T4, T5, T
At 6, the external bus mode is switched by switching the logic level of the selection signal MODSEL supplied to the first and second selectors 7, 9.

Then, as shown in FIG. 5 (c), the first selector 7 connects the first terminal PINA to the first peripheral circuit C1 at time T1 according to the supplied selection signal MODSEL. At T2, it is connected to the second peripheral circuit C2, at time T3, it is connected to the third peripheral circuit C3,
At time T4, connection to the fourth peripheral circuit C4 occurs, and at time T5
At the fifth peripheral circuit C5.

As a result, the data of the first peripheral circuit C1 shown in FIG. 5 (e) is supplied to the first terminal PINA from time T1 to time T2, and similarly from time T2 to time T3. 5A shows that the data of the second peripheral circuit C2 shown in FIG. 5F and the data of the third peripheral circuit C3 shown in FIG. During the time T5, the data of the fourth peripheral circuit C4 shown in FIG. 5H is used, and between the time T5 and the time T6, the data of the fifth peripheral circuit C5 shown in FIG. Each is supplied to the first terminal PINA.

In the above, as shown in FIG. 5D, the second selector 9 connects four terminals from the second terminal PINB to the fifth terminal PINE to the CPU 5.

As described above, according to the microcomputer of the third embodiment of the present invention, during the event occurrence timing (time T1 and time T6) of the peripheral circuit, that is, during one cycle in the operation of the peripheral circuit, the first Since data from the peripheral circuit C1 to the fifth peripheral circuit C5 can be sequentially output to the outside from the first terminal PINA by time division, the data from the first peripheral circuit C1 to the fifth peripheral circuit C5
Two circuits can be used simultaneously through one terminal. [Fourth Embodiment] A microcomputer according to a fourth embodiment has a configuration similar to that of the microcomputer according to the first embodiment shown in FIG. 1, but the signal INIT shown in FIG. Instead, the external clock signal CLK is supplied to the mode switching terminal MDCG, and the function of the first and second selectors 7 and 9 is different. Hereinafter, differences from the microcomputer according to the first embodiment will be described.

FIG. 6 is a timing chart showing the operation of the microcomputer according to the fourth embodiment of the present invention. As shown in FIG. 6A, the external clock signal CLK is a periodic signal having one cycle from time T1 to time T2, and the mode switching circuit is operated in accordance with the rising timing of the external clock signal CLK. 3 switches modes at times T1, T2, T3, T4, T5, T6, and T7.

At this time, the first selector 7 selects the selection signal MODSE generated in response to the external clock signal CLK.
6B, the first terminal PINA is connected to the CPU from time T1 to time T2, as shown in FIG.
5 from time T2 to time T3, the first terminal PINA is connected to the first peripheral circuit C1,
Between the time 3 and the time T4, the first terminal PIN is again
A is connected to the CPU 5, and the first terminal PINA is again connected to the first peripheral circuit C1 from time T4 to time T5.

Then, similarly, the first terminal PINA is alternately connected to the CPU 5 and the first peripheral circuit C1 corresponding to one cycle of the external clock signal CLK shown in FIG. 5A.

As shown in FIG. 6 (c), the second selector 9 operates in response to a selection signal MODSEL generated in response to the external clock signal CLK during a period from time T1 to time T2. Connect the second terminal PINB to CPU5
And between the time T2 and the time T3, the second terminal PINB is connected to the second peripheral circuit C2.
From the second terminal PINB to the time T4.
Is connected to the CPU 5, and between the time T4 and the time T5, the second terminal PINB is again connected to the second peripheral circuit C2.

Then, similarly, the second terminal PINB is alternately connected to the CPU 5 and the second peripheral circuit C2 corresponding to one cycle of the external clock signal CLK shown in FIG. 5A.

Further, as shown in FIGS. 6 (d) to 6 (f), the second selector 9 changes the time from time T1 in response to the selection signal MODSEL generated in response to the external clock signal CLK. The third terminal PINC to the fifth terminal PINE are connected to the CPU 5 until time T2, and the third terminal PIN is connected between time T2 and time T3.
C is connected to the third peripheral circuit C3, the fourth terminal PIND is connected to the fourth peripheral circuit C4, and the fifth terminal PINE is connected to the fifth peripheral circuit C5. During the period from time T3 to time T4, the third terminal PINC to the fifth terminal PINE are again connected to the CPU.
5 between time T4 and time T5, the third terminal PINC is again connected to the third peripheral circuit C3, the fourth terminal PIND is connected to the fourth peripheral circuit C4, and the fifth terminal PINE is connected to the fifth peripheral circuit C5. Connect to

Similarly, the third terminal PINC to the fifth terminal PINE are alternately connected to the CPU 5 and the corresponding peripheral circuit corresponding to each cycle of the external clock signal CLK shown in FIG. I do.

As described above, according to the microcomputer according to the fourth embodiment of the present invention, the first and second selectors 7 and 9 respectively operate in each cycle of the external clock signal CLK shown in FIG. Accordingly, since the terminal is connected to the CPU 5 and the corresponding peripheral circuit, the data of the peripheral circuit can be output to the outside while the CPU 5 executes the program stored in the external storage device.

Therefore, control of the peripheral circuit according to the execution result of the program stored in the external storage device can be easily realized.

Further, the first and second selectors 7 and 9 according to the fourth embodiment set each terminal to one with respect to the terminal regardless of whether the mode is the user mode or the external bus mode. Since connection is made to peripheral circuits specified in advance so as to correspond to one-to-one, characteristics (AC characteristics) in setup, hold, and the like in each peripheral circuit can be ensured regardless of the mode. [Fifth Embodiment] FIG. 7 is a diagram showing a configuration of a microcomputer system according to a fifth embodiment of the present invention.
As shown in FIG. 7, a microcomputer system 20 according to the fifth embodiment includes a microcomputer 1
5, the selector 16, the external storage device 17, and the terminal 1
8, 19, a display and keyboard 21, an external storage interface 23, a communication connector 25, a microphone 27, and a speaker 29. The microcomputer 15 includes a mode terminal MOD, a mode switching terminal MDCG, and first to fifth terminals PINA to PINE.

The terminal 18 is connected to the mode terminal MOD, the terminal 19 is connected to the mode switching terminal MDCG, and the selector 16 is connected to the mode terminal MOD, the mode switching terminal MDCG, and the first to fifth terminals PINA to PINE. The external storage device 17 is connected to the selector 16.

The display and keyboard 21, the external storage interface 23, the communication connector 25, the microphone 27 and the speaker 29 are all connected to the selector 16.

In the microcomputer system 20 having the above-described configuration according to the fifth embodiment of the present invention, the operation of the selector 16 is organized as shown in Table 1 below.

[0056]

[Table 1] In Table 1, “SIO” is the serial I / O
(Input / output buffer).

In the user mode in which a high-level signal SMOD having a logic level of 1 is supplied to the terminal 18, as shown in Table 1, the selector 16 outputs the supplied signal SMOD.
According to the MOD, the first terminal PINA is connected to the display and the keyboard 21, the second terminal PINB is connected to the external storage interface 23, the third terminal PINC is connected to the communication connector 25, and the fourth terminal PIND is connected to the microphone 27. Connection, and the fifth terminal PINE is connected to the speaker 29.

Thus, in the user mode, the display and keyboard 21, external storage interface 23, communication connector 25, microphone 27 and speaker 29
Can be controlled by the microcomputer 15, so that the user can use all the peripheral devices.

In the external bus mode in which the low-level signal SMOD having a logical level of 0 is supplied to the terminal 18, as shown in Table 1, in any case, the selector 16 switches from the second terminal PINB to the fifth terminal PINB. The four terminals up to PINE are connected to the external storage device 17.

Then, in the same manner as in the microcomputer according to the above-described embodiment, the selector 16 switches the mode in accordance with the signal supplied to the mode switching terminal MDCG via the terminal 19, as shown in Table 1. In the first external bus mode, the first terminal PINA is connected to the display and the keyboard 21.

Similarly, in the second external bus mode, the selector 16 connects the first terminal PINA to the external storage interface 23, and in the third external bus mode, the selector 16 connects the first terminal PINA to the communication connector 2.
Connect to 5. In the fourth external bus mode,
The selector 16 connects the first terminal PINA to the microphone 27, and in the fifth external bus mode, the selector 16 connects the first terminal PINA to the speaker 29.

Therefore, in the first to fifth external bus modes, the program stored in the external storage device 17 is read by the microcomputer 15 via the four terminals from the second terminal PINB to the fifth terminal PINE. Issued and executed.

As described above, according to the microcomputer system 20 of the fifth embodiment of the present invention, the display and keyboard 21, the external storage interface 23,
Peripheral devices such as the communication connector 25, the microphone 27, and the speaker 29 can be controlled by the microcomputer 15 executing a program stored in the external storage device 17. [Sixth Embodiment] In a sixth embodiment, a method of testing shipment of chips using the microcomputer according to the first and second embodiments will be described.

FIG. 8 is a flowchart showing a conventional chip shipping test method. As shown in FIG. 8, in the conventional chip shipping test method, first, n is set to 1 in step S1, and a reset sequence is executed in step S2. Here, the “reset sequence” means a series of necessary operations necessary to determine an operation mode to be tested.

Next, a shipping test of the n-th peripheral circuit is performed in step S3, and it is determined whether or not n is 5 in step S4. Here, if n is 5, the shipping test is ended, but if n is not 5, step S1 is executed.
Go to 0, n is incremented by 1 and step S
Return to 2.

As described above, conventionally, the reset sequence needs to be executed for every peripheral circuit to be subjected to the shipping test, so that there has been a problem that the test time becomes longer and the chip cost increases. .

Here, the first and second embodiments of the present invention are described.
According to the microcomputer according to the above, the mode can be easily changed by changing the logic level of the signal supplied to the mode switching terminal MDCG as described above. Can be easily accomplished.

Hereinafter, the chip shipping test method according to the sixth embodiment will be described with reference to the flowchart of FIG.

First, as shown in FIG. 9, step S1
, A reset sequence is executed. Next, in step S2, the first peripheral circuit is tested. Then, in step S3, the value of n is set to 2, and in step S3
4, the signal I supplied to the mode switching terminal MDCG
NIT is set to a high level for a predetermined period as shown in FIG.

Thus, as described in the first and second embodiments, mode switching circuit 3 switches the operation mode. Then, a shipping test of the n-th peripheral circuit is performed in step S5, and it is determined whether or not n is 5 in step S6. Here, when it is determined that n is 5, the chip shipping test is terminated, and when it is determined that n is not 5, the n is incremented by 1 and the process returns to step S4.

As described above, according to the chip shipping test method according to the sixth embodiment of the present invention, the mode switching terminal MDC
By changing the logic level of the signal supplied to G, the desired operation mode can be set and the peripheral circuit to be tested can be easily changed. , And as a result, the test time can be shortened and the chip cost can be reduced.

[0072]

As described above, according to the microcomputer of the present invention, the terminals can be easily shared in the operation by a plurality of internal circuits, so that the number of operation modes can be increased without increasing the number of terminals. it can.

If the selection means connects a predetermined terminal to the CPU irrespective of an externally supplied signal, it is necessary to change the setting between the CPU and an external device connected to the CPU. Therefore, construction of a system including a microcomputer can be facilitated.

If the selecting means always selects an internal circuit specified in advance for each terminal, the data output from the internal circuit can always be output from the same terminal. By holding, the reliability of the operation can be improved.

The selection means may sequentially select a plurality of first internal circuits as internal circuits connected to the terminals in accordance with the second clock signal having a higher frequency than the first clock signal. For example, during the operation cycle of the first internal circuit, the data of the plurality of first internal circuits can be sequentially output via the terminal, so that the plurality of first internal circuits can be used simultaneously.

Further, if the selection means alternately selects the internal circuit and the CPU at a predetermined cycle in accordance with a signal supplied from the outside, the CPU executes the program while executing the program by the CPU. Data can be output to the outside via the terminal, and control of the internal circuit according to the execution result of the program can be easily realized, so that the microcomputer can be sophisticated.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a microcomputer according to Embodiment 1 of the present invention.

FIG. 2 is a diagram illustrating the operation of the microcomputer shown in FIG.

FIG. 3 is a timing chart for explaining the operation of the microcomputer shown in FIG. 1;

FIG. 4 is a diagram illustrating an operation of a microcomputer according to Embodiment 2 of the present invention.

FIG. 5 is a timing chart showing the operation of the microcomputer according to Embodiment 3 of the present invention.

FIG. 6 is a timing chart showing an operation of the microcomputer according to Embodiment 4 of the present invention.

FIG. 7 is a diagram showing a configuration of a microcomputer system according to a fifth embodiment of the present invention.

FIG. 8 is a flowchart showing a conventional chip shipping test method.

FIG. 9 is a flowchart illustrating a chip shipping test method according to a sixth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 chip 3 mode switching circuit 5 CPU (central processing unit) 7 first selector 9 second selector 11 clock signal generation circuit 13 pulse signal 15 microcomputer 16 selector 17 external storage device 21 display and keyboard 23 external storage interface 25 communication connector 27 microphone 29 speaker MOD mode terminal MDCG mode switching terminal TCK clock signal input terminal PINA first terminal PINB second terminal PINC third terminal PIND fourth terminal PINE fifth terminal C1 first peripheral circuit C2 second peripheral circuit C3 third Peripheral circuit C4 Fourth peripheral circuit C5 Fifth peripheral circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yoshito Katano 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Akio Hara 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 No. 1 Fujitsu Limited F term (reference) 5B062 AA02 EE10 GG06 HH01

Claims (5)

[Claims] 1. A microcomputer formed on one chip and including a CPU, at least two internal circuits, and at least one terminal, wherein the microcomputer is connected to the terminal according to a signal supplied from the outside. A microcomputer comprising a selection unit for selecting the internal circuit. 2. The microcomputer according to claim 1, further comprising a plurality of said terminals, wherein said selection means connects said predetermined terminal to said CPU irrespective of a signal supplied from outside. 3. The apparatus according to claim 1, further comprising a plurality of said terminals, wherein said selecting means always selects said internal circuit specified for each of said terminals as said internal circuit connected to each of said terminals. Microcomputer. 4. A semiconductor device comprising: a plurality of first internal circuits operated by a first clock signal; and a second internal circuit operated by a second clock signal having a higher frequency than the first clock signal; 2. The microcomputer according to claim 1, wherein the selection unit sequentially selects the plurality of first internal circuits as the internal circuit connected to the terminal according to the second clock signal. 5. The apparatus according to claim 1, wherein the selection unit alternately selects the internal circuit and the CPU at a predetermined cycle as a connection target of the terminal according to the signal supplied from the outside. Microcomputer.