JP2002026879A - Data error correction system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data error correction system where turbo coding or convolution coding is selected by referring to a reception state when transmitting data and a receiver side conducts turbo decoding and Viterbi decoding so as to enhance the transmission efficiency. SOLUTION: When a reception state of a receiver side is excellent, a transmitter side users a non-recursive convolution coder 16 to apply convolution coding to transmission data, adds coding system information to the transmission data and the transmitter side transmits the resulting transmission data to a receiver side. The receiver sides uses, e.g., a turbo decoder to apply Viterbi decoding to the received data. Furthermore, when the reception state of the receiver side reaches a not excellent state, the receiver side informs the transmitter side about it, then the transmitter side uses a turbo coder 17 to apply turbo coding to the transmission data, adds coding system information to the transmission data and transmits the resulting data to the receiver side. The receiver side applies turbo decoding to the received data, sets number of repetitive times of turbo decoding to about 3-5 times when the reception state is comparatively excellent through the discrimination of the reception state or sets number of repetitive times of turbo decoding to about 10-20 times when the reception state is bad.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data error correction method and apparatus suitable for a data transmission system using, for example, an orthogonal frequency division multiplexing (OFDM) modulation system.

[0002]

2. Description of the Related Art In recent years, it has been considered to employ an orthogonal frequency division multiplex modulation system as a data transmission system such as a wireless LAN.

In this wireless LAN, generally, a constraint length K (= 7) and a coding rate of 1/2 to 3
A non-recursive convolutional encoder of / 4 encodes the convolutional code, interleaves it, and then, according to the modulation scheme,
The mapped data is serial-to-parallel converted, inverse fast Fourier-transformed every 64 symbols, and a guard interval of 12 symbols is further added to the converted data to generate data for a total of 86 OFDM symbols. The generated data is passed through a waveform shaping filter, quadrature-modulated, raised in frequency to a carrier frequency, amplified in high frequency, and transmitted from an antenna.

On the receiving side, the radio wave from the antenna is amplified by a low noise amplifier, the reception level is detected by an AGC amplifier, the carrier is removed by using an AFC circuit, demodulated, the guard interval is removed, and then 64 The received data is obtained by performing fast Fourier transform for each symbol, demapping the obtained symbol, deinterleaving, and decoding with a decoder that performs Viterbi decoding.

In order to improve the anti-selective fading characteristics, it has been proposed to use turbo decoding of turbo-coded data instead of convolutionally coded data in Viterbi decoding in 1999. Communications Society Conference B-5-55 "O using turbo code
Study on FDM Communication System ".

[0006]

However, in the above-mentioned conventional OFDM communication system, it is general to perform Viterbi decoding on transmission data encoded by a convolutional code.
Alternatively, by performing turbo decoding on the transmission data encoded by the turbo code with the number of repetitions being two or more,
The bit error rate BER can be reduced, and the bit error rate decreases as the number of repetitions increases. However, when turbo decoding is performed, the amount of calculation increases as compared with Viterbi decoding, and the memory capacity increases. However, there is an unsolved problem that the transmission efficiency is reduced because a large number is required.

Therefore, the present invention has been made in view of the above-mentioned unsolved problems of the conventional example, and it is possible to select between convolutional coding and turbo coding according to the state of transmission data. It is another object of the present invention to provide a data error correction device capable of improving transmission efficiency by selecting a calculation amount for turbo decoding according to a reception state.

Further, according to the present invention, it is possible to improve the transmission efficiency by judging the reception state on the reception side and changing the code length at the time of turbo coding when the reception state is deteriorating. Another object of the present invention is to provide a data error correction device capable of performing such a method.

[0009]

In order to achieve the above object, a data error correction apparatus according to the first aspect of the present invention encodes transmission data on a transmission side and transmits the encoded data. In the data error correction device, the transmitting side refers to the data receiving state of the receiving side to select either convolutional coding or turbo coding to perform coding, Encoding notifying means for notifying the encoding side selected by the encoding means to the receiving side, and the receiving side, on the receiving side, determining a transmission state based on the received data, and notifying the transmitting side of the determination result, Viterbi decoding means for Viterbi decoding the received data,
A turbo decoding unit that performs turbo decoding at a repetition number set according to the determination result of the transmission state determination unit; and one of a Viterbi decoding unit and a turbo decoding unit according to the encoding method notified by the encoding notification unit. And decoding selection means for selecting.

In the invention according to claim 1, the wireless LAN
Also, when transmitting data between the satellite and the ground station or between the ground stations, when transmitting transmission data from the transmission side to the reception side, referring to the reception state of the reception side, convolutional coding and turbo coding Any of the encodings is selected for encoding, and the selected encoding method is notified to the receiving side by the encoding notifying means.
On the receiving side, the transmission state determination means determines the transmission state based on, for example, a frame synchronization symbol included in the transmission data, and, when the encoding method notified by the encoding notifying means is convolutional coding, the Viterbi decoding means. And if it is turbo coding, a turbo decoding means is selected.

Therefore, when the transmission state is good, convolutional coding is selected on the transmitting side, and Viterbi decoding is selected on the receiving side by selecting Viterbi decoding means, thereby shortening the processing time and improving transmission efficiency. Let it. Also,
When the state of the received data is bad, the turbo decoding means is selected to improve the bit error rate by turbo decoding, but at this time, the number of times of turbo decoding is increased when the state of the received data is relatively good. Reduces the processing time as much as possible by reducing the number of turbo decoding repetitions, and increases the number of turbo decoding repetitions to reduce the bit error rate when the state of received data is poor.

According to a second aspect of the present invention, in the data error correction apparatus according to the first aspect, the data encoding unit determines a reception state by a reception state determination unit that determines a reception state on a reception side. Is good, convolutional coding is performed by a convolutional coder, and turbo coding is performed by a turbo coder when reception conditions are not good.

According to the second aspect of the present invention, the receiving state determining means determines the state of the received data on the receiving side, and when the receiving state is good, performs convolutional coding with a convolutional coder, thereby providing a code. When reception data is in poor condition, turbo encoding is performed by a turbo encoder to suppress a reduction in the bit error rate on the receiving side.

Further, in the data error correction device according to a third aspect of the present invention, in the second aspect of the invention, the turbo encoder changes the code length of the turbo code based on a determination result of a reception state determination unit. It is characterized by being constituted.

According to the third aspect of the present invention, when the receiving state on the receiving side is poor, the code length is changed by the turbo encoder on the transmitting side to reduce the retransmission data length at the time of a retransmission request. Improve transmission efficiency.

Further, in the data error correction apparatus according to a fourth aspect of the present invention, in the invention according to the second aspect, the turbo encoder has a code length of the turbo code when the result of the determination by the reception state determination means is a low reception level. Is encoded with a shorter length.

According to the fourth aspect of the present invention, when the reception state determination means determines that the reception state is not good and the turbo encoder is selected and the reception level is low, the code length of the turbo code length is reduced. By shortening the encoding, the frequency of retransmission requests when turbo decoding is performed on the receiving side is reduced.

Furthermore, the data error correction apparatus according to claim 5 is the data error correction apparatus according to any one of claims 1 to 4, wherein the turbo decoding of a small number of repetitions is performed when the determination result of the transmission state determination means is on the good side. It is characterized in that turbo decoding of a large number of repetitions is performed when the determination result of the transmission state determining means is on the bad side.

According to the fifth aspect of the present invention, when the result of determination by the transmission state determining means on the receiving side is good, that is, the bit error rate decreases in Viterbi decoding, but the bit error rate can be improved in turbo decoding, The number of repetitions is set to about 3 to 5, and when the reception condition is poor, the number of repetitions of turbo decoding is set to 10 to 20 to improve the bit error rate.

According to a sixth aspect of the present invention, in the data error correction apparatus according to any one of the first to fourth aspects, the turbo decoding means performs a small repetition when the result of the determination by the transmission state determining means is good. The turbo decoding of the number of times is performed, the turbo decoding of a large number of repetitions is performed when the determination result of the transmission state determination unit is on the bad side, and the turbo decoding of one time is performed when the determination result of the transmission state determination unit is bad. It is characterized in that the received data is discarded and a retransmission request is made to the transmitting side without performing or performing turbo decoding.

In the invention according to claim 6, in addition to the case of claim 5, when the result of the determination by the transmission state determination means is bad, one turbo decoding is performed or turbo decoding is performed. Without discarding the received data and making a request for retransmission to the transmitting side, unnecessary processing on the receiving side is omitted and transmission efficiency is improved.

Further, according to a seventh aspect of the present invention, in the data error correction apparatus according to any one of the first to sixth aspects, the convolutional encoding means performs convolutional encoding using a configuration of a turbo encoding means. It is characterized by being constituted.

In the invention according to claim 7, it is not necessary to separately provide two sets of convolutional coding means and turbo coding means on the transmitting side, and the configuration can be simplified.

Further, in the data error correction apparatus according to claim 8, in the invention according to any one of claims 1 to 7, the Viterbi decoding means is configured to perform Viterbi decoding using the configuration of turbo decoding means. It is characterized by having.

In the invention according to the eighth aspect, it is not necessary to separately provide two sets of Viterbi decoding means and turbo decoding means on the receiving side, and the configuration can be simplified.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing one embodiment of the present invention.

In the figure, reference numeral 1 denotes a data processing device, which performs data transmission via a wireless data transmission device 2 when the data processing device 1 performs data transmission with another data processing device.

The wireless data transmission device 2 includes an interface 3 for exchanging data with the data processing device 1.
A transmission circuit 4 and a reception circuit 5 connected to the interface 3; a switching circuit 7 for selecting the transmission circuit 4 and the reception circuit 5 and connecting to the antenna 6; And a controller 8 for controlling the switching circuit 8.

The transmission circuit 4 selects a convolutional coding process or a turbo coding process in accordance with the transmission state detected by the receiving circuit 5 and encodes the transmission data input from the interface 3. Error Correction (Forward Error Correction)
) And data encoded by the FEC coder 11 are OFDM (Orthogonal Frequency Divis
and an OFDM modulation circuit 12 for performing ion multiplexing.

Here, the FEC coder 11 transmits the transmission data I input from the interface 3 as shown in FIG.
A changeover switch 15 to which _F is input, a non-recursive convolutional encoder 16 connected to one output side of the changeover switch 15, and a turbo encoder 17 connected to the other output side
These are controlled based on a selection signal SL input from a controller 8 described later, and when the selection signal is a logical value “0”, the changeover switch 15 is switched to the non-recursive convolutional encoder 16 side. At the same time, the non-recursive convolutional encoder 16 is controlled to the operating state, and the transmission data I
_F is convolutionally coded and output, and when the selection signal SL has the logical value “1”, the changeover switch 15
7 and the turbo encoder 17 is controlled to the operating state, and the transmission data _IF is turbo-coded and output.

The non-recursive convolutional encoder 16
For example, as shown in FIG.
171) Code length R = 1/2 corresponding to code and constraint length K
Are composed of 7 non-recursive convolutional systematic encoders, and are provided with six-stage shift registers SR1 to SR6 to which transmission information is input.
, Transmission information I and shift registers SR2, SR3 and S
M where R5 and output is input to output the information bits I _F
an odd bit information bit adder AD1; and a mod2 parity bit adder AD2 that receives the transmission information I and the outputs of the shift registers SR1, SR2, SR3, and SR6 and outputs a parity bit P. and the parity bit P output from the information bits I _F and parity bit adder AD2 output from the information bit adder AD1 is outputted as the output code.

As shown in FIG. 4, the turbo encoder 17 supplies the transmission information I to an N-stage shift register 21 and stores the transmission information I in N-bit units. the information bits I _F1 to be the first
Is input directly to a recursive systematic convolutional coder (RSC) 22A, and after being interleaved by an interleaver 23, is stored in a shift register 24. The information bit _IF2 output from the shift register 24 is used as a second recursive The first and second recursive systematic convolutional encoders 22A and 22B are input to a systematic convolutional encoder (RSC) 22B.
Parity bits P ₁ and P ₂ output from the B is punctured by the puncturer 25, appended to the turbo code in the punctured parity bit P information bits I _F1 is formed.

Then, the first and second recursive tissue convolutions
Each of the encoders 22A and 22B has a coding rate R = 1 /
2, the generator matrices h1 = 7 and h2 = 5 are set and shown in FIG.
Information bit I_F1Or I_F2Adder to which is input
27 and a two-stage to which the addition output of the adder 27 is input.
A shift register 28 and an input of the shift register 28
And an adder 29 for adding the bit and the final stage output bit.
The first stage output bit and the last stage output of the shift register 28
The power bit is input to the adder 29, and the
Tibit P₁ Or P_Two Is configured to output
You. In the first recursive systematic convolutional encoder 22A,
Input information bit I_F1Is output as is, but the second
Of the recursive systematic convolutional encoder 22B of
Bit I _F2Is not output and the parity bit P_Two Only
Output.

The puncturer 25 punctures the parity bits P ₁ and P ₂ output from the first and second recursive systematic convolutional encoders 22A and 22B according to, for example, a puncturing pattern shown below.

[0036]

(Equation 1)

Therefore, the output from the puncture 25
The parity bit P to be used is the parity bit P at each time point.
₁ And P_Two To p₁ (0), p₁ (1), p₁ (2), p₁ (3), …… and
And p _Two (0), p_Two (1), p_Two (2), p_Two (3), ……
And p_Two (0), p₁ (1), p_Two (2), p₁ (3), ...

In the OFDM modulation circuit 12, as shown in FIG. 6, the input coded data is mapped by the mapping circuit 31 in accordance with the modulation method, and the processed data is subjected to serial / parallel conversion and inversely converted. The signal is supplied to a fast Fourier transform (IFFT) circuit 32, and inverse fast Fourier transformed every 64 symbols. The converted data is supplied to the coding method information adding circuit 33, and 1-bit coding method information CI indicating which of the turbo code and the convolutional code has been performed by the FEC coder 11 is added, for example, at the end of the synchronization symbol. Then, the signal is supplied to a guard interval adding circuit 34, and a guard interval of 12 symbols is further added.
(Orthogonal Frequency Division Multiplexing) Symbol data is generated. The generated data is subjected to waveform shaping by a waveform shaping filter 35 and then orthogonal frequency multiplex modulation (BPSK-OFD) by an orthogonal frequency multiplex modulation circuit 36.
M), then the frequency is raised to the carrier frequency by the multiplier 37, and then the high frequency is amplified by the high frequency amplifier 38 and output to the switching circuit 7.

On the other hand, the receiving circuit 5 receives the radio wave received by the antenna 6 via the switching circuit 7 and
The OFDM demodulation circuit 41 includes an OFDM demodulation circuit 41 for demodulating the data, and an FEC decoder 42 for performing either turbo decoding or Viterbi decoding of the data demodulated by the OFDM demodulation circuit 41.

In the OFDM demodulation circuit 41, as shown in FIG. 7, the radio wave received by the antenna 6 is amplified by the low noise amplifier 43 through the switching circuit 7, multiplied by the carrier by the multiplier 44, and then multiplied by the AGC amplifier 45. Detect the reception level,
The carrier is removed by the demodulation circuit 46 using the AFC circuit 47 and then demodulated. The guard interval removal circuit 48 applies an appropriate window to the baseband signal to remove the guard interval. Next, after detecting the coding system information CI by the coding system information detecting circuit 49 and removing it, the fast Fourier transform (FFT) circuit 50 performs fast Fourier transform for every 64 symbols. The demapping circuit 51 performs demapping, deinterleaving, and parallel / serial conversion before supplying the data to the FEC decoder 42.

The FEC decoder 42 is shown in FIG.
And a turbo decoder. That is,
V-decoder sends the transformed data after fast Fourier transform
Bit I_F Information data affected by the communication channel
L_C y and parity bit P are affected on the communication channel.
Digit parity data L_C y 'and parity data
L_C For y ', the puncture 25 of the transmission circuit 4
The corresponding bit of the punctured parity bit P
Any dummy bit in the position (usually treated as -1)
A data separation circuit 60 for inserting and outputting
Information data L output from separation circuit 60_C y is one
On the input side, the likelihood information L on the other input side^{(1 )} initial value of (u)
(= 0) or likelihood information L described later⁽¹⁾ (u) is input
A first soft output decoder 61 and from this soft output decoder 61
Output first likelihood information L _E ⁽¹⁾ (u ＾)
Interleaver 62 to be interleaved and this interleaver 6
Output L of 2⁽²⁾ (u) and output from the data separation circuit 60
Parity data L_Cy 'and soft output recovery
And the likelihood output from the soft-output decoder 63
Information L_E ⁽²⁾ (u ＾) is deinterleaved and the likelihood information L
⁽¹⁾ (u) to be supplied to the first soft output decoder 61.
And an interleaver 64. Where the first
The soft output decoder 61 outputs a first decoded output L⁽¹⁾ (u ＾)
And the second soft-output decoder 63 outputs the second
Second decoding output L⁽²⁾ (u ＾) Can be output.

As described above, in the turbo decoder, the first likelihood information L _E ⁽¹⁾ (u () is decoded by the first soft output decoder 61, and is interleaved by the interleaver 62. information and parity bit information L _C y 'and the second soft-output decoder 63 based on the second round of likelihood information L _E ^{(1) (u}
^) Decoding the works of likelihood information which was deinterleaved in deinterleaver 64 L ⁽¹⁾ (u) and the third likelihood in the first soft-output decoder 31 based on the data L _C y Decoding the degree information L _E ⁽³⁾ (u ＾), repeating this up to the i-th time (for example, i = 5), performing turbo decoding, and finally decoding data at the end of the i-th decoding is L ^(I) (u
＾).

Here, as an algorithm of iterative soft decision decoding used for turbo decoding, MAP (Maximum
a posteriori Probability) Algorithm, Log-M
An AP algorithm, a SOVA (Soft Output Viterbi) algorithm, or the like can be applied. In these cases, received data is stored in a memory for every N bits, and 5 to 20 times.
It is necessary to repeatedly perform soft decision decoding about once, and it takes time to decode.

Then, in the turbo decoder of FIG. 8, a trellis diagram of the soft output decoder 61 is represented as shown in FIG.

That is, the likelihood information L
If for calculating _E a ^{(1) (u ^),} if MAP algorithm, for all data in accordance with the trellis diagram of FIG. 9, the k-th data of the input data _{L C y Y K = (y} K
^I, y If the _K ^P) below (1) conditional probability P represented by formula (Y _K | computes u _K), storing it in the memory.

[0046]

(Equation 2)

Here, u _K is the estimated value of the k-th information bit i, and x _K ^P is the estimated value of the k-th parity bit.

Therefore, when turbo decoding is performed according to the trellis diagram shown in FIG. 10, the probability function γ _K of each branch shown in FIG.
(I, j) is represented by the following equation (3).

[0049]

(Equation 3)

In FIG. 10, the probability function α _K (s) (s =
For example, α _K (0), which is one of 0, 1, 2, 3), can be expressed by the following equation (4).

Α _K (0) = α _K−1 (0) · γ _K (0,0) + α _K−1 (1) · γ _K (1,1) (4)

In the case of turbo decoding, the value of the probability function α _K (s) is obtained from the first data to the last N-th data for each data Y _K , and is further referred to as another probability function β _K (s). The values now need to be calculated backwards from the last Nth data to the first data. One of the reasons why turbo decoding takes time is here. In addition, since all the calculated probability functions α _K (s) and β _K (s) need to be stored in the memory, the memory capacity is also required.

Incidentally, the probability function γ in turbo decoding
_{Since K} (i, j) is an amount corresponding to a metric in Viterbi decoding, a surviving path can be obtained in FIG. 11 by determining a path metric M _K (s) as in the following equation (5). Viterbi decoding can be performed.

M _K (s) = M _K−1 (s ′) + max [γ _K (i, j), γ _K (i ′, j ′)] (5)

That is, the estimation result of the output corresponding to the surviving path is stored in the memory together with the surviving path, and traceback is performed when the path disappears, thereby enabling Viterbi decoding. As a place for storing the output estimation result in that case, it is possible to use a memory for storing the probability function β _K (s) during turbo decoding.

Therefore, γ _K (i, j) and γ _K (i ′,
j ′), it is possible to perform Viterbi decoding only by adding a small circuit such as a comparator for selecting a larger one, and in this Viterbi decoding, decoding is performed sequentially. Therefore, the decoding time can be shortened.

Whether the turbo decoder performs turbo decoding or Viterbi decoding selects Viterbi decoding when the state of the received signal is good, and performs turbo decoding when the state of the received signal is bad to perform the bit error rate ( BER).

When the transmission data is input from the data processing device 1 to the interface 3, the controller 8 switches the switching circuit 7 to the transmission circuit 4 side, and the high-frequency amplifier 38
Is transmitted to the antenna 6 via the switching circuit 7 and transmitted. When there is no transmission data from the data processing device 1, the switching circuit 7 is switched to the receiving circuit 5 side, and the radio wave received by the antenna 6 is switched to the switching circuit. 7 through the low-noise amplifier 43
To supply.

Here, at the time of reception when the switching circuit 7 is switched to the receiving circuit 5 side, a reception level detection signal RD detected by the AGC amplifier 45 is input, and the reception level detection signal RD is input to the controller 8. Thus, based on the reception level detection signal RD, the information bit transmission rate is B (bit / s), the noise power density per 1 Hz of the transmission path is N ₀ (dBm / Hz), and the reception power is C (dB).
m), a reception power-to-noise power density ratio E _B / N ₀ = C / BN ₀ per information bit is calculated, and according to the value of the reception power-to-noise power density ratio E _B / N _0. An FEC decoder 42 transmits a coding designation signal CC for designating whether to perform Viterbi coding or turbo coding to a transmission source, and to a reception power-to-noise power density ratio according to E _B / N _0. The number of repetitions for performing turbo decoding is set, and the encoding scheme information detection circuit 4 of the OFDM demodulation circuit 41 is set.
9, the coding system information CI detected at step 9 is input, and when this is a logical value "1", the FEC decoder 42 outputs a selection signal SR of a logical value "1" for selecting turbo decoding,
When the coding method information is a logical value “0”, the FEC decoder 42 outputs a selection signal SR of a logical value “0” for performing Viterbi decoding.

In order to detect the transmission state, in a diversity reception system in which an adaptive array antenna composed of, for example, a linear array antenna of about 4 to 8 elements or a planar array antenna is used as the receiving antenna 11, a received signal is detected. The transmission state is good when the level of the detection signal exceeds a set threshold based on the level of the detection signal when selecting the gain and array of the AGC circuit using the training signal added to the head of the AGC circuit. Is determined, and when it is equal to or less than the set threshold, it is determined that the transmission state is defective.

The controller 8 executes the switching control process shown in FIG. 12, switches the interface 3 when there is a transmission request from the data processing device 1, and when the control signal SL is "0". convolutional encoding of the transmission data I _F in a non-recursive convolutional encoder 16, when the control signal SL is "1", the transmission data I _F by turbo encoding in the turbo encoder 17, and transmits.

In the switching control process of FIG. 12, first, in step S1, it is determined whether or not there is a transmission request in the data processing device 1. If there is no transmission request, the process proceeds to step S2, where the interface 3 and the Switching circuit 7 to receiving circuit 5
Side, and then proceeds to step S3 to determine whether received data has been received. If no received data has been received, the process returns to step S1, and if data has been received, the process proceeds to step S4.

In this step S4, the FEC coder 11
It is determined whether or not an encoding selection signal SL for determining which of the convolutional encoding and the turbo encoding is to be selected. If the encoding selection signal SL is received, the process proceeds to step S5, and The process proceeds to step S6 after storing the encoded selection signal SL in a predetermined storage area of the storage device, and directly proceeds to step S6 when the encoded selection signal SL has not been received.

In step S6, it is determined whether or not the reception completion response data has been received. When the reception completion response data has been received, it is determined that the reception has been normally performed on the receiving side, and the following step will be described. The flow shifts to S23, and if not the reception completion response data, the flow shifts to step S7,
It is determined whether the request is a retransmission request. If the request is a retransmission request, the process proceeds to step S23 described below. If the request is not a retransmission request, it is determined that the data is received data and step S8 is performed.
Move to

In this step S8, the AGC amplifier 45
In reading the received level detection signal RD detected, it calculates the received power to noise power density ratio E _B / N ₀ of one bit of information per based on the received level detection signal RD, and then proceeds to step S9, calculates It is determined whether or not the received power-to-noise power density ratio E _B / N ₀ is equal to or greater than a threshold TH ₁ (for example, 7 dB) for determining whether or not a preset reception state is good, and E _B / N ₀ ≧ when TH is _1, it is determined that the reception state is good, the process proceeds to step S10, transmits the encoded selection signal SL having the logic value "0" circuit instructing Viterbi coding on the data transmission side transition from instructs to output with the response data of the received data from the 4 to the step S12, step S it is determined that the reception state is not good when an E _B / N ₀ <TH ₁
11, the transmission circuit 4 outputs an encoding selection signal LS having a logical value “1” for instructing the data transmitting side to perform turbo encoding.
And instructs to output together with the response data of the received data, and then proceeds to step S12.

In step S12, the coding system information CI detected by the coding system information detecting circuit 49 is read, and it is determined whether or not this is a logical value "0".
If it is "0", the flow shifts to step S13, and FE
After outputting the selection signal SR of the logical value “0” instructing the Viterbi decoding to the C decoder 42, the process shifts to step S14 to determine whether or not the receiving process of demodulating and decoding the received data is completed. When the receiving process is not completed, the process waits until the receiving process is completed. When the receiving process is completed, it is determined in step S15 whether the reception of the received data is normally completed. The process proceeds to step S16, in which an instruction to transmit a reception completion response is issued, and then returns to step S1. If a bit error occurs and reception is not completed normally, the process proceeds to step S17 to transmit a retransmission request. After giving the instruction, the process returns to step S1.

The result of the determination in step S12 is C
When I = “1”, the process proceeds to step S18,
The reception condition is not good, but E_B / N₀ Is relatively good
Threshold value TH for determining whether or not_Two (For example, 2 dB)
It is determined whether or not the _B / N₀ ≧ TH_Two Is
The reception condition is not so bad
Then, the process shifts to step S19 where the FEC decoder 42
Select signal S of logical value "1" indicating turbo decoding
Set R and the number of repetitions of turbo decoding to 3 to 5 times
Outputs the repetition count setting information RP to the FEC decoder 42.
Then, the process proceeds to step S14.

The result of the determination in step S18 is E _B
If / N ₀ <TH ₂ , the process proceeds to step S20, where the reception state is not good, but a threshold value TH ₃ (for example, 1d) for determining whether E _B / N ₀ is on the relatively good side or not.
B) It is determined whether or not it is equal to or greater than, and if E _B / N ₀ ≧ TH _3, it is determined that the reception state is considerably deteriorated, and the flow shifts to step S21 to execute the FEC decoder 42
, And a repetition number setting information RP for setting the number of repetitions of turbo decoding to 10 to 20 by the FEC decoder 4.
After that, the process proceeds to step S14.

Further, the determination result of step S20 is
_{When B} / N ₀ <TH ₃ , the process proceeds to step S22, where the selection signal S of the logical value “1” indicating turbo decoding is set.
R and the number-of-repetitions setting information RP in which the number of times of turbo decoding is set to 1 are output to the FEC decoder 42, and then the process proceeds to step S14.

On the other hand, if the result of the determination in step S1 is that there is a transmission request in the data processing apparatus 1 or if a reception completion response or a retransmission request is to be transmitted in the reception processing, the flow shifts to step S23, where the interface 3 and the switching circuit are switched. 7 is the transmission circuit 4
Then, the process proceeds to step S24 to determine whether or not there is a reception completion response transmission instruction. If there is a reception completion response transmission instruction, the flow proceeds to step S25 to transmit a reception completion response to the data transmission side. Before returning to step S1,
If there is no reception completion response transmission instruction, the flow shifts to step S26 to determine whether or not there is a retransmission request transmission instruction. If there is a retransmission request transmission instruction, the flow shifts to step S27 to transmit a retransmission request to the data transmission side. Then, the process returns to the step S1, and when there is no instruction to transmit the retransmission request, the process shifts to the step S28.

In step S28, it is determined whether or not the encoding selection signal SL has been received. If the encoding selection signal SL has been received, the process proceeds to step S29, where the FEC coder 11 Encoding selection signal SL
To the FEC coder 11 and then to step S31. If the encoding selection signal SL has not been received, the operation proceeds to step S30 to output the encoding selection signal SL having the logical value "0" to the FEC coder 11. And then step S3
Move to 1.

In this step S31, the transmission data of a predetermined code length is output to the FF coder 11, and the coding method information CI is output to the OFDM modulation circuit 12. Then, the process proceeds to step S32, where the predetermined code length (for example, 1000
It is determined whether the transmission of one frame of transmission data set to (0 bit) has been completed. If the transmission has not been completed, the process waits until the transmission has been completed. If the transmission has been completed, the process returns to step S1.

The thresholds TH ₁ , TH _2, and TH ₃ for determining the reception state in steps S 9, S 18, and S 20 were set by simulating various reception states for Viterbi decoding and turbo decoding. As shown in the figure, when Viterbi decoding is performed when the received power-to-noise power density ratio E _B / N ₀ is plotted on the horizontal axis and the bit error rate BER is plotted on the vertical axis, as shown by a characteristic curve LV, E
_{When B} / N ₀ is less than 7 dB, the bit error rate B
Although ER is not close to 10 ^-5 , E _B / N ₀ is 7
Above dB, the bit error rate BER becomes a small value close to 10 ^-5 , so that the received data can be successfully decoded by Viterbi decoding.

On the other hand, as for the turbo decoding, when the code length (interleaver length) of the turbo code is 10000 bits and the number of repetitions RP of the turbo decoding is ₁ , as shown by a characteristic curve LT1, called waterfall phenomenon peculiar to turbo decoding that a little bit error rate BER at the change will vary extremely in E _B / N ₀ is not conspicuous, E _B / N ₀ is turned 5.5db Is the bit error rate BE at 7 dB in Viterbi decoding.
Without reaching the R, but it is impossible to improve the bit error rate BER, when the repeat count RP turbo decoding is three times, as shown by the characteristic curve LT _3, together with the waterfall phenomenon appears remarkably, E _B / N
_{When 0} becomes 2 dB, the bit error rate BER at the time of 7 dB in Viterbi decoding becomes substantially equal, and it is possible to satisfactorily decode received data by turbo decoding. Similarly, when the number of repetitions RP of the turbo decoding is set to 5, the bit error rate BER at 7 dB in Viterbi decoding becomes approximately equal to around 2 dB. Further, when the number of repetitions RP of turbo decoding reaches 10, E _B / N ₀ becomes 0.5
The waterfall phenomenon appears at the point of exceeding dB, and 2
In the vicinity of dB, the bit error rate BER at 7 dB in Viterbi decoding becomes substantially equal. Note that the characteristic curve LB in FIG. 13 shows the case where the BPSK (Binary Phase Shift Keying) modulation method is used, and in this case, the bit error rate BE
R cannot be reduced.

For this reason, according to the simulation results of FIG. 10, when the reception level where E _B / N ₀ is 7 dB or more is high, Viterbi decoding is performed to shorten the operation processing time.
When E _B / N ₀ is equal to or more than 2 dB and less than 7 dB, decoding in which the bit error rate BER is improved by turbo decoding in which the number of repetitions is 3 to 5 is performed, and E _B / N 0
_{When 0} is equal to or more than 1 dB and less than 2 dB, decoding is performed with the bit error rate BER improved by turbo decoding with the number of repetitions being 10 to 20 times. When E _B / N ₀ is equal to or less than 1 dB, turbo decoding is performed. Since the value of the bit error rate BER is not so different regardless of whether the number of repetitions is 1 or 10 or more, the repetition number RP of turbo decoding is set to 1. Then, as a result of performing the turbo decoding for the set number of repetitions, if there is a bit error in one code length, retransmission of data of the corresponding code length is requested.

Here, in the processing of FIG. 12, the processing of steps S9 to S11 corresponds to the reception state determination means, the processing of step S12 corresponds to the selection means, and the processing of step S13 and the turbo decoder of the FEC decoder 12 A part corresponds to the Viterbi decoding means, and steps S18 and S20
Corresponds to the transmission state determination means, and is performed in step S19,
The processing of S21 and S22 and the turbo decoder of the FEC decoder correspond to turbo decoding means.

Next, the operation of the above embodiment will be described.

Now, it is assumed that, for example, two data processing devices 1 are provided, and data can be transmitted / received by the wireless data transmission device 2 connected thereto. In this state, if there is transmission data to be transmitted from one data processing device 1 to the other data processing device 1, the transmission data is output to the interface 3 so that the controller 8 determines that the request is a transmission request. Then, the switching circuit 7 is switched to the transmission circuit 4 (step S23).
Next, it is determined whether or not the coding selection signal SL has been received (step S28). Since the coding selection signal SL has not been received, the coding selection signal SL having the logical value “0” is output to the FEC coder 11 (step S30). ).

Therefore, in the FEC coder 11, the changeover switch 15 can be switched to the non-recursive convolutional encoder 16 side. Thereafter, the transmission data I _F of a predetermined code length is input to the FEC coder 11, the coding method information CI of a logical value "0" to the OFDM modulator 12 is input. Thus, it supplied encoded convolutional transmission data I _F is convolutional encoder 16 to OFDN modulation circuit 12.

In the OFDM modulation circuit 12, the coded data is mapped by the mapping circuit 31 in accordance with the modulation method, and the processed data is serial-parallel-converted and supplied to the inverse fast Fourier transform circuit 32.
The inverse fast Fourier transform is performed for every four symbols, and this transformed data is supplied to the encoding method information adding circuit 33, and the FEC
For example, coding method information of a logical value "0" indicating that convolutional coding has been performed by the coder 11 is added to the end of a synchronization symbol, for example, and then supplied to a guard interval addition circuit 34 to further add a guard interval of 12 symbols. Thus, a total of 86 OFDM symbol data are generated. The generated data is subjected to waveform shaping by a waveform shaping filter 35, and then subjected to orthogonal frequency multiplex modulation (BPSK-OFDM) by an orthogonal frequency multiplexing and modulation circuit 36. , And is output to the switching circuit 7 and transmitted from the antenna 6 to the wireless data transmission device 2 of another data processing device 1.

In the wireless data transmission device 2 of the other data processing device 1, when the transmission data is received by the antenna 6, it is supplied to the reception circuit 5 via the switching circuit 7, and the reception signal is amplified by the low noise amplifier 43. After multiplying the carrier by the multiplier 44, the reception level is detected by the AGC amplifier 45, the carrier is removed by the demodulation circuit 46 using the AFC circuit 47, and then demodulated. The guard interval removal circuit 48 removes the guard interval. . Next, after the coding method information is detected by the coding method information detection circuit 49 and then removed, the fast Fourier transform (FFT) circuit 50 detects the coding method information.
After fast Fourier transform for each symbol, the obtained symbols are de-mapped by a demapping circuit 51, and
The data is deinterleaved and further subjected to parallel / serial conversion before being supplied to the FEC decoder 42.

At this time, since the reception level signal RD detected by the AGC amplifier 45 is input to the controller 8, a reception power-to-noise power density ratio E _B / N ₀ is calculated based on the reception level signal RD. (step S8), and the calculated E _B / N ₀ is equal to or a predetermined threshold value TH ₁ or more, the reception state is a good, when it is E _B / N ₀ ≧ TH _1, the logical value " By setting an encoding selection signal SL of "0" and instructing the data transmission side to perform Viterbi encoding,
Next, the encoding system information detecting circuit 49 detects the encoding system information CI having the logical value “0”, so that the FEC decoder 42
, A selection signal SR having a logical value “0” is output.
The aforementioned Viterbi decoding is performed by the FEC decoder 42.
As described above, when the transmission state is good, the convolutional encoding process is performed on the transmission side, thereby enabling high-speed data transmission, and using the turbo decoder on the reception side instead of turbo decoding. Since Viterbi decoding is performed, sufficient error correction can be performed while simplifying the arithmetic processing and shortening the decoding time.

When the reception processing of the transmission data of the predetermined code length is completed, it is determined whether or not the reception has been completed normally (step S15). When the reception has been completed normally, an instruction to transmit a reception completion response is issued. (Step S16) If a bit error has occurred and reception has not been completed normally, an instruction to transmit a retransmission request is issued (Step S17).
Therefore, the process proceeds from step S1 to step S23, and when transmitting the reception completion response, the process proceeds to step S25.
Then, when the reception completion response and the encoding selection signal SL are transmitted to the data transmission side and the retransmission request is transmitted, the retransmission request and the encoding selection signal SL are transmitted to the data transmission side.

Therefore, when the data transmission side receives the encoding selection signal SL, it stores this encoding selection signal SL (step S5), so that when transmitting the next transmission data of a predetermined code length, the encoding When the selection signal SL is output to the FEC coder 11 and the reception state of the other party is deteriorating, the encoding selection signal SL of the logical value “1” notified from the data reception side is obtained. Instead of the coding, turbo coding using a turbo encoder 17 is performed, and by adding coding method information CI having a logical value “1” indicating that the turbo coding has been performed, turbo coding is performed on the data receiving side. Decoding is performed.

At this time, on the data receiving side, when the received power-to-noise power density ratio E _B / N ₀ is equal to or greater than the second threshold TH ₂ , the number of repetitions RP of turbo decoding is set to 3 to 5 times. As a result (step S19), turbo decoding with an improved bit error rate BER can be performed in a relatively short processing time, and transmission efficiency can be improved.

However, the received power-to-noise power density ratio E _B / N ₀ is less than the second threshold TH ₂ and the third threshold T
When at H ₃ or more, it is judged that reception is quite poor, the repeat count RP turbo decoding 10-20
Hit error rate BE with a relatively long processing time
Turbo decoding with improved R can be performed.

Further, the reception power to noise power density ratio E _B /
When N ₀ is less than the third threshold TH ₃ , the reception state is worse, and even if turbo decoding is performed, the bit error rate BE
Since it is determined that the improvement of R cannot be expected, it is determined whether or not the received data is normally received only by performing the turbo decoding once, so that a bit error is detected in most cases. , A retransmission request is made.

As described above, in the first embodiment, convolution coding is performed at the start of data transmission, transmission data is transmitted to the data reception side, and when the data reception state on the reception side is good, the logical Since the data selection side is notified of the encoding selection signal SL having the value “0” at the time of completion of reception or at the time of a retransmission request, the data transmission side continuously performs convolutional coding and a code indicating that the convolutional coding has been performed. Transmission data to which the conversion scheme information CI is added, and
By performing Viterbi decoding, it is possible to shorten the processing time on both the transmitting side and the receiving side and improve transmission efficiency.

On the other hand, if the reception power-to-noise power density ratio E _B / E ₀ at the reception side becomes a small value less than the _first threshold value TH ₁ and the data reception state is not good, the data reception side may cause By notifying the data transmission side of the encoding selection signal SL having the logical value “1” indicating the encoding, turbo encoding is performed on the data transmission side and encoding indicating that the turbo encoding has been performed. By transmitting the transmission data to which the method information CI is added, turbo decoding is performed on the receiving side. However, since the number of repetitions RP of turbo decoding at this time is set to the number of times corresponding to the change in the transmission state, Compared with the case where the worst transmission state is predicted and the number of repetitions of turbo decoding is fixed, the optimal number of repetitions according to the transmission state can be set, and the transmission efficiency can be improved. .

In the first embodiment, the FEC decoder 12 on the data receiving side uses one turbo decoder to perform Viterbi decoding and turbo decoding. The configuration can be simplified as compared with the case where a vessel is provided.

Next, a second embodiment of the present invention will be described with reference to FIGS.
FIG. 16 will be described.

In the second embodiment, when the reception state on the data receiving side deteriorates, the code length (interleaver length) of the turbo code at the time of turbo coding is changed to thereby increase the length of a long frame. The retransmission efficiency is improved as compared with the case where the minute is retransmitted.

That is, in the second embodiment, the control process of the controller 8 is performed as shown in FIG.
In the embodiment, step S in the process of FIG.
Between step 13 and step S14, a code length notification signal CS of a logical value "0" indicating a code length for encoding to the data transmitting side to a normal value is added at the time of reception completion response and retransmission request transmission. Step S35 is added, and the process proceeds from step S19 to step S35. After the process of step S21, the logical value "1" for instructing the data transmitting side to shorten the code length of the turbo code is added. Step S36 of adding the code length notification signal CS to the retransmission request transmission instruction is added.
2 to step S36, and accordingly, step S37 is added before step S6. In step S37, it is determined whether or not the code length notification signal CS has been received. When the code length notification signal CS is received, the process proceeds to step S38, where the code length notification signal CS is stored in the code length notification signal storage area of the storage device, and then proceeds to step S6. The process proceeds to step S6 and further to step S12
A step S39 for determining whether or not the code length information CL is a logical value “0” is provided between the step S18 and the step S18. When the result of the determination in the step S39 is CL = 0, the flow shifts to the step S40. Then, the code length at the time of turbo decoding is set to 10000 bits, and then the process proceeds to step S18. If CL = "1", the process proceeds to step S41 to set the code length at the time of turbo decoding to 2000 bits. After that, the process is changed to step S18.

On the other hand, even in the data transmission process, step S3
Before step 1, step S45 for determining whether or not the code length notification signal CS has the logical value “0” is added. When the determination result is the logical value “0”, the process proceeds to step S46 and the turbo After setting the code length of the code to a regular value of, for example, 10000 bits, the process proceeds to step S31. If the logical value is "1", the process proceeds to step S47 to set the code length of the turbo code to, for example, 1/5 of the normal bit number. Of 200
After setting to 0 bits, the process proceeds to step S31. In step S31, the transmission data having the set code length is input to the FEC coder 11, and the coding method information C
It is modified so that I and code length information CL are supplied to the coding method information adding circuit 33 and added to the transmission data.

According to the second embodiment, data transmission
Side performs convolutional coding, and the data receiving side performs Viterbi decoding.
The receiving condition is good and the data transmission side
And perform turbo decoding on the data receiving side.
Power to noise power density ratio E_B / E ₀ Is the second threshold value TH_Two that's all
If the reception condition is relatively good, the code length notification signal
CS is set to the logical value “0” to perform turbo coding
If the code length in the case is a long code length of 10,000 bits, for example,
By setting, on the data receiving side, turbo decoding
Data reception with improved bit error rate BER
Processing can be performed.

However, when turbo decoding is performed and the reception state in which the reception power-to-noise power density ratio E _B / E ₀ is less than the second threshold value TH ₂ is deteriorated, the code length notification signal CS becomes a logical value. Since it is set to “1” and the code length when performing turbo coding is limited to, for example, 2000 bits, the code length of one frame is reduced to 正規 of the normal and the frame error rate is reduced. Can be.

That is, the code length of one frame is set to 1000
As a result of actually measuring the relationship between the bit error rate BER and the frame error rate at 0, 8000, 4000, 2000, and 1000, as shown in FIG. 15, the frame error rate becomes smaller as the code length becomes smaller. In particular, when the bit error rate BER is 10 ^-5 , the code length is set to 100
When set to 0, the frame error rate is about 1 from 10 ^-1 to 10 ^-2 compared to when the code length is set to 10000.
Digit has improved. Therefore, when retransmission of transmission data and error correction are combined, transmission throughput is improved when transmission data is finely divided and transmitted with a small code length.

On the other hand, the relationship between the code length of the turbo code and the bit error rate BER is such that when the number of repetitions of turbo decoding is set to 10, the code length is set to 2000 as shown in FIG. Since the bit error rate BER is not so different between the case and the case of setting to 10000, when the transmission state is deteriorated, the code length is set to 2000 and the data is fragmented and transmitted. It is considered that the throughput is improved when combined with data retransmission.

For this reason, on the data transmission side, the transmission data calculates a check bit of the cyclic coding method every 2000 bits, and adds this check bit to the transmission data before performing turbo coding. , 2
Turbo decoding is performed for each value obtained by adding a tick bit to 000 bits, and thereafter, the received data is divided by a generator polynomial. If it is divisible, there is no error. If it is not divisible, there is a data error. By requesting retransmission of only a frame in which a frame exists, transmission throughput can be remarkably improved as compared with a case of requesting retransmission of a frame having a regular long code length.

In the second embodiment, the case where the code length of one regular frame is 10000 bits and the code length of one frame when the reception condition is deteriorated is 2000 has been described. Without being limited, these code lengths can be set arbitrarily.
In short, when performing turbo decoding, if the reception condition is relatively good, the error correction effect is exhibited as a large code length, and if the reception condition is deteriorated, a small code length is used, reducing the frequency of retransmission requests and reducing retransmission. What is necessary is just to improve the transmission throughput by reducing the data transmission time.

In the first and second embodiments,
Received power to noise power density ratio E_B / E ₀ Is the third threshold value TH
_Three When the value becomes smaller than
Although the description has been given of the case where
Received data without turbo decoding.
Discard the data and immediately request retransmission of data.
You may.

Further, in the first and second embodiments, the case has been described where the FEC decoder 42 on the receiving side performs Viterbi decoding and turbo decoding with a turbo decoder configuration. However, the present invention is not limited to this. Instead, a Viterbi decoder and a turbo decoder may be provided separately.

Furthermore, in the first and second embodiments, the case has been described where both the non-recursive convolutional encoder 16 and the turbo encoder 17 are provided in the FEC coder 11, but the present invention is not limited to this. Instead, the FEC coder 11 may perform both non-recursive convolutional coding and turbo coding by using the configuration of the turbo encoder 17 as shown in FIG.

That is, as shown in FIG. 17, the parity bit P output from the recursive convolutional encoder 22A is added to the configuration of the turbo encoder 17 in the first embodiment described above.
A selection circuit 26 for selecting any one of the parity bits P output from the puncturer 25 and ₁ is provided, and the recursive convolutional encoder 22A is configured as shown in FIG.

Here, when the encoding selection signal SL from the controller 8 has the logical value "0", the selection circuit 26 outputs the parity bit P ₁ output from the first recursive systematic convolutional encoder 22A. selected, which forms an information bit I _F added to the convolutional code, the selection signal S
When T is a logic value "1", it selects the parity bit P output from the puncturer 25, by adding this to the information bits I _F, turbo code is formed.

Also, the first recursive systematic convolutional encoder 2
As shown in FIG. 18, 2A is a code rate R = 1/2 corresponding to a (133,171) code used in a commonly used non-recursive systematic convolutional encoder and a constraint length K of 7 It consists of a recursive convolutional systematic code unit, the input-side adder AD1 of mod2 the information bits I _F is input, and the output-side adder AD2 of mod2 for outputting parity bits, to the output side of the input-side adder AD1 and a connection is 6-stage shift register SR1~SR6 was, and the parity bit P output from the information bits I _F1 and the output-side adder AD2 is input is output as the output code.

The input side adder AD1 has a shift register S
The outputs of R1, SR3, SR5 and SR6 are input via the switch circuits SW1 to SW4, and the output of the shift register SR2 is directly input to the output adder AD2.
The output of the input adder AD1 and the shift register SR
2 is directly input and the shift register SR
1, SR3 and SR6 output from switch circuits SW5 to S
It is input via W7.

Further, the output information bit _IF1 and parity bit P are input to switching circuits SL1 and SL2, respectively, and one output side t of these switching circuits SL1 and SL2.
1 is output as it is as an output code, and the other output side t
2 is output as an inverted output code via the inverters IN1 and IN2.

The switch circuits SW1 to SW7 are controlled by the encoding selection signal SL output from the controller 8, and the switching circuits SL1 and SL2 are connected to the input adder A.
Switching is controlled by the output of a comparator 75 that outputs a comparison signal SC1 having a logical value "1" when the transmission information I input to D1 matches the output of the input adder AD1.
Here, the switch circuit SW1 is turned off when the encoding selection signal SL has the logical value “0”, and turned on when the encoding selection signal SL has the logical value “1”.
7 is turned on when the encoding selection signal SL has a logical value "0", and turned off when the encoding selection signal SL has a logical value "1". The switching circuits SL1 and SL2 switch the switching signal SC2.
When 1 is a logical value "0", it is switched to one output t1, and when it is a logical "1", it is switched to the other output t2.

Therefore, when the encoding selection signal SL has the logical value "0", the outputs of the shift registers SR2, SR3, SR5 and SR6 are fed back to the input side adder AD1 to correspond to "133". Generation state polynomial of octal value “1011011” (= x ⁶
+ X ⁴ + x ³ + x + 1), and the output of the shift registers SR1, SR2, SR3, SR6 is feed-forwarded to the output side adder AD2, so that the octal value “171” corresponding to “171” is obtained. 1111001 ”(= x ⁶ + x
⁵ + x ⁴ + x ³ +1) to form a recursive systematic convolutional encoder having a coding rate R = 1/2 and a constraint length K = 7. On the other hand, the encoding selection signal S
When L is a logical value "1", the input adder AD1
The outputs of the shift registers SR1 and SR2 are fed back to the output adder AD2, and the outputs of the input adder AD1 and the shift register SR2 are feed-forwarded to the output adder AD2, whereby the recursive systematic convolutional encoders 22A and 22B shown in FIG. And a recursive systematic convolutional encoder having the same configuration as

Here, the input bit and the input side adder AD1
By comparing the output data encoded by the recursive systematic convolutional encoder 22A with the output data encoded by the non-recursive systematic convolutional encoder 16 shown in FIG. The reason why can be determined is as follows.

That is, the recursive systematic convolutional encoder 22
FIG. 19 shows a part of the initial state of the shift register and a part after the transition when the same data is input to A and the non-recursive systematic convolutional encoder 17 shown in FIG.

As apparent from FIG. 19, the input bits and the input side adder A are input by the recursive systematic convolutional encoder 22A.
When the sign of the output bit of D1 matches, the initial state is “0”, “1”, “6”, “7”, “8”, “9”,
“14”, “15”, “18”, “19”, “20”,
In these cases, the outputs of the recursive systematic convolutional encoder 22A and the non-recursive systematic convolutional encoder 70 match, and the other initial states are "26",
"27", "28", "29", "34", "35",
"36", "37", "42", "43", "44",
“45”, “48”, “49”, “54”, “55”,
Also in the case of "56", "57", "62", and "63", the outputs of the recursive systematic convolutional encoder 22A and the non-recursive systematic convolutional encoder 17 match.

On the other hand, if the sign of the input bit and the sign of the output bit of the input side adder AD1 do not match in the recursive systematic convolutional encoder 22A, the initial state is "2", "3",
“4”, “5”, “10”, “11”, “12”, “1”
3 "," 16 "," 17 "," 22 "," 23 "," 2 "
4 "and" 25 ". In these cases, the output of the recursive systematic convolutional encoder 22A and the output of the non-recursive systematic convolutional encoder 70 are inverted, and the other initial state is" 30 ". , “31”, “32”, “33”, “3”
8 "," 39 "," 40 "," 41 "," 46 "," 4 "
7 "," 50 "," 51 "," 52 "," 53 "," 5 "
Also, when "8", "59", "60", and "61" are represented, the output of the recursive systematic convolutional encoder 22A and the output of the non-recursive systematic convolutional encoder 17 are inverted.

Therefore, the recursive systematic convolutional encoder 2
When the sign of the input bit and the output bit of the input adder AD1 do not match at 2A, the output bit of the recursive systematic convolutional encoder 22A is supplied to the inverters IN1 and IN2 via the switching circuits SL1 and SL2 and inverted. By doing so, the same encoded output as that of the non-recursive systematic convolutional encoder 16 can be obtained using the turbo encoder 17.

Here, the case where the shift register constituting the recursive systematic convolutional encoder 22A for generating the turbo code is constituted by six stages has been described. However, the present invention is not limited to this, and the (m, n) code In order to obtain the (7, 5) code, a two-stage shift register similar to that shown in FIG. 5 may be used.

In the above embodiment, the FEC coder 11 punctures the parity bits P ₁ and P ₂ with the puncturer 25 and outputs the parity bits P ₁ and P _2.
Has been described that generates, is not limited thereto, may be transmitted by omitting the puncturer 25 aligns parity bits P ₁ and P ₂ alternately with the information bits I _F In this case, the insertion of the dummy bit into the parity data by the data separation circuit 30 in the FEC decoder 20 on the receiving side is omitted.

In the above embodiment, when the FEC coder 11 is used as a convolutional coder, the first
A case has been described in which the additional recursive convolutional parity bits P ₁ encoder 22A as the information bits I _F, by inserting the puncturer optionally adds parity bits punctured in the information bits I _F You may make it.

Furthermore, in the above-described embodiment, the case where the transmission state is determined based on the reception level detection signal in the receiving circuit 5 has been described. However, the present invention is not limited to this. Then, the receiving side performs Viterbi decoding on the receiving side, and determines that the transmission state is bad when there is a transmission data retransmission request from the receiving side or when there is a plurality of transmission data retransmission requests. The transmission data may be turbo-coded and transmitted, and turbo decoding may be performed on the receiving side.

Further, in the above embodiment, the case where the OFDM modulation circuit 12 is applied in the transmission circuit 4 and the OFDM demodulation circuit is applied in the reception circuit has been described.
The present invention is not limited to this, and a CDMA modulation / demodulation method or another modulation / demodulation method can be applied.

[0121]

As described above, according to the first aspect of the present invention, when the transmission state is good, convolutional coding is selected on the transmitting side, and Viterbi decoding means is selected on the receiving side. By performing the Viterbi decoding, the processing time is shortened to improve the transmission efficiency, and when the state of the received data is poor, the turbo decoding means is selected to improve the bit error rate by turbo decoding. ,
At this time, if the received data state is relatively good, the number of turbo decoding repetitions is reduced to minimize the processing time by reducing the number of turbo decoding repetitions. If the received data state is bad, the number of turbo decoding repetitions is reduced. And the bit error rate can be further improved.

According to the second aspect of the present invention, the receiving state determining means determines the state of the received data on the receiving side, and when the receiving state is good, performs convolutional coding with the convolutional encoder. Accordingly, it is possible to simplify coding and perform turbo coding with a turbo encoder when the state of received data is poor, thereby obtaining an effect that a reduction in the bit error rate on the receiving side can be suppressed.

Further, according to the third aspect of the present invention, when the receiving state on the receiving side is poor, the code length is changed by the turbo encoder on the transmitting side to reduce the retransmission data length at the time of a retransmission request. As a result, the effect that the transmission efficiency can be improved is obtained.

Further, according to the fourth aspect of the present invention, when the reception state determination means determines that the reception state is not good and the turbo encoder is selected and the reception level is low, the turbo code length By shortening the code length and performing encoding, it is possible to obtain an effect that the frequency of occurrence of retransmission requests when turbo decoding is performed on the receiving side can be reduced.

Further, according to the invention of claim 5, the bit error rate is reduced on the receiving side where the determination result of the transmission state determining means is good, ie, the bit error rate is reduced in Viterbi decoding, but the bit error rate is improved in turbo decoding. When you can
The number of repetitions is set to about 3 to 5 times, and when the reception condition is poor, the number of repetitions of turbo decoding is set to 10 to 2
The effect that the bit error rate can be improved as zero is obtained.

According to the invention of claim 6, when the result of the determination by the transmission state determining means is bad, one turbo decoding is performed or the turbo decoding is not performed.
By discarding the received data and requesting the transmission side to retransmit, there is an effect that unnecessary processing on the reception side can be omitted and the transmission efficiency can be improved.

Further, according to the seventh aspect of the present invention, it is not necessary to separately provide two sets of convolutional coding means and turbo coding means on the transmitting side, so that the structure can be simplified.

Further, according to the invention of claim 8, there is an advantage that the configuration can be simplified since it is not necessary to provide two sets of Viterbi decoding means and turbo decoding means separately on the receiving side.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of an FEC coder.

FIG. 3 is a block diagram showing a specific configuration of a non-recursive convolutional encoder.

FIG. 4 is a block diagram illustrating a specific configuration of a turbo encoder.

FIG. 5 is a block diagram showing a specific configuration of a recursive convolutional encoder of the turbo encoder.

FIG. 6 is a block diagram illustrating a specific example of an OFDM modulation circuit.

FIG. 7 is a block diagram illustrating a specific example of an OFDM demodulation circuit.

FIG. 8 is a block diagram illustrating a specific configuration of an FEC decoder.

FIG. 9 is an explanatory diagram showing a trellis diagram of the soft output decoder.

FIG. 10 is an explanatory diagram when turbo decoding is performed using a trellis diagram.

FIG. 11 is an explanatory diagram in the case of performing Viterbi decoding using a trellis diagram.

FIG. 12 is a flowchart illustrating an example of a control process performed by a controller.

FIG. 13 is a characteristic diagram showing a relationship between a received power to noise power density ratio and a bit error rate.

FIG. 14 is a flowchart illustrating an example of a control process performed by a controller according to the second embodiment of the present invention.

FIG. 15 is a characteristic diagram showing a relationship between a bit error rate and a frame error rate.

FIG. 16 is a characteristic diagram showing a relationship between a received power to noise power density ratio and a bit error rate.

FIG. 17 is a block diagram showing another specific configuration of the FEC coder.

FIG. 18 is a block diagram illustrating a specific configuration of a recursive convolutional encoder.

FIG. 19 is an explanatory diagram comparing output states of a recursive systematic convolutional encoder and a non-recursive systematic convolutional encoder.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 data processing device 2 wireless data transmission device 3 interface 4 transmission circuit 5 reception circuit 6 antenna 7 switching circuit 8 controller 11 FEC coder AD1 information bit adder AD2 parity bit adder SR1 to SR6 shift register 12 OFDM modulation circuit 13 mapping Circuit 15 Changeover switch 16 Non-recursive convolutional encoder 17 Turbo encoder 21 Shift register 22A, 22B Recursive convolutional encoder 23 Interleaver 24 Shift register 25 Puncturer 27 Adder 28 Shift register 29 Adder 33 Addition of coding method information Circuit 41 OFDM demodulation circuit 42 FEC decoder 49 Coding scheme information detection circuit 60 Data separation circuit 61 Soft output decoder 62 Interleaver 63 Soft output decoder 64 Deinterleaver 7 Recursive systematic convolutional encoder 75 comparator 26 selection circuits SL1, SL2 switching circuit SW1~SW7 switch circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03M 13/41 H03M 13/41 H04J 11/00 H04J 11/00 Z F term (Reference) 5B001 AA01 AA10 AB02 AC05 AD06 AE02 5J065 AA01 AB01 AC02 AD10 AE07 AF04 AG06 5K014 AA01 BA05 BA10 EA08 FA11 FA16 HA10 5K022 DD01 DD13 DD19 DD23 DD33

Claims (8)

[Claims] 1. A data error correction device for correcting a bit error of transmission data on a receiving side by encoding transmission data on a transmitting side and transmitting the data, wherein the transmitting side refers to a data reception state on the receiving side. A data encoding unit that performs encoding by selecting one of convolutional encoding and turbo encoding; and an encoding notifying unit that notifies the receiving side of the encoding selected by the data encoding unit. The transmission state determining means for determining the transmission state based on the received data and notifying the transmitting side of the determination result, the Viterbi decoding means for Viterbi decoding the received data, and setting according to the determination result of the transmission state determining means Turbo decoding means for performing turbo decoding with the number of repetitions to be performed, and selecting one of Viterbi decoding means and turbo decoding means according to the coding method notified by the coding notifying means. A data error correction device, comprising: 2. The data encoding means performs convolutional encoding by a convolutional encoder when the result of the judgment by the reception state judgment means for judging the reception state on the reception side is good. 2. The data error correction device according to claim 1, wherein a turbo encoder performs turbo encoding when not. 3. The data error correction device according to claim 2, wherein the turbo encoder is configured to change the code length of the turbo code based on the result of the determination by the reception state determining means. 4. The data error correction according to claim 2, wherein the turbo encoder performs encoding by shortening the code length of the turbo code when the result of the determination by the reception state determination means is low. apparatus. 5. The turbo decoding means performs turbo decoding for a small number of iterations when the result of the determination by the transmission state determination means is good, and performs the large repetition when the result of the determination by the transmission state determination means is bad. 5. The data error correction device according to claim 1, wherein the data error correction device is configured to perform turbo decoding the number of times. 6. The turbo decoding means performs turbo decoding for a small number of repetitions when the result of the determination by the transmission state determination means is good, and performs the large repetition when the result of the determination by the transmission state determination means is bad. When the turbo decoding is performed a number of times and the result of the determination by the transmission state determining unit is bad, the received data is discarded and a retransmission request is sent to the transmitting side without performing the turbo decoding once or without performing the turbo decoding. The data error correction device according to any one of claims 1 to 4, wherein: 7. The data error correction according to claim 1, wherein said convolutional coding means is configured to perform convolutional coding using a configuration of a turbo coding means. apparatus. 8. The data error correction device according to claim 1, wherein said Viterbi decoding means is configured to perform Viterbi decoding by utilizing a configuration of a turbo decoding means.