JP2002026188A - Manufacturing method for ball grid array semiconductor device - Google Patents
Manufacturing method for ball grid array semiconductor deviceInfo
- Publication number
- JP2002026188A JP2002026188A JP2000212202A JP2000212202A JP2002026188A JP 2002026188 A JP2002026188 A JP 2002026188A JP 2000212202 A JP2000212202 A JP 2000212202A JP 2000212202 A JP2000212202 A JP 2000212202A JP 2002026188 A JP2002026188 A JP 2002026188A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- ball
- solder
- manufacturing
- grid array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ボールグリッドア
レイ（ball grid array:以下、ＢＧＡと記す）型半導体
装置の製造方法に関し、特にボール下面の平坦性をよく
する製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a ball grid array (BGA) type semiconductor device, and more particularly to a method for improving the flatness of a lower surface of a ball.
【０００２】[0002]
【従来の技術】半導体装置が用いられる電子機器が小型
化・薄型化されたことにより、また半導体装置が多ピン
化されたことにより、半導体装置がＢＧＡ構造で提供さ
れる場合が多くなってきている。図７は、特開平９−２
２９６１号公報にて開示された従来のＢＧＡ型半導体装
置の断面図である。図７に示されるように、樹脂基板１
０１ｂ、表面配線１０１ｃ、裏面配線１０１ｄ、内層配
線１０１ｅを有し、基板を貫通して配線間を接続するス
ルーホール１０１ａが形成された印刷配線基板１０１の
表面は、半導体チップ１０２が搭載される領域と表面配
線１０１ｃのワイヤボンディング領域を除いて、ソルダ
レジスト１０５により覆われている。印刷配線基板１０
１上のダイパッド上に半導体チップ１０２をダイボンド
した後、半導体チップの電極パッドと表面配線１０１ｃ
間をボンディングワイヤ１０３にて接続する。半導体チ
ップ１０２およびボンディングワイヤはトランスファモ
ールド法により封止樹脂１０４にて封止される。また、
印刷配線基板１０１の裏面配線１０１ｄの半田ランド上
には外部端子となる半田ボール１０７が固着される。2. Description of the Related Art Due to the miniaturization and thinning of electronic devices in which semiconductor devices are used and the increase in the number of pins of semiconductor devices, semiconductor devices are often provided in a BGA structure. I have. FIG.
1 is a cross-sectional view of a conventional BGA type semiconductor device disclosed in Japanese Patent No. 2961. As shown in FIG.
01b, a front wiring 101c, a back wiring 101d, and an inner wiring 101e. A surface of the printed wiring board 101 in which a through hole 101a penetrating through the substrate and connecting the wirings is formed is a region where the semiconductor chip 102 is mounted. Except for the wire bonding region of the surface wiring 101c and the surface wiring 101c, it is covered with the solder resist 105. Printed wiring board 10
After the semiconductor chip 102 is die-bonded on the die pad on the semiconductor chip 102, the electrode pads of the semiconductor chip and the surface wiring 101c are formed.
The connection is made by a bonding wire 103. The semiconductor chip 102 and the bonding wires are sealed with a sealing resin 104 by a transfer molding method. Also,
Solder balls 107 serving as external terminals are fixed on the solder lands of the back wiring 101d of the printed wiring board 101.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来のＢＧＡ
型半導体装置では、樹脂基板と封止樹脂との熱膨張係数
が異なることにより、半導体装置に反りが生じやすい。
そのため、半田ボール下面の平坦性が悪化して、製品の
最終測定試験の際にテストソケットとの接触不良を起こ
したり、図８に示されるように、ＢＧＡ型半導体装置を
実装基板１１０上に搭載する際に、一部の半田ボールが
実装基板から浮き上がって、接続不良を起こしたりす
る。本発明の課題は、上述した従来技術の問題点を解決
することであって、その目的は、第１に、例え基板に反
りが生じるとがあってもその反りを吸収して半田ボール
下面の平坦性を維持できるようにすることであり、第２
に、基板処理を吸収するための処理が半田ボールの接触
事故を発生させることなく実行できるようにすることで
ある。The above-mentioned conventional BGA
In the type semiconductor device, the semiconductor device is likely to be warped due to a difference in thermal expansion coefficient between the resin substrate and the sealing resin.
As a result, the flatness of the lower surface of the solder ball deteriorates, causing a contact failure with the test socket at the time of the final measurement test of the product, or mounting the BGA type semiconductor device on the mounting substrate 110 as shown in FIG. In such a case, some of the solder balls float up from the mounting board, causing a connection failure. An object of the present invention is to solve the above-mentioned problems of the prior art. The object of the present invention is, firstly, even if the substrate is warped, the warpage is absorbed and the lower surface of the solder ball is absorbed. Is to be able to maintain flatness.
Another object of the present invention is to enable a process for absorbing a substrate process to be performed without causing a solder ball contact accident.
【０００４】[0004]
【課題を解決するための手段】上記の課題を解決するた
め、本発明によれば、（１）絶縁性基板の表面に半導体
チップの電極と接続されるパッドが、その裏面に半田ラ
ンドが形成されその間が配線およびスルーホールによっ
て接続されている印刷配線基板上に、半導体チップを搭
載しその電極を前記パッドに接続する工程と、（２）前
記半導体チップを樹脂封止する工程と、（３）前記半田
ランドに導電性ボールを仮止めする工程と、（４）前記
導電性ボールが当接する位置に凹部が形成されたボール
成形板を前記導電性ボールに当接させ、加熱・加圧して
前記導電性ボールの先端部の平坦性を高める工程と、を
有することを特徴とするボールグリッドアレイ型半導体
装置の製造方法、が提供される。According to the present invention, there is provided, according to the present invention, (1) a pad connected to an electrode of a semiconductor chip on a surface of an insulating substrate and a solder land formed on a back surface thereof. A step of mounting a semiconductor chip on a printed wiring board and connecting the electrodes to the pads on the printed wiring board connected therebetween by wiring and through holes; (2) a step of resin-sealing the semiconductor chip; And (4) temporarily contacting the conductive land with the conductive ball, and (4) contacting the conductive ball with a ball forming plate having a recess formed at a position where the conductive ball is in contact with the conductive ball, and applying heat and pressure. Improving the flatness of the tip of the conductive ball.
【０００５】また、上記の課題を解決するため、本発明
によれば、（１′）絶縁性基板の表面に半導体チップの
電極と接続されるパッドが、その裏面に半田ランドが形
成されその間が配線およびスルーホールによって接続さ
れている印刷配線基板上に、半導体チップを搭載しその
電極を前記パッドに接続する工程と、（２′）前記半導
体チップを樹脂封止する工程と、（３′）前記半田ラン
ドに対応する位置に形成された凹部内に導電性ボールが
配置されたボール成形板上に、前記導電性ボール上に前
記半田ランドが位置するように前記印刷配線基板を配置
する工程と、（４′）加熱・加圧して前記導電性ボール
の先端部の平坦性を高める工程と、を有することを特徴
とするボールグリッドアレイ型半導体装置の製造方法、
が提供される。According to the present invention, in order to solve the above-mentioned problems, (1 ') a pad connected to an electrode of a semiconductor chip is formed on a surface of an insulating substrate, and a solder land is formed on a back surface thereof. Mounting a semiconductor chip on a printed wiring board connected by wiring and through holes and connecting the electrodes to the pads; (2 ') resin sealing the semiconductor chip; and (3') A step of arranging the printed wiring board so that the solder lands are located on the conductive balls on a ball forming plate in which conductive balls are arranged in recesses formed at positions corresponding to the solder lands; and (4 ') a step of increasing the flatness of the tip portion of the conductive ball by heating and pressurizing, the method of manufacturing a ball grid array type semiconductor device,
Is provided.
【０００６】[0006]
【発明の実施の形態】次に、本発明の実施の形態につい
て実施例に則して説明する。 ［第１の実施例］図１（ａ）〜図２（ｇ）は、本発明の
第１の実施例を示す工程順の断面図である。まず、図１
（ａ）に示すように、基板表面にダイパッドと表面配
線、基板裏面に一部領域が半田ランドになされた裏面配
線、基板内部に内層配線を有しそれらを接続するスルー
ホール（いずれも図示なし）が形成されている印刷配線
基板１のダイパッド上に、Ａｇペーストを数十ミクロン
の厚さに塗布し、その上に半導体チツプ２を載せ、１８
０℃程度の熱処理を行って半導体チップ２を固定する。
この印刷配線基板上には、複数の半導体チップを搭載で
きるように、マトリックス状に複数（例えば、４×２０
＝８０）組のパターンが形成されている。但し、ライン
状に半導体チップを搭載するように印刷配線基板を形成
することもできる。Next, embodiments of the present invention will be described with reference to examples. [First Embodiment] FIGS. 1A to 2G are cross-sectional views in the order of steps showing a first embodiment of the present invention. First, FIG.
As shown in (a), a die pad and a front surface wiring are provided on the surface of the substrate, a back surface wiring in which a partial area is formed as a solder land on the back surface of the substrate, and a through hole for connecting and connecting the inner layer wiring inside the substrate. ) Is formed on the die pad of the printed wiring board 1 by applying an Ag paste to a thickness of several tens of microns, and the semiconductor chip 2 is placed on the Ag paste.
The semiconductor chip 2 is fixed by performing a heat treatment at about 0 ° C.
On this printed wiring board, a plurality (for example, 4 × 20) is arranged in a matrix so that a plurality of semiconductor chips can be mounted.
= 80) sets of patterns are formed. However, the printed wiring board can be formed so that the semiconductor chips are mounted in a line.
【０００７】次に、図１（ｂ）に示すように、半導体チ
ップの電極パッドと印刷配線基板の表面配線間をＡｕ細
線であるボンディングワイヤ３にて接続する。次に、図
１（ｃ）に示すように、トランスファモールド法等によ
り、半導体チップ上を封止樹脂４にて覆い、１５０〜１
８０℃程度の熱処理によって樹脂を硬化させ、半導体チ
ツプ２およびボンディングワイヤ３を樹脂封止する。次
に、図１（ｄ）に示すように、ダイサーにより、封止樹
脂４および印刷配線基板１を切断し、個々の半導体装置
に分離する。次に、図２（ｅ）に示すように、半導体装
置を丁度落とし込めるようなガイド５ａを有する金属製
の半導体装置トレー５のガイド５ａ間に、半導体装置を
裏返しにして装着する。図２（ｅ）以降の図では図１の
半導体装置が拡大して示されており、基板を貫通して形
成されたスルーホール１ａが示されている。Next, as shown in FIG. 1B, the electrode pads of the semiconductor chip and the surface wiring of the printed wiring board are connected by bonding wires 3 which are Au thin wires. Next, as shown in FIG. 1C, the semiconductor chip is covered with a sealing resin 4 by a transfer molding method or the like.
The resin is cured by a heat treatment of about 80 ° C., and the semiconductor chip 2 and the bonding wires 3 are sealed with the resin. Next, as shown in FIG. 1D, the sealing resin 4 and the printed wiring board 1 are cut by a dicer and separated into individual semiconductor devices. Next, as shown in FIG. 2E, the semiconductor device is turned upside down between the guides 5a of the metal semiconductor device tray 5 having the guides 5a for dropping the semiconductor device. 2E and subsequent figures, the semiconductor device of FIG. 1 is shown in an enlarged manner, and a through hole 1a formed through the substrate is shown.
【０００８】次に、図２（ｆ）に示すように、外部電極
となる半田ボール７を、基板裏面の半田ランド上に一挙
に載せる。次に、図２（ｇ）に示すように、半田ボール
７の搭載位置に対応した位置に半球形型の凹部６ａを有
する成形金型６を、半導体装置上に載せる。ここで、成
形金型６の表面にはクロムめっき等の半田濡れ性の低い
材料の被膜が施されている。そして、図２（ｆ）の工程
にて載せた半田ボール７を半田ランドに固定するために
２３０℃程度の温度を加えつつ加圧する。その際、図２
（ｇ）に示されるように、成形金型が最初の半田ボール
７に接触してから約５０ミクロン程度成形金型６を矢印
方向に押し下げる。これにより、最も高い位置にあった
半田ボールの下面〔本明細書においては半田ボールの下
面とはＢＧＡ型半導体装置を実装基板に実装する際に実
装基板上の配線に接触する面をいう。図２（ｇ）に示す
状態では半田ボールの下面が上になっている〕が押し潰
されることになり、半田ボール下面の平坦性が確保され
る。Next, as shown in FIG. 2 (f), solder balls 7 serving as external electrodes are mounted on the solder lands on the back surface of the substrate at once. Next, as shown in FIG. 2G, a molding die 6 having a hemispherical concave portion 6a at a position corresponding to the mounting position of the solder ball 7 is mounted on the semiconductor device. Here, a coating of a material having low solder wettability such as chrome plating is applied to the surface of the molding die 6. Then, pressure is applied while applying a temperature of about 230 ° C. in order to fix the solder balls 7 placed in the step of FIG. At that time, FIG.
As shown in (g), after the molding die contacts the first solder ball 7, the molding die 6 is pushed down in the direction of the arrow by about 50 microns. Accordingly, the lower surface of the solder ball at the highest position [in this specification, the lower surface of the solder ball refers to the surface that contacts the wiring on the mounting board when the BGA type semiconductor device is mounted on the mounting board. In the state shown in FIG. 2 (g), the lower surface of the solder ball is on the upper side), and the flatness of the lower surface of the solder ball is secured.
【０００９】ここで、半田ボールを押し付ける成形金型
６には半球形の凹部が形成されているため、半田ボール
が押し潰されても隣接する半田ボール同士が接触するこ
とはない。半田ボールの接触事故をより確実に防ぐに
は、印刷配線基板の半田ランドの周囲に５０〜２００μ
ｍ厚の半田流れ止めを形成しておくのがよい。また、基
板裏面の半田ランドを除く領域全体を５０〜２００μｍ
厚のカバー膜にて覆うようにしても同様の効果が得られ
る。このようにして形成されたＢＧＡ型半導体装置で
は、半田ボール下面の平坦性が確保されているため、こ
の製品の測定試験の際にテストソケットが接触不良を起
こすことがなくなり、安定した測定が可能になる。ま
た、図６に示されるように、ＢＧＡ型半導体装置を実装
基板１０上に搭載する際に、半田ボール７が実装基板上
の配線（図示なし）に接触しなくなることが回避され、
信頼性の高い半田付けが可能になる。Here, since the hemispherical concave portion is formed in the molding die 6 for pressing the solder balls, even when the solder balls are crushed, adjacent solder balls do not come into contact with each other. In order to prevent the contact accident of the solder ball more surely, 50-200μ around the solder land of the printed wiring board
It is preferable to form an m-thick solder flow stopper. Also, the entire area excluding the solder lands on the back surface of the substrate is 50 to 200 μm.
The same effect can be obtained by covering with a thick cover film. In the BGA type semiconductor device formed in this way, since the flatness of the lower surface of the solder ball is ensured, the test socket does not cause a contact failure during the measurement test of this product, and stable measurement is possible. become. Further, as shown in FIG. 6, when the BGA type semiconductor device is mounted on the mounting substrate 10, it is avoided that the solder ball 7 does not contact the wiring (not shown) on the mounting substrate,
Reliable soldering becomes possible.
【００１０】［第２の実施例］図３（ａ）〜（ｄ）は、
本発明の第２の実施例を示す工程順の断面図である。半
導体チップを印刷配線基板上に搭載し、樹脂封止を行う
までの工程は、第１の実施例と同様であるので、その説
明は省略する。図３（ａ）に示すように、樹脂封止済み
の半導体装置（の集団）を印刷配線基板１側が上になる
ように配置して、全ての半田ランド上に半田ボール７を
載せる。そして、２３０℃程度に加熱して半田ボールを
接着（仮止め）する。そして、図３（ｂ）に示すよう
に、ダイサーを用いて個々の半導体装置に分離する。続
いて、図２（ｃ）に示すように、半田ボールの取り付け
られた半導体装置（ＢＧＡ型半導体装置）を半導体装置
トレー５のガイド５ａ間に装着する。次いで、図３
（ｄ）に示されるように、半球形型の凹部６ａを有する
成形金型６を半導体装置上に載せ、２３０℃程度の温度
を加えつつ加圧して、半田ボールの下面を平坦化する。[Second Embodiment] FIGS. 3 (a) to 3 (d)
It is sectional drawing of a process order which shows the 2nd Example of this invention. The steps from mounting the semiconductor chip on the printed wiring board to performing resin sealing are the same as those in the first embodiment, and thus description thereof will be omitted. As shown in FIG. 3 (a), a semiconductor device (group) resin-sealed is arranged so that the printed wiring board 1 side faces upward, and solder balls 7 are placed on all the solder lands. Then, the solder ball is bonded (temporarily fixed) by heating to about 230 ° C. Then, as shown in FIG. 3B, the semiconductor devices are separated into individual semiconductor devices using a dicer. Subsequently, as shown in FIG. 2C, the semiconductor device (BGA type semiconductor device) to which the solder balls are attached is mounted between the guides 5a of the semiconductor device tray 5. Then, FIG.
As shown in (d), a molding die 6 having a hemispherical concave portion 6a is placed on a semiconductor device and pressed while applying a temperature of about 230 ° C. to flatten the lower surface of the solder ball.
【００１１】［第３の実施例］図４（ａ）〜（ｄ）は、
本発明の第３の実施例を示す工程順の断面図である。本
実施例においても、半導体チップを樹脂封止し、ダイサ
ーにより個々の半導体装置に分離するまでの工程は、第
１の実施例の場合と同様であるので、個々の半導体装置
に分離した状態を図４（ａ）に示し、そこまでの工程の
詳細な説明は省略する。次に、図４（ｂ）に示すよう
に、印刷配線基板の半田ランドに対応した位置に半球形
型の凹部を有する成形金型８を用意し、その凹部内に半
導体装置の外部電極となる半田ボール７を配置する。次
に、図４（ｃ）に示されるように、半導体装置が丁度は
まり込む形状のガイド９ａを有し、かつ真空吸着手段を
有する半導体装置保持具９により、分割された半導体装
置を真空吸着し、印刷配線基板上の半田ランドと成形金
型８上の半田ボール７との位置合わせを行う。その後、
半導体装置保持具９を降下させ、印刷配線基板の半田ラ
ンドを半田ボール７に接触させる。そして、２３０℃程
度に加熱しつつ、最初に半田ランドが半田ボール７に接
触してからさらに半導体装置保持具９を５０ミクロン程
度押し下げて、半田ボール７を半田ランドに接着すると
ともに半田ボール下面の平坦化を図る。その後、図４
（ｄ）に示されるように、ＢＧＡ型半導体装置を吸着・
保持した半導体装置保持具９を上昇させる。[Third Embodiment] FIGS. 4 (a) to 4 (d)
It is sectional drawing of a process order which shows the 3rd Example of this invention. Also in the present embodiment, the steps from resin sealing of the semiconductor chip to separation into individual semiconductor devices by the dicer are the same as those in the first embodiment. FIG. 4A shows a detailed description of the steps up to that point. Next, as shown in FIG. 4B, a molding die 8 having a hemispherical concave portion at a position corresponding to the solder land on the printed wiring board is prepared, and the concave portion serves as an external electrode of the semiconductor device. The solder balls 7 are arranged. Next, as shown in FIG. 4C, the divided semiconductor devices are vacuum-sucked by a semiconductor device holder 9 having a guide 9a in which the semiconductor device just fits and having vacuum suction means. Then, the solder lands on the printed wiring board and the solder balls 7 on the molding die 8 are aligned. afterwards,
The semiconductor device holder 9 is lowered to bring the solder lands of the printed wiring board into contact with the solder balls 7. Then, while being heated to about 230 ° C., the solder land first contacts the solder ball 7, and then the semiconductor device holder 9 is further pushed down by about 50 μm, thereby bonding the solder ball 7 to the solder land and the lower surface of the solder ball. Plan for flattening. Then, FIG.
As shown in (d), the BGA type semiconductor device is sucked
The held semiconductor device holder 9 is raised.
【００１２】［第４の実施例］図５（ａ）〜（ｃ）は、
本発明の第４の実施例を示す工程順の断面図である。本
実施例においても、半導体チップを樹脂封止し、ダイサ
ーにより個々の半導体装置に分離するまでの工程は、第
１の実施例の場合と同様であるので、これらの工程の図
示およびその詳細な説明は省略する。図５（ａ）に示す
ように、半導体装置が丁度はまり込む形状のガイド８ａ
を有し、かつ印刷配線基板の半田ランドに対応した位置
に半球形型の凹部を有する成形金型８を用意し、その凹
部内に外部電極となる半田ボール７を配置する。続い
て、図５（ｂ）に示されるように、真空吸着手段を有す
る半導体装置保持具９により、分割された半導体装置を
真空吸着し、その半導体装置を成型金型８上に搬送す
る。そして、真空吸着を解除して半導体装置を成型金型
８の凹所内に落とし込む。続いて、図５（ｃ）に示され
るように、２３０℃程度に加熱しつつ、押圧板１１によ
り半導体装置を押圧して、半田ボール７を半田ランドに
接着するとともに半田ボール下面の平坦化を図る。[Fourth Embodiment] FIGS. 5A to 5C show a fourth embodiment.
It is sectional drawing of a process order which shows the 4th Example of this invention. Also in this embodiment, the steps from sealing the semiconductor chip with a resin and separating the semiconductor chips into individual semiconductor devices by a dicer are the same as those in the first embodiment. Description is omitted. As shown in FIG. 5A, a guide 8a having a shape in which the semiconductor device is just fitted.
And a molding die 8 having a hemispherical concave portion at a position corresponding to the solder land of the printed wiring board, and a solder ball 7 serving as an external electrode is arranged in the concave portion. Subsequently, as shown in FIG. 5B, the divided semiconductor devices are vacuum-sucked by a semiconductor device holder 9 having vacuum suction means, and the semiconductor devices are transferred onto a molding die 8. Then, the vacuum suction is released and the semiconductor device is dropped into the recess of the molding die 8. Subsequently, as shown in FIG. 5C, the semiconductor device is pressed by the pressing plate 11 while being heated to about 230 ° C., so that the solder ball 7 is bonded to the solder land and the lower surface of the solder ball is flattened. Aim.
【００１３】以上好ましい実施例について説明したが、
本発明はこれらの実施例に限定されるものではなく、本
発明の要旨を変更しない範囲内において適宜の変更が可
能なものである。例えば、実施例では成型金型の凹部は
半球形であったが、底部が平面、突起状もしくは丸みを
有する円筒形などであってもよい。また、実施例では、
半田ボール成型板（成型金型）や半導体装置トレーは金
属製であったが、石英ガラスやセラミックス製であって
もよい。また、半田ボール成型板（成型金型）にヒータ
を埋め込むようにしてもよい。また、実施例では、半導
体チップをダイパッド上に搭載しその電極をワイヤボン
ディング方式で接続していたが、この方式に代えフリッ
プチップ方式で半導体チップを印刷配線基板上に搭載す
るようにしてもよい。While the preferred embodiment has been described,
The present invention is not limited to these examples, and can be appropriately changed without changing the gist of the present invention. For example, in the embodiment, the concave portion of the molding die has a hemispherical shape, but may have a flat bottom surface, a protruding shape or a rounded cylindrical shape. In the embodiment,
Although the solder ball molding plate (molding mold) and the semiconductor device tray are made of metal, they may be made of quartz glass or ceramics. Further, a heater may be embedded in a solder ball molding plate (molding die). In the embodiment, the semiconductor chip is mounted on the die pad and its electrodes are connected by the wire bonding method. Instead of this method, the semiconductor chip may be mounted on the printed wiring board by the flip chip method. .
【００１４】[0014]
【発明の効果】以上説明したように、本発明は、凹部を
有するボール成形板によって、ＢＧＡ型半導体装置の半
田ボールを成形するものであるので、半田ボール下面の
平坦性を向上させることができる。したがって、本発明
によれば、最終製品試験の際にテストソケットが接触不
良を起こしてしまったりあるいは実装基板上への実装の
際に接続不良を起こしたりすることを防止することが可
能になる。そして、本発明によれば、ボール成形板に
は、ボールがはまる凹部が形成されているため、ボール
下面の平坦化作業の際にボール同士が接触する事故を防
ぐことができる。さらに、印刷配線基板の半田ランドの
周囲に半田流れ止めを形成しておくことにより、半田ボ
ールの接触をより確実に防止することができる。As described above, according to the present invention, since the solder balls of the BGA type semiconductor device are formed by the ball forming plate having the concave portions, the flatness of the lower surface of the solder balls can be improved. . Therefore, according to the present invention, it is possible to prevent a test socket from causing a contact failure at the time of a final product test or a connection failure at the time of mounting on a mounting board. Further, according to the present invention, since the concave portion in which the ball fits is formed in the ball forming plate, it is possible to prevent the balls from coming into contact with each other at the time of flattening the lower surface of the ball. Further, by forming the solder flow stopper around the solder land of the printed wiring board, the contact of the solder ball can be more reliably prevented.
【図１】 本発明の第１の実施例の工程順の断面図（そ
の１）。FIG. 1 is a sectional view of a first embodiment of the present invention in the order of steps (part 1).
【図２】 本発明の第１の実施例の工程順の断面図（そ
の２）。FIG. 2 is a sectional view of a first embodiment of the present invention in the order of steps (part 2).
【図３】 本発明の第２の実施例の工程順の断面図。FIG. 3 is a sectional view of a second embodiment of the present invention in the order of steps.
【図４】 本発明の第３の実施例の工程順の断面図。FIG. 4 is a sectional view of a third embodiment of the present invention in the order of steps.
【図５】 本発明の第４の実施例の工程順の断面図。FIG. 5 is a sectional view of a fourth embodiment of the present invention in the order of steps.
【図６】 本発明の効果を説明するための断面図。FIG. 6 is a cross-sectional view illustrating the effect of the present invention.
【図７】 従来のＢＧＡ型半導体装置の断面図。FIG. 7 is a cross-sectional view of a conventional BGA type semiconductor device.
【図８】 従来例の問題点を説明するための断面図。FIG. 8 is a sectional view for explaining a problem of the conventional example.
１、１０１ 印刷配線基板 １ａ、１０１ａ スルーホール ２、１０２ 半導体チツプ ３、１０３ ボンディングワイヤ ４、１０４ 封止樹脂 ５ 半導体装置トレー ５ａ ガイド ６ 成形金型 ６ａ 凹部 ７、１０７ 半田ボール ８ 成形金型 ８ａ ガイド ９ 半導体装置保持具 ９ａ ガイド １０、１１０ 実装基板 １１ 押圧板 １０１ｂ 樹脂基板 １０１ｃ 表面配線 １０１ｄ 裏面配線 １０１ｅ 内層配線 １０５ ソルダレジスト DESCRIPTION OF SYMBOLS 1, 101 Printed wiring board 1a, 101a Through hole 2, 102 Semiconductor chip 3, 103 Bonding wire 4, 104 Sealing resin 5 Semiconductor device tray 5a Guide 6 Mold 6a Concave 7, 107 Solder ball 8 Mold 8a Guide Reference Signs List 9 semiconductor device holder 9a guide 10, 110 mounting substrate 11 pressing plate 101b resin substrate 101c front surface wiring 101d back surface wiring 101e inner layer wiring 105 solder resist
フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） // Ｂ２３Ｋ 101:42 Ｈ０１Ｌ 21/92 ６０４Ｆ Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (reference) // B23K 101: 42 H01L 21/92 604F
Claims (12)
の電極と接続されるパッドが、その裏面に半田ランドが
形成されその間が配線およびスルーホールによって接続
されている印刷配線基板上に、半導体チップを搭載しそ
の電極を前記パッドに接続する工程と、 （２）前記半導体チップを樹脂封止する工程と、 （３）前記半田ランドに導電性ボールを配置する工程
と、 （４）前記導電性ボールが当接する位置に凹部が形成さ
れたボール成形板を、前記凹部内に前記導電性ボールが
入るように、前記印刷配線基板に対向させて配置し、加
熱・加圧して前記導電性ボールの先端部の平坦性を高め
る工程と、を有することを特徴とするボールグリッドア
レイ型半導体装置の製造方法。(1) A pad connected to an electrode of a semiconductor chip is formed on a surface of an insulating substrate, and a solder land is formed on a back surface of the pad. Mounting a semiconductor chip and connecting its electrodes to the pads; (2) resin sealing the semiconductor chip; (3) arranging conductive balls on the solder lands; A ball forming plate having a concave portion formed at a position where the conductive ball is in contact with the printed wiring board is arranged so that the conductive ball enters the concave portion. A method of manufacturing a ball grid array type semiconductor device, comprising: a step of improving the flatness of a tip portion of a ball.
プの電極と接続されるパッドが、その裏面に半田ランド
が形成されその間が配線およびスルーホールによって接
続されている印刷配線基板上に、半導体チップを搭載し
その電極を前記パッドに接続する工程と、 （２′）前記半導体チップを樹脂封止する工程と、 （３′）前記半田ランドに対応する位置に形成された凹
部内に導電性ボールが配置されたボール成形板上に、前
記導電性ボール上に前記半田ランドが位置するように前
記印刷配線基板を配置する工程と、 （４′）加熱・加圧して前記導電性ボールの先端部の平
坦性を高める工程と、を有することを特徴とするボール
グリッドアレイ型半導体装置の製造方法。(1 ') A pad connected to an electrode of a semiconductor chip is formed on a surface of an insulating substrate, and a solder land is formed on a back surface of the pad, and a pad is formed on a printed wiring board connected between the land and a wiring. Mounting a semiconductor chip and connecting its electrodes to the pads; (2 ') sealing the semiconductor chip with a resin; and (3') mounting the semiconductor chip in a recess formed at a position corresponding to the solder land. Disposing the printed wiring board on the ball forming plate on which the conductive balls are disposed so that the solder lands are located on the conductive balls; and (4 ') heating and pressurizing the conductive balls. Improving the flatness of the tip of the semiconductor device.
導電性ボールを前記半田ランド上に接着する工程である
ことを特徴とする請求項１記載のボールグリッドアレイ
型半導体装置の製造方法。3. The manufacturing method of a ball grid array type semiconductor device according to claim 1, wherein said step (2) includes a step of bonding a conductive ball onto said solder land by heat treatment. Method.
またはライン状に複数の半導体チップを搭載できるよう
に、複数単位の配線パターンが形成されており、前記第
（２）の工程の後前記第（３）の工程に先立って、また
は、前記第（２′）の工程の後前記第（３′）の工程に
先立って、若しくは、前記第（３）の工程の後前記第
（４）の工程に先立って、個々の半導体装置に切り分け
る工程が付加されることを特徴とする請求項１、２また
は３記載のボールグリッドアレイ型半導体装置の製造方
法。4. A plurality of wiring patterns are formed on the printed wiring board so that a plurality of semiconductor chips can be mounted in a matrix or a line, and after the step (2), the plurality of wiring patterns are formed. Prior to the step (3), after the step (2 '), prior to the step (3'), or after the step (3), the step (4) 4. The method of manufacturing a ball grid array type semiconductor device according to claim 1, wherein a step of dividing the individual semiconductor devices is added prior to the step.
μｍ以上２００μｍ以下の半田流れ止めが形成されてい
ることを特徴とする請求項１または２記載のボールグリ
ッドアレイ型半導体装置の製造方法。5. A film having a thickness of 50 around the solder land.
3. The method for manufacturing a ball grid array type semiconductor device according to claim 1, wherein a solder flow stopper having a thickness of at least 200 [mu] m is formed.
ンドの形成領域を除いて、膜厚が５０μｍ以上２００μ
ｍ以下の絶縁性被膜が形成されていることを特徴とする
請求項１または２記載のボールグリッドアレイ型半導体
装置の製造方法。6. The printed wiring board has a thickness of 50 μm or more and 200 μm or less on the back surface except for the solder land formation region.
3. The method of manufacturing a ball grid array type semiconductor device according to claim 1, wherein an insulating film having a thickness of not more than m is formed.
特徴とする請求項１または２記載のボールグリッドアレ
イ型半導体装置の製造方法。7. The method for manufacturing a ball grid array type semiconductor device according to claim 1, wherein said insulating substrate is a resin substrate.
とを特徴とする請求項１または２記載のボールグリッド
アレイ型半導体装置の製造方法。8. The method of manufacturing a ball grid array type semiconductor device according to claim 1, wherein said conductive balls are solder balls.
特徴とする請求項１または２記載のボールグリッドアレ
イ型半導体装置の製造方法。9. The method for manufacturing a ball grid array type semiconductor device according to claim 1, wherein said ball forming plate is made of metal.
着性の被膜が形成されていることを特徴とする請求項９
記載のボールグリッドアレイ型半導体装置の製造方法。10. The ball-formed board is provided with a solder-resistant coating on the surface thereof.
The manufacturing method of the ball grid array type semiconductor device described in the above.
形状は、半球形、円筒形、底面が丸みのある円筒形の中
の何れかであることを特徴とする請求項１または２記載
のボールグリッドアレイ型半導体装置の製造方法。11. The method according to claim 1, wherein the shape of the concave portion formed in the ball forming plate is any one of a hemispherical shape, a cylindrical shape, and a cylindrical shape having a rounded bottom surface. A method for manufacturing a ball grid array type semiconductor device.
れていることを特徴とする請求項１または２記載のボー
ルグリッドアレイ型半導体装置の製造方法。12. The method for manufacturing a ball grid array type semiconductor device according to claim 1, wherein a heater is buried in the ball forming plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000212202A JP2002026188A (en) | 2000-07-13 | 2000-07-13 | Manufacturing method for ball grid array semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000212202A JP2002026188A (en) | 2000-07-13 | 2000-07-13 | Manufacturing method for ball grid array semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002026188A true JP2002026188A (en) | 2002-01-25 |
Family
ID=18708151
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000212202A Pending JP2002026188A (en) | 2000-07-13 | 2000-07-13 | Manufacturing method for ball grid array semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP2002026188A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014192383A (en) * | 2013-03-27 | 2014-10-06 | Fujitsu Ltd | Electronic component and method of manufacturing electronic device |
-
2000
- 2000-07-13 JP JP2000212202A patent/JP2002026188A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014192383A (en) * | 2013-03-27 | 2014-10-06 | Fujitsu Ltd | Electronic component and method of manufacturing electronic device |
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