JP2002025296A - Verifying method for redundancy analyzing program of semiconductor integrated circuit and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a test time by automatically performing examination and preparation of a redundancy analyzing and verifying program and to prevent dispersion of a verified quality level owing to difference of recognition levels by automating examination of verifying contents and a relieving code expected value and discrimination of acceptance or rejection. SOLUTION: Information for generating a pseudo memory defective pattern is automatically extracted based on information about memory circuit constitution of a test specification 2 and redundancy circuit constitution, a pseudo memory pattern information file 10 is prepared, while a relieving code expected value is automatically extracted, and a relieving code expected value file 11 is prepared (STP6). A pseudo memory defective pattern is automatically generated and a test is performed based on the pseudo memory defective pattern information, a model program, and a model pattern 12, while redundancy analysis is performed by a redundancy analyzing program 7, the redundancy analyzed result is stored in a relieving code output result file 13. Then the relieving code expected value file 11 is compared with the reliving code output result file.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a redundancy analysis program verification method and system for automatically verifying a redundancy analysis program created based on a memory circuit configuration and a redundancy circuit configuration in a semiconductor integrated circuit including a memory circuit. Things.

[0002]

2. Description of the Related Art FIG. 16 is a conventional flowchart for verifying a redundancy analysis program created based on a memory circuit configuration and its redundant circuit configuration in a semiconductor integrated circuit including a memory cell. Verification of a redundancy analysis program can be roughly classified into the following five steps, and conventionally, all are manually performed.

STEP 1: Examination of pseudo memory failure pattern and expected value of repair code (STP1 in FIG. 16). FIG.
In a semiconductor integrated circuit (LSI) 1 including a memory circuit shown in FIG.
/ O number (number of input / output pins)) and redundant circuit configuration (row / column spare selection bits for selecting a spare to be used, row / column replacement target address bits for defining which main memory to replace the selected spare with) , The number of row / column spares existing in the rescue area), test contents for confirming whether the memory operates as specified, and a test method 2 which describes a test method are prepared. Based on the test specification 2, For the created redundancy analysis program, a plurality of pseudo memory failure pattern specifications 3 that can confirm whether all the rescue codes that can be output are output correctly are created as follows.

(1 *) I / O setting verification pattern (each I / O
(2 *) Row spare selection setting verification pattern (Creation of pseudo memory failure pattern for selecting each row spare) (3 *) Column spare selection setting verification pattern (Pseudo for selecting each column spare) (4 *) Row replacement target address selection setting verification pattern (Creation of pseudo memory failure pattern for selecting each row replacement target address) (5 *) Column replacement target address selection setting verification pattern (Each column replacement) (6 *) Verification pattern for setting the number of row spares (creating a pattern in which the number of memory defects existing in the row relief area is changed) (7 *) Verification pattern for setting the number of column spares (Creation of a pattern that changes the number of memory defects existing in the column rescue area (8 *) Row address redundancy analysis unused bit verification pattern (creation of defective pattern by changing bits not used as row selection address) (9 *) Column address redundancy analysis unused bit verification pattern (not used as column selection address Creating defective patterns with changed bits)

In STEP 1, at the same time as the creation of the pseudo memory defect pattern specification 3, the relief code expected value 4 used for the pass / fail judgment of the redundancy rescue program is changed to the pseudo memory defect pattern specification 3 and a predetermined relief code format 9 (FIG. 3). ).

STEP 2: Creation of a pseudo memory failure pattern (STP2 in FIG. 16). In order to accumulate pseudo memory defect information in the defect information storage memory of the semiconductor test device,
A pseudo memory failure pattern 5 is created based on the pseudo memory failure pattern specification 3 created in STEP1.

STEP 3: Acquisition of a relief code output in a pseudo memory failure pattern (STP3 in FIG. 16). A main program 6 created in advance for mass production testing in order to output a redundant analysis result to a semiconductor test device;
The redundancy analysis program 7 and the pseudo memory failure pattern 5 created in STEP 2 are operated by the semiconductor test apparatus, the pseudo memory failure information is transferred to the failure information memory in the semiconductor test apparatus, and the redundancy analysis is performed. Then, after executing the redundancy analysis, a relief code output result file 8 is created.

STEP 4: Examination of expected value of rescue code and output result of rescue code (STP4 in FIG. 16). STEP1
The expected value 4 of the rescue code examined in the step 3 is compared with the rescue code output result file 8 created in STEP 3 by hand to confirm whether the rescue code is output as expected.
If the rescue code is not output as expected,
Pseudo memory failure pattern specification 3, expected rescue code 4,
The pseudo memory failure pattern 5 and the redundancy analysis program 7 are all reviewed, and the verification is performed again.

STEP5: Implementation of all verification items, pass / fail judgment (FIG. 16, STP5). According to the pseudo memory pattern specification 3 examined in STEP1, STEP2 to STEP4 are repeatedly executed, and verification is completed by confirming that all results are output as expected values.

[0010]

In a conventional semiconductor integrated circuit including a memory cell, a method for verifying a redundancy analysis program created based on a memory circuit configuration and its redundant circuit configuration is configured as described above. However, the following problems have occurred.

1) Increase in test development time It is necessary to examine and create a verification program in addition to the normal test program and redundancy analysis program development.
The verification needs to be performed for each test development of a new semiconductor integrated circuit. Further, in the system LSI, since a plurality of types of memories are mounted on one chip, verification is manually performed for each redundancy analysis rule, which leads to an increase in test development time.

2) Variation in verification quality In order to manually examine the contents of verification, the expected value of the rescue code, and make a pass / fail decision, a variation in verification quality due to a difference in the recognition level of personnel has occurred.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and greatly reduces the test time by automatically examining and creating a manual redundant analysis verification program. It is another object of the present invention to prevent the variation of the verification quality level due to the difference in the recognition level by automating the verification contents manually, the examination of the expected value of the rescue code, and the pass / fail judgment.

[0014]

According to the first aspect of the present invention, there is provided a redundancy analysis program verifying method for automatically verifying a redundancy analysis program for a memory circuit and a semiconductor integrated circuit having the redundancy circuit. Automatically extracting information for generating a pseudo memory failure pattern which is a verification pattern of a redundancy analysis program based on information on the configuration and the redundant circuit configuration, and creating a pseudo memory failure pattern information file. I do.

According to a second aspect of the present invention, in the first aspect of the present invention, a rescue code expected value for verifying the redundancy analysis is automatically extracted based on the information on the memory circuit configuration and the redundant circuit configuration. A step of creating a value file.

[0016] The invention of claim 3 is claim 1 or claim 2.
In the invention of the present application, a pseudo memory failure pattern is automatically generated and tested based on the pseudo memory failure pattern information, the template program and the template pattern, and the redundancy analysis is performed by the redundancy analysis program. The method further comprises the step of storing in a relief code output result file.

According to a fourth aspect of the present invention, in the third aspect of the present invention, the information in the relief code expected value file is compared with the information in the relief code output result file, and the comparison result is stored in the redundancy analysis program determination result file. The step of performing

The invention according to claim 5 is the invention according to claim 3 or claim 4.
In the invention, a pseudo memory failure pattern is automatically generated and tested in a pseudo semiconductor test environment on an electronic computer based on the pseudo memory defect pattern information, the template program and the template pattern. A redundancy analysis is performed by a redundancy analysis program in a pseudo semiconductor test environment on a computer, and the result of the redundancy analysis is stored in a relief code output result file.

The invention according to claim 6 is the invention according to claim 3 or claim 4.
In the invention, a pseudo memory failure pattern is automatically generated by a self-pattern generation circuit built in a semiconductor integrated circuit based on the pseudo memory failure pattern information, the template program and the template pattern, and a test is performed.
A redundancy analysis is performed by a redundancy analysis circuit built in the semiconductor integrated circuit, and the result of the redundancy analysis is stored.

According to a seventh aspect of the present invention, there is provided a redundancy analysis program verification system for automatically verifying a redundancy analysis program for a semiconductor integrated circuit having a memory circuit and its redundant circuit, and relates to a memory circuit configuration and a redundant circuit configuration. A means for automatically extracting information for generating a pseudo memory failure pattern, which is a verification pattern of the redundancy analysis program, based on the information and creating a pseudo memory failure pattern information file is provided.

According to an eighth aspect of the present invention, in the seventh aspect of the present invention, a rescue code expected value for verifying the redundancy analysis is automatically extracted based on the information on the memory circuit configuration and the redundant circuit configuration. It is characterized by comprising means for creating a value file.

According to a ninth aspect of the present invention, there is provided an image processing apparatus comprising:
, A pseudo memory failure pattern is automatically generated and tested based on the pseudo memory failure pattern information, the template program and the template pattern, the redundancy analysis is performed by the redundancy analysis program, and the redundancy analysis result is saved as a repair code. It is characterized by comprising means for storing in an output result file.

According to a tenth aspect of the present invention, in the ninth aspect of the present invention, the information of the relief code expected value file is compared with the information of the relief code output result file, and the comparison result is stored in the redundancy analysis program determination result file. Means for performing the operation.

According to an eleventh aspect of the present invention, in the first to tenth aspects of the present invention, the information for generating the pseudo memory failure pattern is information on a pattern operation start and end address, the number of repetitions, and an I / O pin. There is a feature.

According to a twelfth aspect of the present invention, in the first to eleventh aspects of the present invention, the semiconductor integrated circuit includes a plurality of or a plurality of types of memory circuits, and a redundancy analysis program for each memory circuit is stored. It is characterized by automatic verification.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a flowchart showing a method for verifying a redundancy analysis program of a semiconductor integrated circuit according to a first embodiment of the present invention.
3 shows an automatic verification flow of the redundancy analysis program of FIG.
Hereinafter, the method of the present embodiment will be described step by step based on four main steps.

STEP6: Pseudo memory defect pattern information extraction, expected repair code creation (STP6 in FIG. 1). Semiconductor integrated circuit (LSI) 1 including the memory circuit shown in FIG.
In the memory circuit configuration (row, column maximum value,
Number of I / O lines (number of input / output pins)) and redundant circuit configuration (row / column spare selection bits for selecting a spare to be used)
Row / column replacement target address bits that define which main memory is to be replaced with the selected spare, the number of row / column spares present in the rescue area), test contents to confirm whether the memory operates as specified, A test specification 2 describing a test method is prepared, and memory circuit configuration information and redundant circuit information are manually input based on the test specification 2 to automatically generate a pseudo memory failure pattern by a semiconductor test apparatus. A relief code expected value file 11 for automatically determining the pseudo memory failure pattern information file 10 and the relief code output result file 13 output from the semiconductor test apparatus is created.

First, an output example of a pseudo memory failure pattern in the LSI 1 and a method of producing the same will be described in the following (1) to (9).

(1) Verification Pattern for I / O Setting The output example of FIG. 4 is a pattern for verifying a relief code when the I / O of the LSI 1 is changed.
Since I1 has four I / Os, "I / O" is changed to "1 (2
Base number: 0001) "," 2 (0010) "," 4 (01
00) ”and“ 8 (1000) ”. By the way, the pseudo memory failure information is“ Low ”,
It consists of “column”, “I / O”, “direction”, and “line length”. “Row” and “column” are the start addresses of the pseudo memory defect pattern, “I / O” is the I / O information for which a pseudo memory defect is to be created, and “direction” is whether the pseudo memory defect to be created is a row line defect or a column line defect. The “line length” means the number of bits of a row line defect or a column line defect (length of a line defect).

(2) Verification Pattern for Row Spare Selection Setting The output example of FIG. 5 is a pattern for verifying a rescue code when a row spare selection address is changed, and includes a row maximum value, a row spare selection address bit, and a rescue code. It is created based on the number of spares in the area. Row address is maximum value 7
Since the FF and row spare selection address bits are the 11th bit and the 9th bit of the row and the number of row spares is 1, the 11th row and the 9th bit of the row are changed, and the column length is equivalent to that of the row spare. The row spare selection setting can be verified with four line failure patterns (FIG. 5). Here, FIG. 6 is the first line in FIG.
FIG. 7 is a simplified diagram of a pseudo memory failure pattern of FIG.

(3) Verification pattern for column spare selection setting This is a pattern for verifying a relief code when the column spare selection address is changed. The column maximum value, the column spare selection address bit, and the spare in the relief area The information is created based on the number and the information extraction method is the same as that of the verification pattern for the row spare selection setting in (2) above.

(4) Verification Pattern for Selecting Row Replacement Target Address The output example in FIG. 7 is a pattern for verifying a relief code when the row replacement target address is changed. Created based on address bits. The pseudo memory failure information is obtained by adding the row address bits other than the row spare selection bits one bit at a time and repeatedly performing verification until all bits other than the row spare selection bits become "1". In addition, from this verification, the prior art (8)
The unused bits in the row address redundancy analysis of *) can also be verified.

(5) Verification pattern for selecting a column replacement target address This is a pattern for verifying a relief code when the column replacement target address is changed, and is created based on the column maximum value and the column spare selection address. The information extraction method is the same as that of the verification pattern for the row replacement target address selection setting in the above (4).

(6) Verification Pattern for Setting the Number of Row Spares The output example of FIG. 8 is a pattern for verifying a repair code and a redundancy analysis result when a plurality of column line defects occur in the row repair area. It is created based on the row maximum value and the row spare selection address bit. The information extraction method is the same as that in the case of the verification pattern for the row replacement target address selection setting in (4).

(7) Verification pattern for setting the number of column spares This is a pattern for verifying a repair code and a redundancy analysis result when a plurality of row line defects occur in the column repair area, and the information extraction method is (6). This is the same as the case of the verification pattern for the setting of the number of row spares.

(8) Verification Pattern for Unused Bits in Row Address Redundancy Analysis Since the verification pattern is verified by the verification pattern for selecting the address to be replaced in (4) above, pseudo memory failure pattern information is not newly created. .

(9) Verification Pattern for Unused Bits in Column Address Redundancy Analysis Since the verification pattern for the column selection target address selection setting in (5) above is confirmed, no pseudo memory failure pattern information is created again. .

Next, an explanation will be given of the expected value of the rescue code used for the automatic judgment of the redundancy analysis result output from the semiconductor test apparatus.

The patterns (1) to (9) of the pseudo memory failure pattern information file 10 described above are generated based on the relief code format 9 (FIG. 3). FIG. 9 shows an output example of the expected rescue code value for the pattern (2) (FIG. 5) of the pseudo memory failure pattern information file 10. In the first row, the pattern start address of the pseudo memory defect information is “0” in both the row and column, and there are 256 column line defects, so that it can be seen that the row can be replaced by the row spare of the main memory 1 (see FIG. See simplified diagram). Since the row replacement target address at that time is "0", when the above information is applied to the relief code format 9, it becomes "100000000000000000" in binary notation, and becomes "8000" in hexadecimal notation. Similarly, the expected value of the rescue code is created in the second and subsequent lines.

STEP 7: Test execution, redundancy analysis (STP 7 in FIG. 1) A pseudo memory failure pattern is generated using the pseudo memory failure pattern information file 10 created in STEP 6 and the template program and template pattern file 12 created in advance. Then, the defective memory information is subjected to redundancy analysis by the redundancy analysis program 7 to be tested, and a relief code output result file 13 is created. Here, a template program file and a template pattern file 12 for applying a pseudo memory failure pattern from the semiconductor test apparatus to the LSI 1 according to the pseudo memory failure pattern information file 10 will be described with reference to FIG. I do.

First, the pseudo memory defective pattern information from the pseudo memory defective pattern information file for one line is read (STP20), and the "direction" information of the read pseudo memory defective pattern information is "R" (row line defect) or "C".
(STP21). When the “direction” is “R”, after calling the row line defect creation template pattern (STP22), the pattern start address (“row, column, I / O, line length”) of the pseudo memory defect pattern information is referred to. Set row, column), expected I / O pin, and pattern repeat count (STP
24). (There is a pattern pattern for creating row line / column line defects, and the pattern is made so that the line length can be changed by changing the number of repeats.) After the setting is completed, a pattern test is executed (STP25), and The obtained defective memory information is transferred to a defect information storage memory (fail memory) of the semiconductor test apparatus (STP
26), the transferred defective memory information is subjected to redundancy analysis (STP27) by the redundancy analysis program 7, and the obtained repair code is output to a file (STP28). The above operation is repeated until all the verification items are completed.

Step 8: Verification of all items (STP
8) It is checked whether all the verification items described in the pseudo memory failure information file 10 in the template program file have been completed.

STEP9: Output of rescue code, expected value comparison (STP9) The rescue code output result file 13 output from the semiconductor test apparatus is compared with the rescue code expected value file 11 created in STEP6, and the result is analyzed by the redundancy analysis program. The output to the determination result file 14 is processed in the template program.

As described above, according to the first embodiment, by automating all the steps other than the input of the test specifications, it is possible to suppress an increase in test development time and suppress a variation in verification quality.

Embodiment 2 FIG. 11 is a flowchart showing a redundancy analysis program verification method according to the second embodiment of the present invention. A semiconductor integrated circuit (L) having a single memory in a pseudo semiconductor test apparatus environment on an electronic computer is shown.
3 shows an automatic verification flow of a redundancy analysis program of SI).

In the first embodiment, the application of the pseudo memory failure pattern and the redundancy analysis are realized on the semiconductor test device. However, in the present embodiment, in the environment of the pseudo semiconductor test device on the electronic computer. The purpose of the present invention is to perform automatic verification of the redundancy analysis program.

In FIG. 11, the STP 10 refers to the pseudo-memory defect information file 10 and creates a pseudo-memory defect pattern using the template program file and the template pattern file 12, and stores the obtained memory defect information. In the step of analyzing the data in accordance with the redundancy analysis program file 7 and creating the repair code output result file 13, it is realized not on the semiconductor test apparatus of the first embodiment but on an electronic computer in a pseudo manner. Other processes are the same as in the first embodiment.

According to the second embodiment, in addition to the effect of the first embodiment, there is an effect that the restriction on the place and time is reduced by performing the verification with the electronic computer instead of the semiconductor test apparatus.

Embodiment 3 FIG. 13 is a flowchart showing a method for verifying a redundancy analysis program according to Embodiment 3 of the present invention, and shows an automatic verification flow of a redundancy analysis program for a semiconductor integrated circuit (LSI) equipped with a plurality of types of memories.

In the first embodiment, the case of a semiconductor integrated circuit (chip) equipped with a single memory has been described. In the present embodiment, a plurality of types of memories and a plurality of types of memories existing in the semiconductor integrated circuit (chip) are described. The purpose is to perform automatic verification of a redundancy analysis program.

FIG. 12 is a diagram showing a semiconductor integrated circuit (LSI) 15 including a plurality of types and a plurality of types of memory circuit portions. The LSI 15 has a "chip address" for distinguishing a plurality of mounted memory circuits. Exists.

In FIG. 13, the test specification 16 includes L
For all memory circuits mounted on the SI15, memory circuit configuration information (row / column maximum value, I
/ O number), redundant circuit information (row / column spare selection address bits, row / column replacement target address bits,
The number of spares in the row / column repair area), test items, and test methods are described. The verification of this embodiment is as follows.
Information is extracted for each redundancy analysis rule based on the test specification 16 and verified for each memory circuit. At this time, each of the mounted memory circuits is selected by a chip address (S
TP11). Other processing is the same as in the first or second embodiment.

According to the third embodiment, in addition to the effect of the first embodiment, automatic verification of the redundancy analysis program of the LSI 15 with a plurality of types of memories is realized by performing the verification for each redundancy analysis rule. Can be.

Embodiment 4 FIG. 14 is a block diagram showing a semiconductor integrated circuit having a memory on which a self-pattern generation circuit and a redundancy analysis circuit according to a fourth embodiment of the present invention are mounted. FIG. 15 is a flowchart showing a redundancy analysis program verification method according to the fourth embodiment, and shows an automatic verification flow of the redundancy analysis circuit of the semiconductor integrated circuit of FIG.

In the first embodiment, the pattern generation and the redundancy analysis are performed by the semiconductor test apparatus. However, in the present embodiment, the semiconductor integrated circuit equipped with the self-pattern generation circuit and the redundancy analysis circuit performs the redundancy analysis by itself. The purpose is to automatically verify the circuit.

In FIG. 14, a semiconductor integrated circuit (LS
I) 17 includes a self-pattern generation circuit and a redundancy analysis circuit (self-diagnosis circuit).

In FIG. 15, the test specification 18 indicates that the LSI 17 including the self-pattern generation circuit and the self-diagnosis circuit has memory circuit configuration information, redundant circuit information, test items,
And test methods. Reference numeral 19 denotes a template program and a template pattern for testing the self-pattern generation circuit and the self-diagnosis circuit. Further, the STP 12 uses the semiconductor test apparatus to change the pattern for operating the self-pattern generation circuit and the self-diagnosis circuit to LS based on the pseudo memory failure information file 10 and the template program pattern 19.
Represents the step of applying to I17.

According to the fourth embodiment, it is necessary to verify the operation of the self-pattern generating circuit of the semiconductor integrated circuit (LSI) 17 in advance, but it is possible to verify the redundancy analysis circuit.

[0059]

As described above, according to the present invention, the test time can be greatly reduced by automatically examining and creating a redundancy analysis verification program. Further, by automatically examining the verification contents, the expected value of the rescue code, and the pass / fail judgment, it is possible to prevent variations in the verification quality level due to the difference in the recognition level.

Further, by performing verification using an electronic computer instead of the semiconductor test apparatus, there is an effect that restrictions on place and time are reduced.

Further, by performing verification for each redundancy analysis rule, automatic verification of a redundancy analysis program for a semiconductor integrated circuit having a plurality of memories and a plurality of types of memories can be realized.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a redundancy analysis program verification method for a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 is a block diagram illustrating a semiconductor integrated circuit including a memory circuit and a redundant circuit.

FIG. 3 is a diagram showing an example of a relief code format.

FIG. 4 is a diagram showing an example of a verification pattern for I / O settings.

FIG. 5 is a diagram showing an example of a verification pattern for row spare selection setting.

FIG. 6 is a simplified diagram showing a memory to be verified for a pseudo memory failure pattern in FIG. 5;

FIG. 7 is a diagram showing an example of a verification pattern for a row replacement target address selection setting.

FIG. 8 is a diagram showing an example of a verification pattern for setting the number of row spares.

[Fig. 9] Example of output of expected value of rescue code

FIG. 10 is a diagram showing an operation flow of a template program based on pseudo memory failure pattern information.

FIG. 11 is a flowchart illustrating a redundancy analysis program verification method according to Embodiment 2 of the present invention;

FIG. 12 is a block diagram showing a semiconductor integrated circuit on which a plurality of types of memory circuits are mounted.

FIG. 13 is a flowchart showing a redundancy analysis program verification method according to Embodiment 3 of the present invention.

FIG. 14 is a block diagram showing a semiconductor integrated circuit having a memory on which a self-pattern generation circuit and a redundancy analysis circuit are mounted according to a fourth embodiment of the present invention.

FIG. 15 is a flowchart illustrating a redundancy analysis program verification method according to Embodiment 4 of the present invention;

FIG. 16 is a flowchart showing a conventional redundancy analysis program verification method for a semiconductor integrated circuit.

[Explanation of symbols]

1 semiconductor integrated circuit (LSI), 2 test specifications, 7
Redundancy analysis program file, 10 pseudo memory failure pattern information file, 11 relief code expected value file, 12 template program, template pattern file, 1
3 relief code output result file, 14 redundancy analysis program judgment result file, 15 semiconductor integrated circuit (LSI) having a plurality of memory circuits, 16 test specifications, 1
7 Self-pattern generation circuit, semiconductor integrated circuit (LSI) equipped with redundancy analysis circuit, 18 test report, 19 template program, template pattern file.

Claims (12)

[Claims] 1. A redundancy analysis program verification method for automatically verifying a redundancy analysis program for a memory circuit and a semiconductor integrated circuit having the redundancy circuit, wherein the method is based on information on a memory circuit configuration and a redundancy circuit configuration. Automatically extract information for generating a pseudo memory failure pattern which is a verification pattern of a redundancy analysis program,
A method for verifying a redundancy analysis program of a semiconductor integrated circuit, comprising a step of creating a pseudo memory failure pattern information file. 2. The method according to claim 1, further comprising a step of automatically extracting a rescue code expected value for verifying the redundancy analysis based on information on the memory circuit configuration and the redundant circuit configuration, and creating a rescue code expected value file. A method for verifying a redundancy analysis program of a semiconductor integrated circuit according to the above. 3. A method for automatically generating and testing a pseudo memory failure pattern based on the pseudo memory failure pattern information, the template program and the template pattern,
3. The method according to claim 1, further comprising the step of performing a redundancy analysis by a redundancy analysis program, and storing the result of the redundancy analysis in a repair code output result file. 4. Comparing information of the relief code expected value file with information of the relief code output result file,
4. The method according to claim 3, further comprising the step of storing the comparison result in a redundancy analysis program determination result file. 5. A pseudo memory defect pattern is automatically generated and tested in a pseudo semiconductor test environment on an electronic computer based on the pseudo memory defect pattern information, the template program and the template pattern. 5. The redundancy of a semiconductor integrated circuit according to claim 3, wherein a redundancy analysis is performed by a redundancy analysis program in a pseudo semiconductor test environment on an electronic computer, and the redundancy analysis result is stored in a relief code output result file. Analysis program verification method. 6. A self-pattern generating circuit built in a semiconductor integrated circuit automatically generates a pseudo-memory defect pattern based on the pseudo-memory defect pattern information, the template program and the template pattern, and performs a test. 4. A redundancy analysis is performed by a redundancy analysis circuit built in the semiconductor integrated circuit, and the result of the redundancy analysis is stored.
5. The method of verifying a redundancy analysis program for a semiconductor integrated circuit according to claim 4. 7. A redundancy analysis program verification system for automatically verifying a redundancy analysis program with respect to a memory circuit and a semiconductor integrated circuit having the redundancy circuit, wherein the redundancy analysis program verification system is provided based on information on a memory circuit configuration and a redundancy circuit configuration. Automatically extract information for generating a pseudo memory failure pattern which is a verification pattern of a redundancy analysis program,
A redundancy analysis program verification system for a semiconductor integrated circuit, comprising: means for creating a pseudo memory failure pattern information file. 8. A means for automatically extracting a rescue code expected value for verifying a redundancy analysis program based on information on a memory circuit configuration and a redundant circuit configuration and creating a rescue code expected value file. 8. The system for verifying redundancy analysis of a semiconductor integrated circuit according to claim 7. 9. A pseudo memory failure pattern is automatically generated based on the pseudo memory failure pattern information, the template program and the template pattern, and a test is performed.
9. The redundancy analysis program verification system for a semiconductor integrated circuit according to claim 7, further comprising means for performing a redundancy analysis by a redundancy analysis program and storing the result of the redundancy analysis in a repair code output result file. 10. Comparing information of the relief code expected value file with information of the relief code output result file,
The redundancy analysis program verification system for a semiconductor integrated circuit according to claim 9, further comprising means for storing the comparison result in a redundancy analysis program determination result file. 11. The information according to claim 1, wherein the information for generating the pseudo memory failure pattern is information on a pattern operation start and end address, the number of repetitions, and an I / O pin. A method or system for verifying a redundancy analysis program of a semiconductor integrated circuit. 12. The semiconductor integrated circuit according to claim 1, wherein a plurality or a plurality of types of memory circuits are mounted, and a redundancy analysis program for each memory circuit is automatically verified. The method or system for verifying a redundancy analysis program of a semiconductor integrated circuit according to any one of the preceding claims.