JP2002025260A - Voltage converting method of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage converting method of a semiconductor integrated circuit device capable of suppressing the fluctuations of internal power supply potential even when externally applied power supply potential fluctuates. SOLUTION: Potential (VCC) that is externally applied is converted into internal potential (ϕD) having a controlled potential area where potential fluctuations are small by restricting the potential (VCC) at a certain potential level by using a step-down circuit (6), and the internal potential (ϕD) is boosted to internal boosted potential (ϕP1 or ϕP2) while reflecting the controlled potential area the internal potential (ϕD) has. The externally applied potential (VCC) is converted into the internal potential (ϕD) by restricting the potential (VCC) at a certain potential level by using another step-down circuit (4) before the step-down circuit (6) operates.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit having an improved power supply system in an integrated circuit.

[0002]

2. Description of the Related Art In a current dynamic random access memory (DRAM), it is desirable to generate a voltage in an integrated circuit itself rather than using an externally applied power as it is. This allows a single externally applied power supply to be connected to the integrated circuit, even if multiple voltage levels are required inside the integrated circuit.

In the current DRAM, a method is employed in which a single externally applied power supply voltage is used and other necessary voltages are generated inside the integrated circuit. Examples of the internal voltage generation circuit include a substrate potential generation circuit for supplying a substrate potential or a well potential, an internal power supply voltage generation circuit used as an internal power supply, and a reference potential generation circuit used as an internal reference potential.

A voltage generating circuit used as an internal power supply includes a booster circuit and a step-down circuit. These internal voltage generating circuits are used for the purpose of improving the operation margin of the integrated circuit with respect to the external power supply voltage and ensuring the reliability. In particular, in recent years, the externally applied power supply voltage has tended to be reduced, and DRAMs having a booster circuit have been proposed.

FIGS. 21 (a) to 21 (d) show configuration examples of the prior art. The example shown in FIG. 7A is an example in which an internal power supply voltage generating circuit is not used. The bootstrap method is used for driving a word line, and an externally applied power supply voltage is used as it is for a peripheral circuit. For example, this method has been adopted in a 1 Mbit DRAM and a 4 Mbit DRAM.

The example shown in FIG. 1B is a method using the output of an internal step-down potential generating circuit as a power supply for a peripheral circuit. For example, this method is used in a 16 Mbit DRAM.

In the examples shown in FIGS. 1C and 1D, in order to cope with the reduction of the externally applied power supply voltage, the output of the boosted potential generating circuit is not used in the bootstrap system but in the word line driving system circuit. It is used as a power supply. Of these, the example shown in (c) uses the externally applied power supply voltage as it is as the power supply for the peripheral circuit, and the example shown in (d)
An internal step-down potential generating circuit is used as a power supply for a peripheral circuit. These methods are, for example, 64Mbit DRAM
It is considered for use in.

[0008]

As described above, DRA
A step-down potential generating circuit for generating a voltage lower than the externally applied power supply voltage as a power supply for the peripheral circuits of M, or a boosted potential generating circuit for generating a voltage higher than the externally applied power supply voltage as a power supply for the word line drive system circuit Is a conventional technique.

However, in the conventional internal power supply voltage system, as shown in FIG.
C drives the potential VCC to an internal boosted potential φP. Similarly, the step-down circuit steps down the input potential VCC to the internal step-down potential φD. With this configuration, when the potential level of the potential VCC changes, the potential levels of the internal boosted potential φP and the internal reduced potential φD also change together.

[0010] In a DRAM of a generation with a low integration degree and a relatively low operation speed, the above fluctuation is within the range of an allowable error. However, in the future, the ultra-large-scale integration of 64M, 256M, 1G,. Considering a DRAM that is a high-speed operation generation, a slight change in the internal power supply voltage can be a sufficient cause of a malfunction.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor integrated circuit device capable of suppressing a change in an internal power supply potential even when a power supply potential applied from the outside fluctuates. And a voltage conversion method.

[0012]

In order to achieve the above object, in a first aspect of a voltage conversion method for a semiconductor integrated circuit device according to the present invention, a first step-down circuit is used and a voltage applied from outside is used. Is converted to an internal potential having a constant potential region with less potential fluctuation by limiting at a certain potential level, and the internal potential is boosted to an internal boosted potential while reflecting the constant potential region of the internal potential. Before the first step-down circuit operates, a second step-down circuit is used to convert the externally applied potential to the internal potential by limiting the potential at an external level to a certain potential level.

In a second aspect of the voltage conversion method for a semiconductor integrated circuit device according to the present invention, the first voltage step-down circuit is used to limit an externally applied potential at a certain potential level, thereby causing a potential fluctuation. Is converted to an internal potential having a constant potential region having a small internal potential, and the internal potential is boosted to a first internal boosted potential used in an internal voltage down converter while reflecting the constant potential region of the internal potential. Is raised to a second internal boosted potential used in the word line drive system circuit while reflecting the constant potential region of the internal potential, and before the first step-down circuit operates, the second step-down circuit is activated. And wherein the potential applied from outside is converted to the internal potential by limiting the potential at a certain potential level.

Further, in a third aspect of the voltage conversion method for a semiconductor integrated circuit device according to the present invention, the first voltage step-down circuit is used to limit an externally applied potential at a certain potential level, thereby causing a potential fluctuation. Is converted to an internal potential having a constant potential region with a small amount, and a potential different from the internal potential is boosted to a first internal boosted potential used in an internal voltage down converter, and the internal potential is set to a constant potential held by the internal potential. The voltage is boosted to the second internal boosted potential used in the word line drive system circuit while reflecting the potential region, and is applied from the outside using the second voltage down circuit before the first voltage down circuit operates. Potential
The internal potential is converted by limiting the potential at a certain potential level.

In a fourth aspect of the voltage conversion method for a semiconductor integrated circuit device according to the present invention, the first voltage step-down circuit is used to limit the externally applied potential at a certain potential level, thereby causing a potential fluctuation. Is converted into an internal potential having a small constant potential region, and the internal potential is boosted to an internal boosted potential used in an internal voltage down converter and a word line drive system circuit while reflecting the constant potential region of the internal potential. Before the first step-down circuit operates, a second step-down circuit is used to convert the externally applied potential to the internal potential by limiting the potential at a certain potential level.

In a fifth aspect of the voltage conversion method for a semiconductor integrated circuit device according to the present invention, the first voltage step-down circuit is used to limit a potential applied from the outside at a certain potential level, thereby causing a potential fluctuation. Is converted into an internal potential having a constant potential region with less, and the internal potential is boosted to an internal boosted potential used in a word line driving system circuit while reflecting the constant potential region of the internal potential, Before the step-down circuit operates, a second step-down circuit is used to convert the externally applied potential to the internal potential by limiting the potential to a certain potential level.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments. In this description, in all the drawings, the same portions are denoted by the same reference characters, and redundant description will be avoided.

FIG. 1 is a block diagram of a dynamic RAM according to the first embodiment of the present invention.

As shown in FIG. 1, inside the IC chip 1,
A reference voltage generating circuit 2 for generating a reference voltage φR from an externally applied potential VCC, a power-on reset circuit 3 for outputting a reset signal SR a predetermined time after turning on the externally applied potential VCC (external power supply), an internal step-down potential from the reference voltage φR φD
Circuit 4 which outputs the voltage until the reset signal SR falls, a boosting circuit 5 for a step-down circuit which is driven by a potential difference between the step-down potential φD and the ground potential GND, and boosts the step-down potential φD to a step-up potential φP1 for the step-down circuit. A source follower-type step-down circuit 6 controlled by the potential φP1 to step down the applied potential VCC to the internal step-down potential φD, driven by a potential difference between the step-down potential φD and the ground potential GND, and boosting the step-down potential φD for the word line driving circuit A booster circuit 7 for the word line drive system for boosting to potential φP2, a reduced potential φD and a ground potential G
ND, the boosted potential φP2 and the ground potential GN
And integrated circuits 8 each including a circuit driven by a potential difference from D. The device according to the first embodiment is a dynamic RAM, and the integrated circuit unit 8 includes:
As main circuits, a memory cell array 9, a word line driving system circuit 10, and a peripheral circuit 11 are provided.

Next, the operation will be described.

After the external power supply is turned on, reference voltage generating circuit 2 generates reference voltage φR, and at almost the same time, power-on reset circuit outputs a reset signal SR of “H” level.
The “H” level reset signal SR is input to the starting circuit 4, and the reference voltage φR is input to the starting circuit 4 and the boosting circuits 5 and 7, respectively. The starting circuit 4 has a reference voltage φ
When the reset signal SR is at the “H” level, the transistor is kept conducting, receiving the input of R and the input of the reset signal SR at the “H” level. The reduced potential φD is supplied to the booster circuits 5 and 7 and the integrated circuit section 8 (word line drive system circuit 10 and peripheral circuit 11) as a high potential power supply. An operation power supply is applied to the booster circuits 5 and 7 by supplying the reduced potential φD. Therefore, conduction occurs, and the boosted potential φ
P1 and φP2 are output. Boost potential φP1
Is input to the source follower type step-down circuit 6, and the boosted potential φ
P2 is supplied to the integrated circuit section 8 (word line drive system circuit 10) as a high potential power supply. The step-down circuit 6 continues to conduct while the boosted potential φP1 is at the “H” level, reduces the applied potential VCC to the reduced potential φD, and continues to output the reduced potential φD. Here, the power-on reset circuit 3 causes the reset signal SR to fall from the “H” level to the “L” level in synchronization with the time from when the power is turned on to when the step-down circuit 6 outputs the step-down potential φD. The start-up circuit 4 cuts off upon receiving the input of the “L” level reset signal SR.
It is output from the start-up circuit 4 in place of the step-down circuit 6.

Next, the configuration of the booster circuits 5 and 7 will be described.

FIG. 2 is a block diagram of the booster circuit 5 for the step-down circuit and the booster circuit 7 for the word line drive system shown in FIG.

The configuration of the booster circuits 5 and 7 shown in FIG.
Since both are the same, they will be described simultaneously with reference to one figure.

As shown in FIG. 2, booster circuits 5 and 7
Is a voltage control circuit 12 for receiving a reference potential φR, controlling the boosted potential φP output from the booster circuits 5 and 7 to a set potential, using the potential difference between the reduced potential φD and the ground potential as an operation power supply, Control signals S0, BS from control circuit 12
0 (the first B indicates an inverted signal), an oscillation circuit 13 for outputting a clock signal CLK for driving the capacitor of the charge pump circuit, and a potential difference between the step-down potential φD and the ground potential as an operation power supply. Clock signal CLK
To a clock signal CLK0 suitable for driving the capacitor of the charge pump circuit,
A charge pump circuit 15 which uses a potential difference between the step-down potential φD and the ground potential as an operation power source, boosts the step-down potential φD to a step-up potential φP under the control of the clock signal CLK0, and outputs
And a feedback path 16 for feeding back the boosted potential φP to the voltage control circuit 12.

Next, the operation of the booster circuit will be described with reference to the circuit configuration of each block.

FIG. 3 is a circuit diagram of the voltage control circuit 12 shown in FIG.

As shown in FIG. 3, the voltage control circuit 12 mainly includes a voltage generator 17 and a control signal generator 18.

After the external power supply is turned on, the reference potential φR is input to the gate of the N-channel MOSFET (hereinafter referred to as NMOS) 19 of the voltage generator 17. Thereby, NMOS
19 becomes conductive, and the drain of the NMOS 19 becomes low potential. N
An “L” level internal voltage signal SC is extracted from the drain of the MOS 19, and the “L” level signal SC is supplied to the input of the inverter 20 of the control signal generator 18. Inverter 20 is driven by the potential difference between step-down potential φD and the ground potential. When the reduced potential φD is supplied to the power supply terminal of the inverter 20, the inverter 20 outputs an “H” level control signal S0. The signal S0 is supplied to an input of the inverter 21. The inverter 21 is also driven by the potential difference between the step-down potential φD and the ground potential, similarly to the inverter 20. Inverter 21 outputs "L" level control signal BS0.

Although a specific circuit for the reference voltage generating circuit 2 is omitted, the reference voltage generating circuit 2 is generally a circuit having a low dependency on an externally applied power supply voltage.

FIG. 4 is a circuit diagram of the oscillation circuit 13 shown in FIG.

As shown in FIG. 4, the oscillation circuit 13 mainly includes five-stage CMOS inverters 22 to 26 connected in series to each other.
And the output of the last-stage inverter 26
22 is a ring oscillator constituted by a feedback path 27 for feeding back to the input of the input 22. These five-stage CMOS inverters 22 to
26 are driven by the potential difference between the step-down potential φD and the ground potential.

The control signal S0 is input to the gate of the PMOS 28 whose source is connected to the power supply terminal to which the reduced potential φD is supplied and whose drain is connected to the input of the second inverter 23. At the same time, the control signal S0 has a source connected to the ground terminal and a drain connected to the NMOS 29 of the first inverter 22.
Is input to the gate of the NMOS 30 connected to the source of the NMOS.

The control signal BS0 has a source connected to the power supply terminal to which the step-down potential φD is supplied, and a drain connected to the source of the PMOS 31 of the second inverter 23.
Input to the gate of OS32. At the same time, the control signal B
S0 is input to the gate of the NMOS 33 whose source is connected to the ground terminal and whose drain is connected to the input of the third inverter 24.

Here, when the control signal S0 is at "H" level,
When S0 is at the "L" level, the PMOS 28 and the NMOS 33 are cut off, and the NMOS 30 and the PMOS 32 are turned on. Therefore, operating power is supplied to the five-stage CMOS inverters 22 to 26, respectively. Therefore, the oscillation circuit 13 is activated, and oscillates a predetermined clock signal CLK.

FIG. 5 is a circuit diagram of the buffer circuit 14 shown in FIG.

As shown in FIG. 5, the buffer circuit 14 is composed of two stages of inverters 33 and 34 connected in series to each other. These two-stage inverters 33 and 34 are each driven by a potential difference between the step-down potential φD and the ground potential.

The clock signal CLK is supplied to the input of the inverter 34, converted into a clock signal CLK0 suitable for driving the charge pump circuit 15, and output from the inverter 35.

FIG. 6 is a circuit diagram of the charge pump circuit 15 shown in FIG.

As shown in FIG. 6, the charge pump circuit 15
Is a power supply terminal supplied with the step-down potential φD and a step-up potential φP
Between the output terminal from which the output is generated and two diodes 36 and 37 connected in series so as to be forward-connected to each other, and one electrode between the cathode of the diode 36 and the anode of the diode 37. It is composed of a capacitor 38 connected to the input terminal to which the other electrode is supplied with the clock signal CLK0, and a capacitor 39 having one electrode connected to the cathode of the diode 37 and the other electrode grounded.

When clock signal CLK0 is input to the other electrode of capacitor 38, the potential of the output node of diode 37 becomes higher than step-down potential φD, and step-up potential φP is generated. This boosted potential φP is fed back to the voltage generator 17 of the voltage control circuit 12 shown in FIG.

As shown in FIG. 3, the voltage generator 17 is provided with resistors 40 and 41 connected in series between a power supply terminal to which the boosted potential φP is supplied and a ground terminal. The interconnection point between the resistors 40 and 41 is the NMOS 42 with the source grounded.
Connected to the gate.

The boosted potential φP is converted to a converted potential φS using resistance division by the resistors 40 and 41. Here, converted potential φS is compared with reference potential φR. NM
The OS 42 cuts off when the boosted potential φP is lower than the set potential, and conducts when it is higher.

When the NMOS 42 is shut off, the voltage generator 17 outputs the internal voltage signal SC at the "L" level, so that the above-described operation is performed and the clock signal C
Since LK and CLK0 are generated, the charge pump circuit 15 keeps raising the reduced potential φD.

On the contrary, when the NMOS 42 is turned on,
Reference numeral 42 denotes a P having a source connected to the power supply terminal to which the applied potential VCC is supplied and a drain connected to the drain of the NMOS 19.
The MOS 43 and the source are connected to the power supply terminal to which the applied potential VCC is supplied, and the PMOS 44 whose drain is connected to the drain of the NMOS 42 is made conductive. Therefore, internal voltage signal SC attains an "H" level, control signal S0 attains an "L" level, and BS0 attains an "H" level. When the control signal S0 goes to "L" level and BS0 goes to "H" level, the NMOS 30 and PMOS 32 of the oscillation circuit 13 shown in FIG.
Is turned off, and the PMOS 28 and the NMOS 33 are turned on. Therefore, no operating power is supplied to the first and second stage inverters 22 and 23, and the inverters are deactivated. In addition, while the control signal BS0 is at the "H" level, an "L" level signal is input to the input of the third stage inverter 24, and the inverter 24 outputs an "H" level signal. to continue. Therefore, the clock signal CLK is not generated, and is fixed at the “H” level. Therefore, the charge pump circuit 15
The step-down potential φD is not boosted.

As described above, although the configurations of boosting circuits 5 and 7 shown in FIG. 1 are the same, boosting potential .phi.P1 for driving the step-down circuit and boosting potential .phi.P2 for the word line driving system circuit are respectively set. , Can be set to another value.
In this case, for example, the size and impedance of the transistor of the buffer circuit 14 and the charge pump circuit 15
The coupling ratio of the capacitor may be adjusted so as to obtain the optimum boosted potential.

Next, the configuration of the source follower type step-down circuit 6 will be described.

FIG. 7 is a block diagram of the source follower type step-down circuit 6 shown in FIG.

As shown in FIG. 7, the step-down circuit 6 has a drain connected to a power supply terminal to which the applied potential VCC is supplied and an NMOS 45 serving as a driver of a source follower type step-down circuit that outputs a step-down potential φD from a source. It is configured. The boosted potential φP1 from the booster circuit 5 is supplied to the gate of the NMOS 45. The source-follower type step-down circuit 6 has a function of generating an internal step-down potential φD by utilizing a threshold drop of the NMOS 45. The output of the step-down circuit 6 has the step-down potential φD, but does not operate when the power is turned on. Therefore, the start circuit 4 is added. The activation circuit 4 is for generating the step-down potential φD when the power is turned on only during the period from the time when the power is turned on until the step-down circuit 6 starts operating.

Next, the configuration of the starting circuit 4 will be described.

FIG. 8 is a circuit diagram of the starting circuit 4 shown in FIG.

When the external power supply is turned on, the starter circuit 4 generates the reduced potential φ before the source follower type step-down circuit 6 operates.
D is generated, and the basic configuration is based on the feedback type step-down circuit.

After the external power supply is turned on, the power-on reset circuit 3 outputs an "H" level reset signal SR.
The "H" level reset signal SR is generated by the gates of the PMOS 46 connected to the power supply terminal to which the applied potential VCC is supplied, and the NMOSs 47 and 48 connected to the ground terminal.
Are supplied to the respective gates. Therefore, immediately after the external power is turned on, the PMOS 46 is shut off, and the NMOS 47 and
48 respectively conduct. Further, the reference potential φR is input from the reference voltage generation circuit 2 to the gate of the NMOS 49. N
The source of the MOS 49 is connected to the drain of the NMOS 47. As a result, the NMOS 49 becomes conductive, and N
The drain of the MOS 49 becomes low potential. From the drain of the NMOS 49, an "L" level internal voltage signal SC0 is extracted. The "L" level signal SC0 is supplied to the gate of the PMOS 51 whose source is connected to the power supply terminal to which the applied voltage VCC is supplied and whose drain is connected to one end of the resistor 50. A resistor 52 is inserted between the other end of the resistor 50 and the drain of the NMOS 48. The PMOS 51 is turned on when the internal voltage signal SC0 at the “L” level is input to the gate. Therefore, the reduced potential φD is output from the interconnection point between the drain of the PMOS 51 and the resistor 50. Further, the gate of the NMOS 53 whose source is connected to the drain of the NMOS 47 is connected to the interconnection point between the resistors 50 and 52. The step-down potential φD is converted into a converted potential φS0 by using resistance division by the resistors 50 and 52. Here, converted potential φS0 is compared with reference potential φR. NMOS 53 is
Cut off when the step-down potential φD is lower than the set potential. As a result, the internal voltage signal SC0 of “L” level continues to be output from the drain of the NMOS 49, and functions to lower the impedance of the PMOS 51 and increase the step-down potential φD to the set potential.

Conversely, when the step-down potential φD becomes higher than the set potential, the NMOS 53 is turned on. NMO
In S42, the source is connected to the power supply terminal to which the applied potential VCC is supplied, the drain is connected to the PMOS 54 connected to the drain of the NMOS 49, the source is connected to the power supply terminal to which the applied potential VCC is supplied, and the drain is connected to the drain of the NMOS 53. The connected PMOSs 55 are made conductive. As a result, internal voltage signal SC0 attains “H” level, and PMO
The function of raising the impedance of S51 and lowering the step-down potential φD to the set potential is performed.

The power-on reset circuit 3 outputs the "H" level when the externally applied power is turned on, and thereafter, at the "L" level when the step-down circuit 6 shown in FIG. 1 outputs the step-down potential φD. Is generated. When the reset signal SR becomes “L” level, PMO
S46 is turned on to set the gate of the PMOS 51 to a high potential,
OS51 is shut off. Further, the NMOSs 47 and 48 are cut off. Therefore, the supply of the operation power to the start circuit 4 is stopped, and the operation is stopped.

Next, the configuration of the integrated circuit section 8 shown in FIG. 1 will be described.

FIG. 9 shows the word line drive system circuit 10 shown in FIG.
FIG. 2 is a circuit diagram of a part of a peripheral circuit 11.

As shown in FIG. 9, a dynamic RAM
As an example of the peripheral circuit 11 of the word line driver selection circuit 56
And a row decoder circuit 57 are shown. Further, as an example of the word line drive system circuit 10, a word line driver circuit for driving one word line with the boosted potential φP2 is shown.

The word line driver selection circuit 56 receives a plurality of address signals, and outputs one decode signal SDWL based on a combination of these address signals.
The ND gate 58 is used. Similarly, the row decoder circuit 57 includes a NAND gate 59 to which a plurality of address signals are input and which outputs one decode signal SWL based on a combination of these address signals. NAND gates 58 and 59 have a reduced potential φD
It is driven by a potential difference between the ground potential.

The decode signal SDWL is supplied to the level shifter 60
And the input of the inverter 61. The decode signal SDWL has a maximum potential of the level shifter 60.
The level is shifted to the amplified signal SD1WL substantially set to the boosted potential φP2.

When the word line driver selection circuit 56 outputs the decode signal SDWL of “H” level, the output of the level shifter 60 supplies the source of the PMOS 62 with the amplified signal SD1WL of “H” level. This allows P
CMOS inverter 64 composed of MOS 62 and NMOS 63
Is supplied with operating power, and the inverter 64 is activated.
After the inverter 64 is activated, in response to the decode signal SWL from the row decoder circuit 57 being “H” or “L”, the maximum potential is almost equal to the boosted potential φP2 to a word line (not shown).
The boosted potential φP2WL is output, and the word line is driven by the boosted potential.

Driver MOSFET for driving word line
However, the P-channel type is a method that has recently attracted attention because a word line can be sufficiently boosted even when an externally applied power supply voltage is low. In this case, as a matter of course, it is desirable that the boosted potential φP2 supplied as a power supply to the word line drive system circuit be stable without a potential change.

The decode signal SWL is also supplied to the level shifter
At 65, the maximum potential is level-shifted to the amplified signal S1WL, which is substantially the boosted potential φP2.

On the contrary, the word line driver selection circuit 56
When the "L" level decode signal SDWL is output, the "L" level amplified signal SD1WL is supplied from the output of the level shifter 60 to the source of the PMOS 62.
As a result, the CMOS inverter 64 has no operating power supply, and the inverter 64 becomes inactive. At this time, the inverter 61 outputs an "H" level signal. This "H" level signal is input to the gate of the NMOS 66 whose drain is connected to the inverter 64 and whose source is grounded. Therefore, N
MOS 66 is turned on, and decode signal SDW of "L" level
While L is being output, the output of the inverter 64 is fixed at the “L” level. This inverter 66 is driven by a potential difference between the step-down potential φD and the ground potential.

FIG. 10 is a circuit diagram of the level shifters 61 and 65 shown in FIG.

The configuration of the level shifters 61 and 65 shown in FIG.
Since both are the same, they will be described simultaneously with reference to one figure.

As shown in FIG. 10, decode signal SDWL
(Or SWL) is supplied to the gate of the NMOS 67 whose source is grounded and the input of the inverter 68.

When the "H" level decode signal SDWL (or SWL) is supplied to the gate of the NMOS 67,
The NMOS 67 is turned on, and the gate of the PMOS 68 whose source is connected to the boosted potential φP2 is set to the low potential. Therefore, PMO
S68 is turned on, and the amplified signal SD1WL (or S1WL) whose maximum potential is almost the boosted potential φP2 is output. Also, the "L" level decode signal SDWL (or SWL)
WL) is supplied to the gate of NMOS 67, NM
OS 67 conducts. At this time, the inverter 68 is set to “H”.
Output level signal. This “H” level signal is
The source is grounded and the drain is supplied to the gate of NMOS 69 connected to the drain of PMOS 68. Therefore, NM
OS 69 is turned on, and the decode signal SDWL at the “L” level
(Or SWL) is output while the level shifter
The output of 60 (or 65) is fixed at the “L” level. This inverter 68 is driven by a potential difference between the step-down potential φD and the ground potential.

The dynamic RAM described in the first embodiment includes an important configuration described below.

FIG. 11 is a schematic block diagram showing only a main part of the dynamic RAM shown in FIG.

First, internal boosting circuits 5 and 7 are driven using the reduced potential φD of internal voltage down converting circuit 6 as an operating power supply. According to the method in which the operation power supply of the booster circuits 5 and 7 is set to the reduced potential φD, the operation of the booster circuits 5 and 7 does not change much even if the externally applied potential VCC fluctuates.
That is, the step-down potential φD is limited at a certain potential level, thereby obtaining a constant potential region where the potential variation is small. If the applied potential VCC changes within the range of the constant potential region, the operating power supply voltages of the booster circuits 5 and 7 do not change. Therefore, the operation margin of the booster circuits 5 and 7 can be secured.

The boosted potential φP is obtained by boosting the reduced potential φD. This not only prevents a change in the internal boosted potential φP due to a change in the external power supply voltage, but also allows the semiconductor integrated circuit device to operate with a wide range of the external power supply voltage.

FIG. 18 shows the characteristics of the internal boosted voltage.
(A) is a characteristic diagram of the internal boosted voltage by the conventional device,
(B) is a characteristic diagram of the internal boosted voltage by the device according to the present invention. As shown in FIG. 18A, the external power supply potential VC
In the internal boosted potential φP obtained by boosting C, as shown by reference numeral A in the figure, the external power supply potential is VCC.
If it fluctuates in the range from a to VCCb, the internal boosted potential φP fluctuates in the range from φPa to φPb.

By limiting the external power supply potential VCC to a certain potential level, as shown in FIG. 18B, an area where the rate of change of the power supply voltage inside the IC is small,
That is, the step-down potential φD in which the constant potential region 100 is obtained is obtained. Then, the step-down potential φD is boosted while reflecting the constant potential region to obtain a step-up potential φP. The boosted potential φP thus obtained has a region (constant potential region) 101 where the rate of change of the power supply voltage inside the IC is small. For this reason, even if the external power supply potential changes from VCCa to VCCb, the boosted potential φP does not change if it changes within the constant potential region 101. Therefore, it is possible to prevent a change in internal boosted potential φP due to a change in external power supply voltage. Further, with this configuration, the semiconductor integrated circuit device can be operated in the same manner without malfunction even when 5 V or 3.3 V is supplied, for example, with a wide range of external power supply voltage. Operation can also be realized.

When the power supply of booster circuits 5 and 7 is set to the output potential of step-down circuit 6, boosted potential φP can be set to be lower than external power supply voltage VCC. Even when external power supply voltage VCC is high, That operation can be guaranteed.

Incidentally, also in the conventional device, the boosted potential φP
The voltage control circuit controls the booster circuit that generates
It is possible to create a region where the rate of change of the boosted potential φP inside is small, but since the boosted potential φP is a potential generated by the booster circuit, it cannot be set lower than the potential VCC which is the power supply of the booster circuit. A region where the rate of change of the boosted potential φP is small can be created only in the region defined. Further, there arises a problem that the oscillation frequency and the current supply capability of the booster circuit change due to the fluctuation of the potential VCC of the power supply of the booster circuit.

Further, in the device according to the first embodiment, the boosted potential φP1 for generating the reduced potential φD for driving the peripheral circuit and the boosted potential φP2 for driving the word line can be controlled independently.

The boosted potential φP1 for generating the reduced potential φD is desirably set in consideration of the operating speed, the current consumption, the timing margin, and the like. The boosted potential φP2 for driving the word line is preferably a memory cell. It is desirable that the potential be set in consideration of the pause characteristics, transfer transistor characteristics, charge / discharge current, reliability, and the like. Therefore, the boosted potential φP1 and the boosted potential φP2 can be independently changed and optimized to improve the characteristics of the entire DRAM.

Furthermore, it is effective to make the booster circuit independent not only in terms of the degree of freedom in setting the DC potential but also in consideration of the AC operation. This is because the boosted potential φP2 supplied to the word line drive system circuit 10 fluctuates with time due to charge and discharge associated with the operation of the word line system circuit. When this boosted potential φP2 is connected to the gate of a MOSFET which is a driver of a source follower type step-down circuit, the step-down potential supplied to the peripheral circuit 11 also fluctuates with the operation of the word line drive system circuit, and This is because the margin is reduced.

In this regard, as shown in FIG. 11, separately from the booster circuit 7 provided for driving the word line drive system circuit, a potential for supplying a potential to the gate of the driver MOSFET of the source follower type step-down circuit 6 is provided. A booster circuit 5 is provided. That is, in the device according to the first embodiment, two power supply systems for supplying the boosted potential are provided. If two power supply systems are provided, the circuit configuration becomes complicated. However, the booster circuit 7 that supplies the boosted potential φP1 to the source follower type step-down circuit 6 may have a very small current capability, so that the chip size increases. It is not something that leads to. Therefore, the operation of the word line drive system circuit 10 can be improved by independently providing the boosted potential φP1 for generating the reduced potential φD and the boosted potential φP2 for driving the word line, rather than the disadvantage that the circuit configuration becomes complicated. The advantage is that the fluctuation of the boosted potential φP1 for generating the reduced potential φD is not caused.

The use of the source follower type step-down circuit 6 makes it possible to compose the step-down circuit relatively simply.
Since the step-down circuits can be easily distributed and arranged at a plurality of locations inside the IC, it is suitable for integration in the IC.

When a source follower type NMOS 45 is used in the source follower type step-down circuit 6 as shown in FIG. 7, it is preferable to supply the boosted potential φP1 to the gate of the NMOS 45.

FIG. 19 shows the characteristics of the internal step-down voltage.
(A) is a characteristic diagram of the internal step-down voltage by the conventional device,
(B) is a characteristic diagram of the internal step-down voltage by the device according to the present invention.

As shown in FIG. 19A, the externally applied voltage V
When the reduced potential φD is obtained by supplying the limited potential VC obtained by limiting CC at a certain potential to the gate of the NMOS 45, the range of the constant potential region 102 of the reduced potential φD is reduced. If the external power supply voltage fluctuates to VCCa beyond the range of the constant potential region 102, the step-down potential φD changes to the step-down potential φDa.

In this regard, as shown in FIG. 19B, when the boosted potential φD is supplied to the gate of the NMOS 45 to obtain the reduced potential φD, the range of the constant potential region 102 of the reduced potential φD is wide. Operating margin can be expanded.

The ideal internal power supply voltage has the same rate of change as the external power supply voltage VCC when the external power supply voltage VCC is low, and the rate of change smaller than the rate when the external power supply voltage VCC is high. It is to show.
That is, it has a characteristic like the step-down potential φD shown in FIG. In order to realize such characteristics, a boosted potential φP1 is supplied to the gate of the NMOS 45. Then, the boosted potential φP1 is increased by the threshold value of the NMOS 45 or more so that the reduced potential φD obtained by dropping by the threshold value of the NMOS 45 has the characteristic shown in FIG. Set to.

Next, a dynamic RAM according to a second embodiment of the present invention will be described.

FIG. 12 is a schematic block diagram showing only a main part of a dynamic RAM according to the second embodiment of the present invention.

As shown in FIG. 12, boosted potential φP2 generated from booster circuit 5 is used as the power supply for word line drive system circuit 10 for driving the word line, and voltage generated from step-down circuit 70 is used as the power supply for peripheral circuit 11. In the apparatus using the reduced potential φD, the reduced potential φD generated from the step-down circuit 70 is used as the power supply of the booster circuit 5.

Even with such a configuration, the booster circuit 5
However, since the step-down potential φD is used as the power supply, the effect that the operation margin can be expanded as in the device according to the first embodiment, particularly as described with reference to FIG. Can be. In this description, as described above, it is desirable that the output of the boosted potential φP2 generated from the booster circuit 5 has a constant potential region similar to the characteristic of the internal step-down potential than the external power supply voltage. It is more suitable to use the output potential φD of the internal step-down circuit than to use the external power supply voltage VCC as it is for the drive power supply 5.

In the device shown in FIG. 12, the boosted potential is divided into a boosted potential φP1 for generating a reduced potential and a boosted potential φP2 for driving an integrated circuit, as in the first embodiment. In the step-up circuit 7 for the step-down circuit, it is not always necessary to be driven by the step-down potential φD. Step-down circuit
Because it only drives 70. Also, the step-down circuit 70
Also, is not limited to the source follower type,
The external power supply potential VCC may be limited to a certain potential level.

Next, a dynamic RAM according to a third embodiment of the present invention will be described.

FIG. 13 is a schematic block diagram showing only a main part of a dynamic RAM according to the third embodiment of the present invention.

As shown in FIG. 13, it is not always necessary to provide two systems for supplying the boosted potential φP.

Even in this configuration, since the booster circuit 5 is driven by using the step-down potential φD as a power supply, similarly to the device according to the first embodiment, particularly referring to FIG. As described above, the effect that the operation margin can be expanded can be obtained.

Next, a dynamic RAM according to a fourth embodiment of the present invention will be described.

FIG. 14 is a schematic block diagram showing only a main part of a dynamic RAM according to the third embodiment of the present invention.

As shown in FIG. 14, there is no need to provide two power supply systems for the boosted potential φP, and the step-down circuit need not be a source follower type.

In this configuration, since the booster circuit 5 is driven by using the step-down potential φD as a power supply, the operation margin can be expanded similarly to the device according to the first embodiment.

The present invention is not limited to the first to fourth embodiments, and various modifications are possible.

FIG. 15 is a circuit diagram showing another example of the word line drive system circuit.

The difference between the word line drive system shown in FIG. 15 and the word line drive system shown in FIG. 9 is that the decode signal SDWL output from the word line driver selection circuit 56 in the circuit shown in FIG. To the voltage signal S by the level shifter 60.
Level shift to D1WL. Then, the inverter 63 whose output is connected to the word line is driven by the level-shifted voltage signal SD1WL, so that the output φP2W
L is output.

On the other hand, in the circuit shown in FIG. 15, the level-shifted decode signal BSD1WL (inverted signal of the decode signal SDWL) from the word line driver selection circuit 56 and the NOR gate 70 having one input as one input are provided. Provided. The other input of the NOR gate 70 is a row decoder circuit.
57, the level-shifted decode signal BS1WL
(Inverted signal of the decode signal SDWL). NOR gate 70 outputs an "H" level signal only when decode signals BSD1WL and BS1WL are both at "L" level. This “H” level signal is made “L” level by the inverter 71. This "L" level signal is input to inverter 64, and its output signal φ2WL is set to "H".
Level. Thus, it may be deformed.

Although not explicitly shown in the above embodiment, the peripheral circuits 11 include those driven by the output of the word line driving step-up circuit φP2. Figure 16 for an example
And the peripheral circuit 11 shown in FIG. Also, N for decoding
AND, for example, NANDs 58 and 59 shown in FIG. 9 and FIG.
The gate of the PMOS constituting the NAND corresponding to FIG.
The level shift circuit as shown in FIG.
In some cases, while a signal having an amplitude of 2 is input, a signal having an amplitude of voltage φD is input to the gate of the NMOS. Further, although not particularly shown, the peripheral circuit 11 includes a circuit driven by the external power supply voltage VCC.

A part of the booster circuit is connected to the external power supply voltage V
It may be driven by CC. For example, when the configuration shown in FIG. 12 is adopted, the booster circuit 7 for the step-down circuit
It may be driven by CC.

Further, a feedback type step-down circuit similar to start-up circuit 4 shown in FIG. 8 may be applied to step-down circuit 6 shown in FIG. When a feedback type step-down circuit is used, a step-up circuit for the step-down circuit is unnecessary.

The starter circuit 4 may be added only when the configuration requires the starter circuit 4 as in the device according to the first embodiment. The starting circuit 4 is basically a step-down circuit.

Although the device according to the first embodiment is an example of a dynamic RAM having a relatively simple configuration, the present invention can be applied to a dynamic RAM having another configuration. . For example, dynamic type R
In AM, different booster circuits are provided for standby (standby) and active (operating) times. However, the present invention can be applied to this configuration.

Further, the present invention provides a dynamic RA
M, semiconductor storage devices other than DRAM,
For example, the present invention is applicable when an EEPROM or the like is provided with both an internal step-down potential generating circuit and an internal step-up potential generating circuit. Further, the present invention can be applied to a microprocessor having a built-in memory.

Further, the present invention can be applied not only to a storage device but also to a logic LSI. This is because the above-described embodiment has the effects described below.

FIG. 20 shows the characteristics of the internal power supply voltage.
(A) is a characteristic diagram of the internal power supply voltage by the conventional device,
(B) is a characteristic diagram of the internal power supply voltage of the device according to the present invention.

If the potential of external power supply potential VCC is limited in order to set internal power supply voltage φ, constant potential region 103 can be obtained as shown in FIG.

On the other hand, as shown in FIG.
If the external power supply potential VCC is limited and the limited potential φL is boosted to set the internal power supply voltage φ,
The range of the constant potential region 103 can be further expanded. Therefore, it is effective in securing an operation margin of the semiconductor integrated circuit device.

Further, according to the method shown in FIG.
Internal power supply voltage φ can be set only to a voltage lower than external power supply voltage VCC.

However, according to the method shown in FIG.
The internal power supply voltage φ can be not only lower than the external power supply voltage VCC but also higher than the external power supply voltage VCC, and various internal power supply voltages can be set. Therefore, the power supply voltage can be set according to a plurality of circuit blocks provided in the semiconductor integrated circuit device and respective purposes. Even in this configuration, even when the external power supply voltage VCC fluctuates, the internal power supply voltage φ is hardly fluctuated.

As described above, the present invention can provide an effective power supply voltage system in a semiconductor integrated circuit which is an external single power supply and has both a booster circuit and a step-down circuit in a chip. This is effective for guaranteeing operation at the power supply voltage VCC.

[0117]

As described above, according to the present invention, it is possible to provide a voltage conversion method for a semiconductor integrated circuit device which can suppress the fluctuation of the internal power supply potential even if the power supply potential applied from the outside fluctuates.

[Brief description of the drawings]

FIG. 1 is a block diagram of a dynamic RAM according to a first embodiment of the present invention.

FIG. 2 is a block diagram of the booster circuit shown in FIG. 1;

FIG. 3 is a circuit diagram of the voltage control circuit shown in FIG. 2;

FIG. 4 is a circuit diagram of the oscillation circuit shown in FIG. 2;

FIG. 5 is a circuit diagram of the buffer circuit shown in FIG. 2;

FIG. 6 is a circuit diagram of the charge pump circuit shown in FIG. 2;

FIG. 7 is a circuit diagram of the source follower type step-down circuit shown in FIG. 1;

FIG. 8 is a circuit diagram of the starting circuit shown in FIG. 1;

FIG. 9 is a circuit diagram of a part of the word line drive system circuit and peripheral circuits shown in FIG. 1;

FIG. 10 is a circuit diagram of the level shifter shown in FIG. 9;

FIG. 11 is a schematic block diagram showing only a main part of the dynamic RAM shown in FIG. 1;

FIG. 12 is a schematic block diagram showing only a main part of a dynamic RAM according to a second embodiment of the present invention;

FIG. 13 is a schematic block diagram showing only a main part of a dynamic RAM according to a third embodiment of the present invention.

FIG. 14 is a schematic block diagram showing only a main part of a dynamic RAM according to a fourth embodiment of the present invention.

FIG. 15 is a circuit diagram showing another example of the word line drive system circuit.

FIG. 16 is a circuit diagram showing another example of the word line drive system circuit.

FIG. 17 is a circuit diagram showing another example of the word line drive system circuit.

FIG. 18 is a diagram showing characteristics of an internal boosted voltage.
(A) is a characteristic diagram of the internal boosted voltage by the conventional device,
(B) is a characteristic diagram of the internal boosted voltage by the device according to the present invention.

FIG. 19 is a diagram showing characteristics of an internal step-down voltage,
(A) is a characteristic diagram of the internal step-down voltage by the conventional device,
(B) is a characteristic diagram of the internal step-down voltage by the device according to the present invention.

FIG. 20 is a diagram showing characteristics of an internal power supply voltage;
(A) is a characteristic diagram of the internal power supply voltage by the conventional device,
(B) is a characteristic diagram of the internal power supply voltage of the device according to the present invention.

FIG. 21 is a diagram showing a conventional dynamic RAM system, FIG. 21 (a) is a diagram showing a bootstrap system,
(B) is a diagram showing a method of driving peripheral circuits by a step-down potential in a bootstrap system, (c) is a diagram showing a method of driving a word line by a boosted potential, and (d) is a diagram showing a method of driving a word line by a boosted potential. FIG. 5 is a diagram illustrating a method in which peripheral circuits are driven by a step-down potential in a method of driving by a step-up potential.

FIG. 22 is a diagram showing an internal power supply system of a conventional dynamic RAM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... IC chip, 2 ... Reference voltage generation circuit, 3 ... Power-on reset circuit, 4 ... Start circuit, 5 ... Boost circuit for step-down circuit, 6 ... Source follower type step-down circuit, 7 ... Boost circuit for word line drive system circuit 8 Integrated circuit section 9 Memory cell array 10 Word line drive system circuit 11 Peripheral circuit 12 Voltage control circuit 13 Oscillator circuit 14 Buffer circuit 15 Charge pump circuit 16 Feedback 17: voltage generator, 18: control signal generator, 22, 23, 24, 25, 26: CMOS inverter, 45: N-channel MOSFET, 56: word line driver selection circuit, 57: row decoder.

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference)

Claims (5)

[Claims] 1. A first step-down circuit converts an externally applied potential to an internal potential having a constant potential region with a small potential variation by limiting the potential applied from the outside to a certain potential level. The internal voltage is raised to an internal boosted potential while reflecting the constant potential region of the internal potential. Before the first step-down circuit operates, the potential applied from the outside is changed to a certain potential level using a second step-down circuit. And converting the internal potential to the internal potential by limiting the internal potential. 2. Using a first step-down circuit, an externally applied potential is converted to an internal potential having a constant potential region with a small potential variation by limiting the potential at an external level to a certain potential level. The internal potential is boosted to a first internal boosted potential used in the internal voltage down converter while reflecting the constant potential area of the internal potential, and the internal potential is reflected in the word line drive system while reflecting the constant potential area of the internal potential. By boosting the voltage to a second internal boosted potential used in the circuit, and by using a second step-down circuit before operating the first step-down circuit, limiting the externally applied potential at a certain potential level A voltage conversion method for a semiconductor integrated circuit device, wherein the voltage is converted to the internal potential. 3. A first step-down circuit converts an externally applied potential to an internal potential having a constant potential region with a small potential variation by limiting the potential applied from the outside to a certain potential level. Is raised to a first internal boosted potential used in an internal voltage down-converting circuit, and the internal potential is reflected in a second internal voltage used in a word line drive system circuit while reflecting a constant potential area of the internal potential. Before the first step-down circuit operates, converting the externally applied potential to the internal potential by limiting the potential applied from the outside to a certain potential level before the first step-down circuit operates. A voltage conversion method for a semiconductor integrated circuit device. 4. A first step-down circuit converts an externally applied potential to an internal potential having a constant potential region with a small potential variation by limiting the potential applied from the outside to a certain potential level. While reflecting the constant potential region of the internal potential, the internal step-down circuit and the internal line-up potential used for the word line drive system circuit are boosted, and the second step-down circuit is used before the first step-down circuit operates. And converting the externally applied potential to the internal potential by limiting the potential to a certain potential level. 5. A first step-down circuit converts an externally applied potential to an internal potential having a constant potential region with small potential fluctuations by limiting the potential applied from the outside to a certain potential level. The internal voltage is boosted to an internal boosted potential used in the word line drive system circuit while reflecting the constant potential area of the internal potential, and is applied from the outside using the second step-down circuit before the first step-down circuit operates. A voltage conversion method for a semiconductor integrated circuit device, comprising converting the applied potential to the internal potential by limiting the potential at a certain potential level.