JP2002016504A - Turbo decoding processing circuit, cdma base station and turbo decoding processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a turbo decoding circuit that can efficiently decode a turbo code with a small memory area. SOLUTION: This invention solves the task by adopting a ring buffer configuration for memories, that respectively store state metric data by the number of trellis states calculated by an ACS(add-compare-select) unit in existence in the inside of a decoder, external information data obtained from each decoder and received data. The ring buffer configuration conducts control of sequentially writing data and control of sequentially reading data required for a succeeding arithmetic operation. Then this ring buffer configuration executes forward processing (α arithmetic operation) and backward processing (β arithmetic operation) and realizes a circuit, that sequentially extracts a soft output decoding result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for decoding turbo-coded data in code division multiple access (CDMA) data transmission, and more particularly to a decoder having a small memory capacity. And a base station comprising the same.

[0002]

2. Description of the Related Art In a code division multiple access (CDMA) system, when burst-like deterioration due to fading occurs, large distortion occurs in information and communication quality deteriorates. Therefore, in order to realize high-quality communication and a large subscriber capacity, it is necessary to overcome burst degradation. Therefore, in CDMA, transmission power control or forward error correction (FEC:
Elemental technologies such as Forward Error Correction) are used.

[0003] In recent years, turbo codes have attracted attention as one of the FECs. The turbo code encodes an information sequence and a sequence obtained by interleaving the sequence in parallel. For this reason, it is said that the turbo code can constitute a code having a performance close to the Shannon limit. If the turbo code is adopted, even in a poor reception environment, it is possible to exhibit a high error correction capability that greatly exceeds the performance of the convolutional code, and it is possible to realize highly efficient transmission.

In particular, when transmitting multimedia data by CDMA, the reception quality is greatly affected by the performance of the error correction code. For this reason, a turbo code having a high error correction capability is currently one of the most noticeable error correction codes in CDMA.

[0005] In decoding a turbo code, an iterative decoding method is employed. Then, by repeating the decoding, it is possible to avoid complication of the device.
Further, as a soft output decoding algorithm applied to turbo decoding, currently, a maximum likelihood decoding method (MAP: Maxi
mum A posterior Probability) is considered the best.

By the way, when the MAP is used, the device scale and the amount of information processing at the time of decoding are increased. For this reason, in practice, a method of obtaining an approximate value of MAP, "Max-l
"og-MAP" is widely adopted as a practical method. If “Max-log-MAP” is used, the device scale and the like can be made smaller than when MAP is used.

[0007]

However, conventionally,
In order to decode the turbo code, a memory area for storing the state metric for the entire decoding length of the trellis calculated from the add comparator (ACS) inside the decoder is required. In addition, "Max-l
Using "og-MAP" reduces the amount of processing, but requires memory for the maximum bit length handled.

The device scale of the Max-log-MAP turbo decoding circuit is determined by the addition comparator (A) of the soft decision decoder.
Forward processing (F: CS: Add Compare Select)
(forward processing) and backward processing (Backw
ard processing), which is almost determined by the memory capacity required to hold the state metric data for the number of trellis states, which is the output of the ard processing.

Here, the "forward processing" is defined as α
Also called an operation, it refers to an operation that executes the Viterbi algorithm from the start point to the end point of data. The “backward processing” is also referred to as β operation, and indicates an operation of executing the Viterbi algorithm from the end point to the start point of data. In addition, the processing of the α operation and the β operation
Also referred to as S processing.

On the other hand, in recent years, memory devices have been reduced in size and performance. However, it is still difficult to secure such a huge memory area only inside the decoder. For this reason, in order to perform turbo decoding by “Max-log-MAP”, it is necessary to add an external memory in addition to the memory inside the decoder. However, when an external memory is added, it becomes difficult to control when access timing between devices becomes extremely fast. Therefore, the addition of the external memory is a factor that hinders an improvement in processing speed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and can efficiently decode data in a small memory area.
Further, it is an object of the present invention to provide a turbo decoding circuit capable of improving the processing speed, a CDMA base station including the same, and a turbo decoding method.

[0012]

According to a first aspect of the present invention, there is provided a turbo decoder processing circuit for a soft output decoder for decoding received data. An adder / comparator for performing forward processing and backward processing based on received data and external information to output state metric data for the number of trellis states, and temporarily storing received data fetched from external received data storage means. Receiving data memory unit for temporarily storing reliability information of the receiving data fetched from an external reliability information storage means, and a state for temporarily storing state metric data A metric memory unit, and a calculation unit that calculates reliability information based on the state metric data and outputs the calculated reliability information to an external reliability information storage unit. The addition comparator performs a forward process on the received data by a fixed bit length, outputs state metric data by a fixed bit length, and the state metric memory unit stores the state metric data by a fixed bit length, After outputting the stored state metric data to the calculation unit, the state metric data for the next fixed bit length is stored.

As described above, according to the present invention, the decoding process is sequentially performed by the constant bit length in the addition comparator, and the contents of the state metric memory are updated by the constant bit length. Therefore, it is not necessary to simultaneously secure all the state metrics of the entire trellis of the turbo code in the memory. Thus, a turbo decoding circuit can be configured with a small memory area, and the circuit scale can be reduced.

Further, according to the present invention, all the state metric data used for one operation in the operation unit at the time of turbo decoding are all stored in the memory inside the soft output decoder. Thereby, at the time of calculation, the access time with the external storage means is reduced, and the processing speed can be improved.

According to the second aspect of the present invention, the reception data memory section includes a plurality of reception data memory buffers, and sequentially stores the reception data in these memory buffers by a predetermined bit length. After the received data stored in the memory buffer is used for forward processing and backward processing, the received data for the next fixed bit length is sequentially stored in the memory buffer, and the reliability information memory unit A memory buffer for reliability information is provided. In these memory buffers, reliability information for a predetermined bit length of received data is sequentially stored, and the reliability information stored in the memory buffer is subjected to forward processing and backward processing. Then, the reliability information for the next fixed bit length is sequentially stored in the memory buffer.

As described above, if the reception data memory and the reliability information memory are also configured as ring buffers and the reception data and the reliability information of each memory buffer are sequentially updated, the memory capacity of the overrun data memory and the reliability information memory can be improved. Can also be reduced.

Furthermore, since the received data and the reliability information used for one operation in the addition comparator are all stored in the memory inside the soft output decoder, this makes the memory internal so that the communication with the outside is possible. The access time is reduced, and the speed of the ACS processing can be improved.

According to the third aspect of the present invention, two addition comparators are provided, and the two addition comparators alternately output the state metric data by a fixed bit length from the head of the received data. Two state metric memory units are provided corresponding to one addition comparator, and the two state metric memory units are configured to alternately output state metric data to the operation unit.

As described above, if two systems of the addition comparator and the state metric memory unit are provided, the processing of the reception data of the next fixed bit length is performed by the other addition comparator while processing is being performed by the other addition comparator. It can be carried out. Thereby, the processing capacity can be improved.

According to the fourth aspect of the present invention, the decoding processing result is held, and every time the turbo decoding processing is repeated,
It is configured to include a repetition number optimizing means for comparing the decoding processing result at the previous iteration with the latest decoding processing result and stopping the turbo decoding processing when these decoding processing results match each other. In this way, if the code processing result is checked each time the decoding processing is repeated, if there is no error in the decoded data before the decoding of the specified number of repetitions is completed in turbo decoding, there is no more meaninglessness. It is possible to prevent repeated decoding processing from being repeated. This makes it possible to speed up the decoding process.

According to the CDMA base station of the present invention, an external reception data storage means for storing reception data, an external reliability information storage means for storing reliability information of the reception data, Turbo decoding means for turbo-decoding received data while updating the reliability information based on the received data stored in the received data storage means and the reliability information stored in the external reliability information storage means; A source extractor for extracting information bits from data decoded by the means, the CDMA base station comprising:
As the turbo decoding means, a turbo decoding processing circuit according to any one of claims 1 to 4 is provided.

As described above, according to the present invention, since the memory capacity can be reduced, the scale of the turbo decoding processing circuit can be reduced. Further, since the ACS processing can be performed only once using only the data stored in the memory inside the soft output decoder, the decoding processing speed can be improved.

According to the turbo decoding method of the sixth aspect of the present invention, the soft output decoder of the turbo decoder processing circuit for decoding the received data performs forward processing based on the received data and external information. And performing backward processing to temporarily store state metric data for the number of trellis states in the state metric memory, calculate reliability information based on the stored state metric data, and output the calculated data. Forward processing is performed for each constant bit length, state metric data is output for each predetermined bit length, and state metric data for a predetermined bit length is stored in a state metric memory unit. After output to the arithmetic unit, the state metric memory unit There a method for storing the state metric data over bit length of.

As described above, according to the present invention, since the memory is configured as a ring buffer and decoding results are sequentially output, decoding can be efficiently performed with a small memory area, and the processing speed can be improved. .

[0025]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] First, an example of the configuration of a CDMA base station provided with a turbo decoding processing circuit according to the present invention of the first embodiment will be described with reference to FIG. As shown in FIG.
The DMA base station includes an antenna 1, a transmission / reception separation unit 2, a reception radio unit 3, a despreading unit 4, a demodulation unit 5, a turbo decoding unit 6 as a turbo decoding processing circuit, and an information extraction unit 7.

Next, the operation of the CDMA base station device will be described. A spread signal transmitted from an external device such as a mobile terminal is received by the antenna 1 and input to the reception radio unit 3 via the transmission / reception separation unit 2. In the reception radio section 3, the reception signal passes through a band-pass filter (BPF) (not shown), and the reception signal from which the out-of-band component has been removed is converted into an intermediate frequency band (IF) by a signal generated by a local oscillator. Is converted.

Further, in the reception radio section 3, the reception signal whose frequency has been changed to the IF band is corrected to an appropriate signal level by an automatic gain control circuit (AGC) (not shown) after passing through the BPF. The quasi-synchronous detection is performed and the frequency is converted to a baseband signal. After passing through a low-pass filter (LPF), the received signal frequency-converted to baseband is
It is D-converted and output as a digital signal.

The reception digital signal output from the reception radio section 3 is despread by the despreading section 4 and output as a narrow-band modulated signal. The demodulation unit 5 demodulates the signal output from the despreading unit 4, performs a predetermined soft decision process, and stores the signal in the reception data memory unit 6.

Subsequently, the turbo decoding unit 8 decodes the data based on the data stored in the received data memory unit 6 and the reliability information stored in the external information memory unit 7. Then, at the time of data decoding, decoding is performed while updating the reliability information of the external information memory unit 7. Subsequently, after decoding, a hard decision process is performed, and the information source extracting unit 9 extracts information bits from the decoded data.

Next, referring to the functional block diagram of FIG.
The configuration of the turbo decoding unit 8 will be described. As shown in FIG. 2, the turbo decoding unit 8 includes a soft output decoder 80, a hard decision processing unit 85, interleave processing units 83 and 83a,
A deinterleave processing unit 84 is provided.
In FIG. 2, the soft-output decoder 80 is separately illustrated as a first decoder 81 and a second decoder 82 for convenience. Note that the first and second soft-output decoders 81 and 82 may be actually realized by one decoder. In FIG. 2, the external information memory unit 7 also includes the first and second reliability memory units 71.
And 72.

Next, the operation of the turbo decoder will be described. Turbo code (coding rate 1/3) obtained from demodulation unit 5
), Soft-decision reception data (inf, parity)
1, parity2) is stored in the reception data memory unit 6, and decoding is performed in the turbo decoding unit 8. When the decoding process is started, first, the ACS of the soft output decoder 80 is executed.
Prior to the ACS processing in the first unit 805 or the ACS 2 unit 806, initialization is performed. In the initial setting, soft decision data inf ′ used by the second decoder 82 is generated by the interleave processing unit 83a, and the second decoder 8
2 is stored.

When the initial setting is completed, the first decoder 81 reads out the soft decision data (inf, parity1) and the external information from the reception data memory 6 and the external information memory 7 outside the turbo decoder 8, respectively. Start decryption. The external information referred to here is any reliability information given in advance (Apriori) to each information bit. Hereafter, this external reliability information is referred to as Ap.
riori.

The reliability information obtained from the first decoder 81 is transmitted to the second decoder 82 by the interleave processing unit 83.
Is stored in the second reliability information memory unit 72 as “Apriori2” used by the user.

Next, in the second decoder 82, the soft decision data (inf ', parity2) and "Apriori2" output from the first decoder 81 are respectively stored in the reception data memory unit 6 and the external information memory unit 7. And starts decoding. The soft output obtained in this way is used in the first decoder 81, and is rearranged in the deinterleave processing unit 84, and is stored in the first reliability information memory unit 71 as "Apriori1". Thereafter, this process is repeated for the set specified number of times, and the hard decision processing unit 85 finally makes a hard decision to terminate the decoding process.

Next, referring to FIG.
Will be described. Although the first and second decoders 81 and 82 are distinguished for explanation, the first decoder 81 will be described because it can be actually realized by one decoder.

As shown in FIG. 3, the first decoder 81 includes an internal reception data memory unit 801, an internal a priori memory unit 802, and a state metric memory unit 80.
3a and 803b. Also,
The first decoder 81 includes two systems of γ operation units 804 for calculating a branch metric from received data and reliability information, and an addition comparator for performing α operation and β operation is also AC
Two systems, an S1 unit 805 and an ACS2 unit 806, are provided.

The first decoder 81 includes an external information calculation unit 808 for calculating reliability information from external information, and an ACS1
(SEL) 807 for switching external information obtained from the external and ACS2, a timing control unit 810 for controlling read / write timing for configuring a memory as a ring buffer, and switching between an external memory and an internal memory. And a switching unit (SEL) 809.

Subsequently, referring to FIG.
The operation of 0 will be described. ACS1 part 805, ACS
2 unit 806, each memory unit 801, 802 and 803a,
The operation timing of 803b is determined by the timing control unit 810.
Is controlled by timing signals 0 to 6 output from.

(1) Control of Internal Apriori Memory Unit 802 (Timing Signal 0) The internal apriori memory unit 802 includes the memory 21 and the control unit 22. The memory 21 includes four memory buffers 21a to 21d for reliability information. Ain1 to Ain4 shown in FIG. 4 mean inputs to the memory buffers 21a to 21d, respectively, and Aout1 to 4 mean outputs from the memory buffers 21a to 21d, respectively.

The control unit 22 controls the use of these memory buffers 21a to 21d in a ring buffer configuration. That is, the control unit 22 sequentially stores the reliability information for a certain bit length of the received data in the memory buffers 21a to 21d, and the reliability information stored in the memory buffer is used for the forward processing and the backward processing. After that, the reliability information for the next fixed bit length is sequentially stored in the memory buffer.

More specifically, the control unit 22 stores “Apriori1” and “Apori1” stored in the external information memory unit 7.
riori2 ”to the internal a priori memory unit 802 (APWA, APWE), and control to read the data (APWD) required for the next operation (A
PRA, APRE).

(2) Control of Internal Reception Data Memory Unit 801 (Timing 1) The internal reception data memory unit 801 includes a memory 11 and a control unit 12. The memory 11 includes four reception data memory buffers 11a to 11d. Also, Rin1 to Rin4 shown in FIG. 4 mean inputs to the memory buffers 11a to 11d, respectively. Also, Rout1 to Rout1
Reference numeral 4 denotes outputs from the memory buffers 11a to 11d, respectively.

The control unit 11 controls the use of these memory buffers 11a to 11d in a ring buffer configuration. That is, the control unit 12 sequentially stores the received data in the memory buffers 11a to 11d by a predetermined bit length, and after the received data stored in the memory buffer is used for the forward process and the backward process, The received data for the next fixed bit length is sequentially stored in the memory buffer.

More specifically, the control unit 12 performs control (RWA, RW) for writing the reception data stored in the external reception data memory unit 6 to the internal reception data memory unit 801.
E), and control (RRA, RRE) for reading data (RWD) necessary for the next operation. When the first decoder 81 executes the soft output decoding process, the control unit 11
Processes the received data of “inf” and “parity1”. Further, when the second decoder 82 executes the soft output decoding process, the control unit 11 sets “Inf”, “Parity”
2).

(3) Addition comparator (Timing 4
And 5) In the embodiments shown in FIGS. 3 and 4, as the addition comparator,
Two ACS units 803a and two ACS units 803b are provided. Then, the addition comparator performs forward processing on the received data by a fixed bit length, and outputs state metric data by a fixed bit length. here,
Two addition comparators ACS1 section 803a and ACS2 section 8
03b alternately outputs the state metric data by a fixed bit length from the head of the received data.

(4) Control of State Metric Memory Unit (Timings 6 and 7) In the embodiment shown in FIGS. 3 and 4, the ACS1 unit 803a
Also, two state metric memory units are provided corresponding to the two addition comparators of the ACS 2 unit 803b.

Then, each state metric memory unit 8
03a and 803b include memories 51 and 61 and control units 52 and 62, respectively. Each of the memories 51 and 61 has memory buffers 51a to s and 61a to 61s corresponding to the Q1 bit length, each having S trellis states. Also, Sin1 and Sin2 shown in FIG.
Means input to the memory buffers 51a-s and 61a-s for the ACS1 unit 805 and the ACS2 unit 806, respectively. Also, Sout1 and Sout2 are memory buffers 51a for ACS1 unit 805 and ACS2 unit 806, respectively.
~ S, means the output from 61a-s.

In order to use these memory buffers 51a-s and 61a-s in a ring buffer configuration, the control units 51 and 62 convert the state metric data for the S state calculated by the decoder internal ACS operation into the internal state data. Control for writing to the metric memory unit 813 and control for reading data necessary for the next operation are performed.

That is, the state metric memory unit stores state metric data of a fixed bit length in each of the memory buffers 51a-s and 61a-s, and outputs the stored state metric data to the arithmetic unit. And state metric data for the next fixed bit length. In this embodiment, the two state metric memory units output state metric data to the arithmetic unit 808 alternately.

In this embodiment, as shown in FIG. 4, the state metric memory area has two surfaces (2 × SQ
1), a reception data memory area, and an Aprili memory area are provided for 4 × Q1 each. Further, in the present embodiment, data necessary for the ACS operation is read from the reception data memory unit 6 or the external information memory unit 7 which is an external storage means, and the data is used for the operation and at the same time, the internal memories 801 and 802 are used as they are. A circuit for storing data in 803a and 803b is realized. As a result, the same data can be processed a plurality of times without being read from outside.

Here, the memory areas of the state metric memory units 803a and 803b for holding the output of the α operation by the ACS1 unit 805 and the ACS2 unit 806 will be described. For example, as shown in FIG. 5, when the number of trellis states is S and the number of time points is Q1, the time point Q1
The capacity of the memory area required to hold the output of the α operation up to (Q1 × S (the number of states)) is equal to the time point. on the other hand,
Regarding the β operation, if the calculation of the α operation is completed before the calculation of the β operation, the soft output information can be calculated while performing the β operation. In addition, in the device scale of the entire turbo decoding, the influence of the number of output bits of the α operation, the number of bits of the β operation output, and the number of bits of the external information passed between decodings may be considered, but it is mentioned here. do not do.

When the data length to be decoded is k,
When external information is obtained for each process for Q1 time, α
The number of calculation repetitions is k / Q1. Except for the last block, the number of ACS processing points in the α operation in one pass memory processing is Q1, and the number of ACS processing points in the β operation is (Q1 + Q2). Therefore, the number of ACS times N required for Max-log-MAP decoding of one post-coded block is given by the following equation (1).

N = S · (k / Q1) · (Q1 + (Q1 + Q2)) = Sk (2 + Q2 / Q1) (1)

As is apparent from the above equation (1), AC
In order to reduce the number N of times S, the value of Q1
Needs to be increased. For example, when the entire trellis is included, Q1 = k (information length), Q2 = v (the number of memories)
And Q2 is sufficiently smaller than Q1. And
If Q2 / Q1 ≒ 0 is approximated, the number of ACS is N = 2Sk
And becomes the minimum value of N. On the other hand, to maintain the decoding characteristics, it is necessary to secure Q2 of a certain size.

Therefore, the memory area for storing the state metric obtained by the α operation is determined by tuning Q1, whereby the device scale (memory capacity) and the amount of calculation (the number of ACS processes) can be exchanged. .

Next, referring to FIGS. 6 and 7, the procedure of the turbo decoding processing circuit of the present invention will be described with k = 320, S = 8, and Q1 =
An example when 32 and Q2 = 96 will be described. FIG. 6 is a diagram showing an ACS operation procedure, and FIG.
It is a figure showing operation timing.

(1) Start of α32-1 calculation in ACS1 section First, each data (address: 0 to 31) is read from the reception data memory section 6 and the first reliability information memory section 71, and the ACS section 805 calculates α. Execute At the same time, the read data (Rin1, Ain1) and the state metric (Sin1) obtained from the operation are stored in the internal memory units 801, 802, 803a, respectively.

(2) Start of β96-1 calculation in ACS1 unit Subsequently, each data (addresses 95 to 64, 63 to 32) is sequentially read from the reception data memory unit 6 and the external information memory unit 7 and calculated. At the same time, each of the internal memory units 81
1812 (Rin2, Ain2, Rin3,
Ain3).

Subsequently, the state metric, external information, and received data (address:
0-15) read out (Sout1, Aout)
1, Rout1). At the same time, “Apriori2” calculated by the external information calculator 808 is stored in the second reliability information memory 72.

(3) Start of α32-2 operation in ACS2 section Subsequently, the operation of ACS2 starts. The external information and received data (address 6) stored in the internal memory by ACS 1 immediately before.
3 to 32) (Rout1, Aout1), and the state metric calculated from the data is stored in the internal memory (Sin2).

(4) Start α32-3 calculation in ACS1. Next, the received data and the external information (addresses 64 to 95) stored in the internal memory are read (Rout1, Aout).
1) The state metric calculated from the data is stored in the internal memory (Sin1). Next, a β933 operation is executed.

(5) Start of β96-2 calculation in ACS2 section Next, data (addresses 127 to 96) are read from the received data and the second reliability information memory information 72, respectively.
The read data is stored in the internal memory at the same time as being used for the operation (Rin4, Ain4).

Next, the received data and the external information (addresses 95 to 64) stored in the internal memory in the above process (2)
Is read out and calculated (Rout3, Aout3). Next, state metrics, external information,
The received data (addresses 63 to 32) is read out, operated, and at the same time, “Apriori2” obtained at that time is stored in the second reliability information memory unit 72. By repeating the above processing, the decoding result can be sequentially extracted.

[Second Embodiment] Next, referring to FIG.
A second embodiment of the present invention will be described. In the second embodiment, a repetition number optimization processing unit 86 is added to the turbo decoding unit 8 of the first embodiment in order to further improve the processing capability of the turbo decoding processing circuit.

In turbo decoding, if there is no error in the decoded data before the decoding for the designated number of repetitions is completed, the further iterative decoding becomes meaningless. Therefore, each time the decoding process is repeated, the result of the decoding is checked to optimize the number of repetitions.

For this purpose, in the second embodiment, in addition to the pipeline processing in the first embodiment, by providing an optimization processing unit 86 for the number of repetitions, the decoding processing is speeded up.

In the repetition number optimization processing unit 86,
Each time the hard decision data obtained from the hard decision processing unit 85 is held as a decoding process result and the turbo decoding process is repeated,
Compare the decryption result of the previous iteration with the latest decryption result, and if these decryption results match,
A flag for stopping the turbo decoding processing function is output, and the decoding process of the decoder 1 is stopped.

If the results of the comparison show that the decoding processing results do not match, the decoding processing is continued.
This comparison is performed each time the decoding process is repeated, and the decoding process is operated until the current number of repetitions obtained from the decoder 2 matches the set number of repetitions.

Thus, in the second embodiment, in addition to the effect of the first embodiment, there is a new effect that the number of repetitions, which is an experimental parameter in turbo decoding, can be handled according to the reception quality.

In the above-described embodiment, an example in which the present invention is configured under specific conditions has been described. However, the present invention can be variously modified. For example, in the above-described embodiment, an example in which four memory buffers are provided has been described. However, in the present invention, the number of memory buffers is not limited to four.

[0071]

As described above in detail, according to the present invention, according to the present invention, the decoding process is sequentially performed by the constant bit length in the adder / comparator, and the content of the state metric memory is changed by the constant bit length. Update by length. Therefore, it is not necessary to simultaneously secure all the state metrics of the entire trellis of the turbo code in the memory. Thus, a turbo decoding circuit can be configured with a small memory area, and the circuit scale can be reduced.

Further, according to the present invention, all the state metric data used for one operation in the operation unit at the time of turbo decoding are all stored in the memory inside the soft output decoder. Thereby, at the time of calculation, the number of accesses to the external storage means is reduced, and the processing speed can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a CDMA base station device according to a first embodiment.

FIG. 2 is a block diagram illustrating a configuration of a turbo decoder according to the first embodiment.

FIG. 3 is a block diagram illustrating a configuration of a soft-output decoder according to the first embodiment.

FIG. 4 is a memory control circuit.

FIG. 5 is a trellis diagram.

FIG. 6 is a diagram showing an ACS operation procedure.

FIG. 7 is a diagram showing ACS operation timing.

FIG. 8 is a block diagram illustrating a configuration of a turbo decoder according to a second embodiment.

[Explanation of symbols]

 Reference Signs List 1 antenna 2 transmission / reception separation unit 3 reception radio unit 4 despreading unit 5 demodulation unit 6 reception data memory unit 7 external information memory unit 8 turbo decoding unit 9 information source extraction unit 80 soft output decoder 81 first decoder 82 first 2 decoder 83, 83a Interleave processing unit 84 Deinterleave processing unit 85 Hard decision processing unit 86 Repetition count optimization processing unit 801 Internal reception data memory unit 802 Internal a priori memory unit 803a, 803b State metric memory unit

Claims (6)

[Claims] 1. A soft output decoder of a turbo decoder processing circuit that decodes received data, performs forward processing and backward processing based on the received data and external information, and obtains a state metric corresponding to the number of trellis states. An addition comparator for outputting data, a reception data memory unit for temporarily storing reception data fetched from external reception data storage means, and reliability information of the reception data fetched from external reliability information storage means. A reliability information memory unit for temporarily storing the external reliability information, a state metric memory unit for temporarily storing the state metric data, and calculating reliability information based on the state metric data. Means for outputting the received data to the receiving data by a constant bit length. Word processing is performed, and state metric data is output for each of the predetermined bit lengths. The state metric memory unit stores the state metric data for the predetermined bit lengths, and transmits the stored state metric data to the arithmetic unit. A turbo decoding processing circuit which stores state metric data for the next constant bit length after outputting. 2. The reception data memory section includes a plurality of reception data memory buffers, and sequentially stores the reception data by the fixed bit length in these memory buffers, and stores the reception data in the memory buffer. After the received data is used for the forward processing and the backward processing, the received data for the next constant bit length is sequentially stored in the memory buffer, and the reliability information memory unit includes a plurality of reliability information memories. , And sequentially stores the reliability information for the fixed bit length of the received data in these memory buffers, and the reliability information stored in the memory buffer is used for the forward processing and the backward processing. After being used, reliability information for the next constant bit length is sequentially stored in the memory buffer. Turbo decoding processing circuit Motomeko 1 wherein. 3. Two addition comparators are provided, and the two addition comparators output state metric data alternately by a fixed bit length from the head of the received data, and correspond to the two addition comparators. 3. The turbo decoding processing circuit according to claim 1, wherein two state metric memory units are provided, and the two state metric memory units output state metric data to the arithmetic unit alternately. 4. When the decoding processing result is held and the turbo decoding processing is repeated, the decoding processing result of the previous iteration is compared with the latest decoding processing result, and if these decoding processing results match, the turbo processing is performed. 4. The turbo decoding processing circuit according to claim 1, further comprising an iterative number optimizing means for stopping the decoding process. 5. An external reception data storage means for storing reception data, an external reliability information storage means for storing reliability information of the reception data, a reception data stored in the external reception data storage means, Turbo decoding means for turbo-decoding the received data while updating the reliability information based on the reliability information stored in the reliability information storage means, and information bits from the data decoded by the turbo decoding means. A CDMA base station comprising an information source extracting unit to be extracted, wherein the turbo decoding unit includes the turbo decoding processing circuit according to any one of claims 1 to 4.
DMA base station. 6. A soft output decoder of a turbo decoder processing circuit for decoding received data, wherein a forward process and a backward process are performed based on the received data and external information, and a state metric corresponding to the number of trellis states is obtained. In temporarily storing data in a state metric memory and calculating and outputting reliability information based on the stored state metric data, the addition comparator performs a forward process on the received data by a predetermined bit length. After outputting the state metric data for each of the predetermined bit lengths, storing the state metric data for the predetermined bit length in the state metric memory unit, and outputting the stored state metric data to the arithmetic unit. The following fixed bit length is stored in the state metric memory unit. A turbo decoding method comprising storing state metric data.