JP2002016224A - Adjusting device for signal timing between functional blocks, and the adjusting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a timing-adjusting device and the adjusting method, by which an LSI containing functional blocks not generate violation for a signal timing limitation between the functional blocks. SOLUTION: When an LSI generates a wire length difference between wires W1 and W2, which connects between functional blocks IPA1 and IPB2 as IPS contained caused by layout and generates a timing limited violation in an input signal of the reception side functional block IPB2 caused by a delayed time difference, the delayed time difference is detected by a delay-detecting circuit 4, which is provided at the functionalal block IPB2 of the reception side, is coded and is fed back to a delay adjusting circuit 3, which is provided at the reception side function block IPA1 via a feed back wire 5 and the timing limited violation, which is generated in the input signal of the reception side functional block IPB2 can be avoided automatically by adjusting the delay time at the reception side functional block IPA1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an IP (Intellectual)
The present invention relates to a signal timing adjustment between function blocks as a property (intellectual property), and in particular, to provide an adjustment device and an adjustment method for adjusting a signal delay in a transmission-side function block.

[0002]

2. Description of the Related Art In recent years, the timing of transmitting and receiving signals between functional blocks constituting an LSI has been speeded up, and accordingly, restrictions on timing between signals have become stricter. In the submicron process technology, signal delay due to wiring becomes dominant, and there may be a difference in signal transmission / reception timing between functional blocks due to the arrangement of functional blocks in a chip and the wiring connecting functional blocks. .

[0003] This problem is particularly important in the case where a function block made IP is reused in another LSI, rather than when a function block specially designed for a specific LSI is mounted on the LSI.

[0004] A problem concerning signal transmission / reception timing which has conventionally occurred between functional blocks will be specifically described with reference to FIG. For example, as shown in FIG. 4, a function block IPA 1 on the transmission side (hereinafter simply referred to as IPA 1) and a function block IPB 2 on the reception side (hereinafter simply referred to as I
PB2) are connected to each other by a long wiring W1 and a short wiring W2.

Here, if IPA 1 and IPB 2 are both IP function blocks, these function blocks are not designed exclusively for an LSI to be developed, so that the layout is In addition, the matching between the functional blocks becomes insufficient. For example, the wiring W1 is a long detour wiring, but the wiring W2 is an ideal linear wiring, and the wiring length is likely to be unbalanced. Therefore, the signal output from the IPA 1 on the transmitting side is changed to the IPA 1 on the receiving side.
There is a problem that a timing constraint violation occurs in B2.

Conventionally, the functional blocks that constitute an LSI are:
Layout considerations are made so that ideal wiring can be obtained by arranging as close as possible. However, in an LSI which is increasing in size year by year, a large number of function blocks are mixed and all the function blocks are ideal. It is difficult to place and wire them. This problem is particularly important when IP is mixed in many functional blocks. For this reason, in recent years, the development of a timing adjustment device and an adjustment method for avoiding violation of timing constraints of signals between functional blocks has become an important issue.

[0007]

As described above, conventionally, when a large number of functional blocks are mixedly mounted on an LSI, especially when a functional block as an IP is included, these are ideally arranged and wired. This makes it difficult to adjust the timing of signals between functional blocks.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a timing adjustment device and an adjustment method that do not cause a signal timing constraint violation between function blocks even when a function block as an IP is included. The purpose is to:

[0009]

SUMMARY OF THE INVENTION According to the present invention, an apparatus and method for adjusting the timing of a signal between functional blocks detects the degree of violation in a receiving-side functional block when a timing constraint violation occurs. It is characterized in that a result is transferred to a function block on the transmission side, and a function of adjusting timing constraint violation in the function block on the transmission side is provided.

Specifically, the signal timing adjusting apparatus according to the present invention includes a transmitting-side functional block, a receiving-side functional block, an output unit of the transmitting-side functional block, and a receiving-side functional block. A timing adjustment device for signals between functional blocks including first and second wirings for connecting the input units to each other, wherein the transmitting-side functional block includes a delay adjusting circuit and the first and second wirings. An output buffer for driving wiring is provided, and the functional block on the receiving side includes:
A delay detection circuit, wherein the delay detection circuit includes the first,
An encoder for detecting a delay time difference of a signal between the second wirings and outputting the code signal is provided, and the code signal output from the encoder is input to a decoder of the delay adjustment circuit.

Preferably, the delay detection circuit includes first and second input terminals for inputting signals of the first and second wirings, respectively, wherein the first input terminal is a functional block on the receiving side. And the second input terminal is connected in parallel to the internal circuit of the receiving-side functional block and each clock terminal of the plurality of flip-flops, respectively. The plurality of flip-flops are adjusted such that the metastable periods are different from each other, and the output terminals of the plurality of flip-flops are respectively connected to buffers having high glitch detection sensitivity, and the output terminal of the buffer is , Are respectively connected to the input terminals of the encoder.

Preferably, the decoder of the delay adjustment circuit includes an input terminal for inputting the code signal, and an output terminal connected in parallel to an enable terminal for activating a plurality of buffers. The output terminals of the plurality of buffers that drive the wiring or the second wiring are connected in parallel with each other, and the decoder selects the number of the buffers that are activated by the input of the code signal. And

Preferably, the code signal is input to an input terminal of the decoder, a control terminal of a selector is connected to an output terminal of the decoder, and the input terminal of the selector is connected to the first and second terminals. It is connected to a connection point of a plurality of buffers connected in series for driving a wiring, and an output terminal of the selector is connected to the first wiring or the second wiring.

A signal timing adjustment method between functional blocks according to the present invention is a timing adjustment method for a plurality of signals transferred between a transmitting side functional block and a receiving side functional block. Detecting the degree of the timing constraint violation in the receiving side functional block, transferring the detection result to the transmitting side functional block, and adjusting the degree of the timing constraint violation in the transmitting side functional block. Is included.

Further, the functional block of the present invention is a functional block for adjusting the timing of signals between the functional blocks of a plurality of wirings connecting the plurality of functional blocks to each other. An output buffer that drives the plurality of wirings, and a delay detection circuit, wherein the delay detection circuit includes an encoder that detects a delay time difference between signals of the plurality of wirings and outputs the difference as a code signal. A code signal output from an encoder of the block is input to a decoder of the delay adjustment circuit.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of a signal timing adjustment device between functional blocks as an IP according to an embodiment of the present invention. Here, the IP is an intellectual property of a functional block having a specific function built in the LSI, and all materials relating to the design of the functional block which requires a long development period when developing the LSI and its derivatives are provided. It is taken over as intellectual assets and reused in the development of new products.

By using the apparatus and method for adjusting signal timing between functional blocks of the present invention described in the following embodiments, a long development period is required when reusing an IP functional block for the development of an LSI and its derivatives. By effectively utilizing known intellectual assets related to the design of required functional blocks, etc., it is possible to contribute to reduction of development costs.

In recent years, since a large number of function blocks are mounted on an LSI, it is not always possible to wire the IP-based function blocks at an ideal shortest distance in a layout.
For this reason, as shown in FIG. 1, the wiring between the functional blocks IPA 1 and IPB 2 as IP in particular becomes unbalanced,
The IPA 1 on the transmitting side and the IPB 2 on the receiving side are connected to each other via a long wiring W1 and a short wiring W2.

As shown in FIG. 1, the IPA 1 on the transmitting side includes a delay adjusting circuit 3, and an output section of the IPA 1 on the transmitting side has an output buffer Buf1 for driving a long wiring W1;
An output buffer Buf2 for driving the short wiring W2 is arranged. The output signals of the IPA 1 are input to the input terminals 6 and 7 of the output buffers Buf1 and Buf2. The receiving-side IPB 2 includes a delay detection circuit 4, and its input terminals are connected to wirings W1 and W2.

FIG. 2 shows the configuration of the delay detection circuit 4. The delay detection circuit 4 has an output terminal E, and its output is output via the feedback wiring 5 shown in FIG.
Function block IPA on the transmission side that controls the delay of Buf2
1 to the delay adjustment circuit 3. At this time, the delay amount for controlling the delay of the output buffers Buf1 and Buf2 is:
It is set by a code signal sent from the delay detection circuit 4 of the function block IPB2 on the receiving side.

That is, the code signal is coded as a delay amount to be adjusted after the difference between the delay time of the long wiring W1 and the delay time of the short wiring W2 is detected by the delay detection circuit 4, and the code signal is transmitted via the feedback wiring 5. Delay adjustment circuit 3
Is forwarded to

As shown in FIG. 2, the input terminal D of the delay detection circuit 4 connected to the long wiring W1 transfers an input signal into the function block IPB2 on the receiving side, and
The flip-flops FF1 to FF4 are respectively connected to data terminals. The input terminal C connected to the short wiring W2 transfers the input signal to the inside of the function block IPB2 on the receiving side and is connected to the clock terminals of the FF1 to FF4 at the same time.

Here, FF1 to FF4 are adjusted so that the metastable periods are different from each other.
The output of F4 is a buffer Gbu having high glitch detection sensitivity.
f1 to Gbuf4 are connected. An encoder 8 is connected to outputs of Gbuf1 to Gbuf4.

Here, the metastable period is a period in which the flip-flop performs an operation of transitioning from 0 to 1 or 1 to 0 and returning to the original state. The glitch is temporarily generated from the flip-flop at this time. A pulse signal that is generated.

A glitch signal is generated from a plurality or one of the FF1 to FF4 due to a delay time difference of an input signal between the input terminals C and D, and the glitch signal is sent to the encoder 8 via buffers Gbuf1 to Gbuf4 having high glitch signal detection sensitivity. Is entered. The encoder 8 encodes, for example, four inputs and outputs them to the terminal E. In this way, the delay time difference of the input signal between the input terminals C and D is coded and fed back to the delay adjustment circuit 3.

On the input side IPA 1, on the output side IPB 2
The delay of the output buffers Buf1 and Buf2 is adjusted using the code signal fed back from the
A timing violation is prevented from occurring in B2.

FIG. 3A shows a circuit configuration in which the delay adjustment circuit 3 included in the IPA 1 on the input side is combined with the output buffer Buf1 or Buf2. In FIG. 3A, the decoder 9 corresponds to the delay adjustment circuit 3, and the buffers 10 to 12 connected in parallel are Buf1 or Buf1.
Equivalent to 2. The output signal of the IPA 1 is input to the input terminals 13 of the buffers 10 to 12 connected in parallel. The wiring W1 or W2 is connected to the output terminals 14 of the buffers 10 to 12.

The code signal fed back from the terminal E of the encoder 8 in the delay detection circuit 4 is decoded by the decoder 9 and input to the enable terminals of the buffers 10 to 12. In this way, the number of active buffers 10 to 12 connected in parallel is selected by the code signal. As the number of the selected buffers 10 to 12 increases, the driving capability of Buf1 or Buf2 increases, and the signal propagation delay time of the wiring W1 or W2 decreases.

Further, in the circuit shown in FIG.
The decoder 15 corresponds to the delay adjustment circuit 3, and the selector 16
Buffers 17 to 20 connected in series with Buf1,
Or it corresponds to Buf2. The code signal fed back from the terminal E of the encoder 8 in the delay detection circuit 4 is decoded using the decoder 15 and input to the control terminal of the selector 16.

The input terminal of the selector 16 is connected to each connection point of the buffers 17 to 20 connected in series, selects the number of the buffers 17 to 20 connected in series, and connects the output terminal 22 of the selector 16 to the wiring W1. , Or W2.

Since the delay time in Buf1 or Buf2 increases as the number of selected buffers 17 to 20 increases, if the circuits shown in FIGS. 3A and 3B are used, the signal on wiring W1 or W2 Can be automatically adjusted.

The present invention is not limited to the above embodiment. For example, in FIG. 1, IPA 1 and I
Although the case where the wirings W1 and W2 connecting the PA 2 are composed of the long wiring W1 and the linear short wiring W2 has been described, the present invention is similarly implemented if there is a difference in delay time between the wirings W1 and W2. be able to.

Although the case has been described where IPA 1 and IPA 2 are function blocks as IPs, the present invention is not necessarily limited to two IPs. The present invention can be similarly applied to a plurality of functional blocks as IP. Further, these functional blocks need not always be IP, and it goes without saying that the present invention can be applied to a normal functional block built in an LSI or a mixed functional block as IP. Nor.

The delay detection circuit described with reference to FIG. 2 and the delay adjustment circuit and buffer described with reference to FIG. 3 are merely examples, and various other circuits may be used. Can be. In addition, various modifications can be made without departing from the scope of the present invention.

[0035]

As described above, by using the apparatus and method for adjusting the timing of signals between functional blocks according to the present invention, when a timing constraint violation occurs in a signal between a plurality of functional blocks incorporated in an LSI, The degree of the violation is detected by the function block on the receiving side, and this is coded and fed back to the function block on the transmitting side, and the timing is adjusted in the function block on the transmitting side to automatically avoid the timing constraint violation. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a signal timing adjustment device between functional blocks according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a delay detection circuit in a reception-side functional block.

FIG. 3 is a diagram illustrating a combination of a delay adjustment circuit and a buffer circuit in a transmission-side functional block, and FIG.
9 is a diagram showing a combination of a decoder and a buffer circuit connected in parallel. (B) is a diagram showing a combination of a decoder, a selector, and a buffer circuit connected in series.

FIG. 4 is a diagram showing a wiring that causes a difference in signal timing between conventional functional blocks.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Input side functional block IPA 2 ... Output side functional block IPB 3 ... Delay adjustment circuit 4 ... Delay detection circuit 5 ... Feedback wiring 6, 7 ... Input terminal of Buf1, Buf2 8 ... Encoder 9, 15 ... Decoder 10, 11, 12 ... parallel connection buffer circuit 13 ... input terminal of parallel connection buffer circuit 14 ... output terminal of parallel connection buffer circuit 16 ... selector 17, 18, 19, 20 ... series connection buffer circuit 21 ... input terminal of series connection buffer circuit 22 ... output terminal of series connected buffer circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (6)

[Claims] 1. A function block on a transmission side, a function block on a reception side, and first and second wirings interconnecting an output section of the function block on the transmission side and an input section of a function block on the reception side. A timing adjustment device for signals between functional blocks, comprising: a function block on the transmission side includes a delay adjustment circuit; and an output buffer for driving the first and second wirings. The functional block includes a delay detection circuit, the delay detection circuit includes an encoder that detects a delay time difference between signals of the first and second wirings and outputs a code signal, and the code output from the encoder. A signal timing adjusting device between functional blocks, wherein a signal is input to a decoder of the delay adjusting circuit. 2. The delay detection circuit includes first and second input terminals for inputting signals of the first and second wirings, respectively, wherein the first input terminal is a functional block on the receiving side. The second input terminal is connected in parallel with the internal circuit of the plurality of flip-flops and the clock terminal of the plurality of flip-flops, respectively. The plurality of flip-flops are adjusted so that the metastable periods are different from each other, and the output terminals of the plurality of flip-flops are respectively connected to buffers having high glitch detection sensitivity, and the output terminal of the buffer is 2. The signal timing adjustment between functional blocks according to claim 1, wherein the signal timings are connected to input terminals of the encoder. Location. 3. A decoder of the delay adjustment circuit, comprising: an input terminal for inputting the code signal; and an output terminal connected in parallel to an enable terminal for activating a plurality of buffers; Alternatively, output terminals of the plurality of buffers for driving a second wiring are connected in parallel with each other, and the decoder selects the number of the plurality of buffers activated by the input of the code signal. The signal timing adjusting device between functional blocks according to claim 1. 4. The input terminal of the decoder receives the code signal, the output terminal of the decoder is connected to a control terminal of a selector, and the input terminal of the selector is connected to the first and second wirings. 2. The functional block according to claim 1, wherein the output terminal of the selector is connected to the first wiring or the second wiring, and the output terminal of the selector is connected to a connection point of a plurality of serially connected buffers to be driven. Signal timing adjustment device between. 5. A method for adjusting the timing of a plurality of signals transferred between a function block on a transmission side and a function block on a reception side, the method comprising: A block detecting the block; transferring the detection result to a function block on the transmission side; and adjusting the degree of the timing constraint violation in the function block on the transmission side. Signal timing adjustment method between. 6. A function block for adjusting a timing of a signal between respective function blocks of a plurality of wirings interconnecting the plurality of function blocks, wherein the function block drives a delay adjustment circuit and the plurality of wirings. An output buffer, and a delay detection circuit, wherein the delay detection circuit includes an encoder that detects a delay time difference between signals of the plurality of wirings and outputs a code signal, and is output from an encoder of another functional block. A functional block, wherein a code signal is input to a decoder of the delay adjustment circuit.