JP2002016117A - Semiconductor wafer provided with processing temperature measuring method and temperature measuring method of semiconductor wafer - Google Patents

Semiconductor wafer provided with processing temperature measuring method and temperature measuring method of semiconductor wafer

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Publication number
JP2002016117A
JP2002016117A JP2000196266A JP2000196266A JP2002016117A JP 2002016117 A JP2002016117 A JP 2002016117A JP 2000196266 A JP2000196266 A JP 2000196266A JP 2000196266 A JP2000196266 A JP 2000196266A JP 2002016117 A JP2002016117 A JP 2002016117A
Authority
JP
Japan
Prior art keywords
temperature
wafer
semiconductor wafer
thermocouple
temperature measuring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000196266A
Other languages
Japanese (ja)
Inventor
Shigeru Tsunoda
茂 角田
Kiyoshi Ogata
潔 尾形
Hisayuki Kato
久幸 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000196266A priority Critical patent/JP2002016117A/en
Publication of JP2002016117A publication Critical patent/JP2002016117A/en
Pending legal-status Critical Current

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  • Measuring Temperature Or Quantity Of Heat (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve a problem that the intra-face distribution of a wafer temperature which hourly changes and is required to be accurately measured by an RTA process cannot precisely be measured in a conventional method. SOLUTION: The intra-face distribution of the wafer temperature which hourly changes a real time basis can be measured by providing a thin film-like temperature measuring element for a semiconductor wafer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体製造工程のう
ち、熱処理を伴う工程に関わり、処理温度の測定を行う
ことにより、ウェハ処理温度面内均一性のチェックや熱
処理装置において温度均一性の調整等に用いられる半導
体ウェハに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process involving a heat treatment in a semiconductor manufacturing process. By measuring a process temperature, it is possible to check the uniformity in a wafer process temperature plane and to adjust the temperature uniformity in a heat treatment apparatus. The present invention relates to a semiconductor wafer used for a semiconductor device.

【0002】[0002]

【従来の技術】熱処理工程は半導体製造において重要な
工程の一つである。特に近年は従来から行われている昇
温・降温に長時間を要するバッチ式の炉体による加熱
(FA)に代わって、短時間で昇温・降温が可能な枚葉
式の急速加熱(RTA)が用いられるようになってき
た。加熱方式の変化は酸化膜の薄膜化や新材料容量膜
(PZT,BST)の必要性等、新しい製造プロセスの
出現によるものである。
2. Description of the Related Art A heat treatment step is one of the important steps in semiconductor manufacturing. In particular, in recent years, a single-wafer rapid heating (RTA) capable of raising and lowering the temperature in a short time has replaced the batch type heating (FA) that requires a long time for raising and lowering the temperature, which has been conventionally performed. ) Has come to be used. The change in the heating method is due to the emergence of a new manufacturing process, such as the need for thinner oxide films and the need for new material capacitance films (PZT, BST).

【0003】熱処理工程において、最も重要なことはウ
ェハ温度の正確な管理である。そのため、FA、RTA
どちらの加熱方式においてもウェハ温度を正確に測定
し、熱源を制御することにより、所望の温度プロファイ
ルを得られるように装置開発・改良が行われてきた。装
置制御用の温度モニターとしては従来から熱電対や放射
温度計が用いられてきた。ところでこれらの温度モニタ
ーは熱電対が接触している点近傍や放射温度計が観測し
ている領域の平均値しか測定することができない。ま
た、熱電対は金属汚染などの可能性からウェハ裏面に接
触させることが多いため、測定対象の温度に対する時間
応答性も悪い。炉内温度の測定方法としては適用可能温
度が酸化、アニールプロセスに使用できるかどうかは別
として特開平6−265414号公報に示されるBi/
Sb超格子に発生する熱起電力から温度を測定する方
法、特開平6−283589号公報に示されるシリコン
基板表面のダングリングボンドに吸着している原子の脱
離速度から温度を求める方法、特開平7−27634号
公報に示されるウェハ支持部材の熱膨張から温度を求め
る方法等が挙げられる。しかしながらこれらの方法では
汚染などの問題から使用できる工程が限られることもあ
る。
[0003] In the heat treatment process, the most important thing is accurate control of the wafer temperature. Therefore, FA, RTA
In both heating methods, the apparatus has been developed and improved so that a desired temperature profile can be obtained by accurately measuring the wafer temperature and controlling the heat source. Conventionally, thermocouples and radiation thermometers have been used as temperature monitors for device control. By the way, these temperature monitors can measure only the average value in the vicinity of the point where the thermocouple is in contact or in the area observed by the radiation thermometer. Further, since the thermocouple is often brought into contact with the back surface of the wafer due to the possibility of metal contamination, the time response to the temperature of the object to be measured is poor. Regarding the method of measuring the temperature inside the furnace, Bi / Japanese Patent Application Laid-Open No. 6-265414 describes whether the applicable temperature can be used for the oxidation and annealing processes.
A method of measuring a temperature from a thermoelectromotive force generated in an Sb superlattice, a method of obtaining a temperature from a desorption rate of an atom adsorbed on a dangling bond on a silicon substrate surface disclosed in JP-A-6-283589, Japanese Patent Application Laid-Open No. 7-27634 discloses a method of obtaining a temperature from the thermal expansion of a wafer supporting member. However, in these methods, steps that can be used may be limited due to problems such as contamination.

【0004】ウェハ温度の正確な管理という意味ではウ
ェハ温度の面内均一性も重要である。FAプロセスでは
ウェハとウェハ雰囲気がほぼ熱平衡状態を保って温度変
化するので、昇温・降温時のウェハ温度の面内分布も定
常時の面内分布に準じていると考えられる。従って温度
均一性のチェックは定常時の面内温度分布を均一にすれ
ば良く、熱処理によってできた酸化膜の膜厚やシリサイ
ド膜のシート電気抵抗の変化などを測定すれば十分であ
った。一方、RTAプロセスはサーマルバジェットの管
理が容易で前述の新プロセスへの適用性が高い。しかし
ウェハとウェハ雰囲気が熱的に非平衡な状態で加熱され
るために、プロセス中にウェハ温度の面内分布が生じ易
い。加えて温度が急激に変化する昇温・降温中と定常状
態ではまったく別の面内分布を示す。RTAを用いるプ
ロセスでは昇温時や定常状態に切り替わる前後が結晶成
長の核形成など、プロセスの成否を左右するため、歩留
まり向上のためには昇温・定常時の面内温度分布の均一
性は特に重要である。ところが、従来の酸化膜厚やシー
ト電気抵抗の変化を用いた測定方法ではRTAプロセス
の昇温・降温、定常時それぞれにおけるウェハ温度の面
内分布を得ることができない。なぜなら、これらの測定
で得られるものは昇温・定常・降温のステップを経た結
果であり、各ステップにおいて面内温度分布は時間変化
するからである。
[0004] In terms of accurate control of the wafer temperature, in-plane uniformity of the wafer temperature is also important. In the FA process, since the temperature of the wafer and the wafer atmosphere change while maintaining a substantially thermal equilibrium state, it is considered that the in-plane distribution of the wafer temperature at the time of temperature rise / fall also conforms to the in-plane distribution at the steady state. Therefore, the temperature uniformity can be checked by making the in-plane temperature distribution in a steady state uniform, and it is sufficient to measure the change in the thickness of the oxide film formed by the heat treatment and the change in the sheet electric resistance of the silicide film. On the other hand, the RTA process can easily manage the thermal budget and is highly applicable to the above-described new process. However, since the wafer and the wafer atmosphere are heated in a thermally non-equilibrium state, an in-plane distribution of the wafer temperature easily occurs during the process. In addition, it shows completely different in-plane distributions during the temperature rise / fall and the steady state where the temperature changes rapidly. In the process using RTA, the success or failure of the process such as nucleation of crystal growth depends on whether the temperature rises or before and after switching to the steady state. In order to improve the yield, the uniformity of the in-plane temperature distribution during the temperature rise and steady state is important. Of particular importance. However, the conventional measurement method using the change in the oxide film thickness or the sheet electric resistance cannot obtain the in-plane distribution of the wafer temperature at the time of the temperature increase / decrease of the RTA process and the steady state. This is because what is obtained by these measurements is the result of going through steps of temperature rise, steady state, and temperature drop, and the in-plane temperature distribution changes with time in each step.

【0005】時々刻々変化するRTAプロセス中のウェ
ハ温度の面内分布を測定するために、熱処理を行う直前
のウェハ表面に熱電対の先端を埋め込んだウェハを用い
ることとした。この種のウェハとして、アメリカ合衆国
のSensarray社がダミーウェハに複数の熱電対
を埋め込んだ形で製品として取り扱っている。そこで我
々は、Sensarray社に依頼して熱処理をかける
直前までの膜構造を作り込んだウェハに熱電対を図1の
各点に埋め込んでもらい、RTAプロセス中のウェハ温
度の面内分布を測定することとした。時間応答性を改善
するために、熱電対は測定対象膜に直接埋め込んであ
る。このようにして作成したウェハを用いてウェハ温度
の面内分布を測定した例を図2に示す。同時にウェハの
中心に対する他4点の温度差も併記した。この測定の結
果、ウェハ温度の面内分布はプロセス中に時々刻々変化
していることが確認された。また、この測定によってウ
ェハ温度の面内分布は昇温・降温レートやガス流量、ガ
ス種に依存することが確認された。ウェハ面内の温度分
布を測定することを前提に考えられた公知例としては、
密封空間に閉じこめられた気体の膨張を利用したもの
(特開平5−335284号公報)、本発明の請求項の
一部と同様、熱電対を用いたもの(特開平6−3105
80号公報)、光の反射率が温度によって異なることを
利用したもの(特開平8−313368号公報)が挙げ
られる。これらのうち、気体の膨張を用いた特開平5−
335284号に記載の方法は、レーザー変位計等、非
接触の温度測定手段を熱処理装置に備えなければなら
ず、汎用性に欠ける。また、気体を密封する空間の大き
さ、密度によってはウェハ面内の熱伝導を阻害するた
め、実際の製品との誤差が大きくなってしまうことも懸
念される。光の反射率を利用した特開平8−31336
8号も光照射−検出手段を備えなければならないという
欠点がある。さらに光学的に透明な物質については温度
を測定できないという問題もある。熱電対を利用した特
開平6−310580号記載の方法は本発明で述べた熱
電対を用いた方法と同様であるが、熱電対の確実な形成
という点で本発明に劣る。
In order to measure the in-plane distribution of the wafer temperature during the RTA process, which changes every moment, a wafer having a thermocouple tip embedded in the surface of the wafer immediately before the heat treatment is used. As such a wafer, Sensarray of the United States of America deals with a dummy wafer in which a plurality of thermocouples are embedded. Therefore, we asked Sensarray to embed a thermocouple at each point in Fig. 1 on a wafer with a film structure just before heat treatment, and measure the in-plane distribution of the wafer temperature during the RTA process. I decided that. In order to improve the time response, the thermocouple is embedded directly in the film to be measured. FIG. 2 shows an example in which the in-plane distribution of the wafer temperature is measured using the wafer thus prepared. At the same time, the temperature differences at the other four points with respect to the center of the wafer are also shown. As a result of this measurement, it was confirmed that the in-plane distribution of the wafer temperature changed every moment during the process. In addition, this measurement confirmed that the in-plane distribution of the wafer temperature depends on the temperature rise / fall rate, the gas flow rate, and the gas type. Known examples considered on the assumption that the temperature distribution in the wafer surface is measured include:
Utilizing expansion of gas confined in a sealed space (JP-A-5-335284), and using a thermocouple as in some of the claims of the present invention (JP-A-6-3105)
No. 80) and one utilizing the fact that the reflectance of light varies depending on the temperature (Japanese Patent Application Laid-Open No. 8-313368). Of these, Japanese Patent Application Laid-Open No.
In the method described in JP-A-335284, a non-contact temperature measuring means such as a laser displacement meter must be provided in the heat treatment apparatus, and the method lacks versatility. Further, depending on the size and density of the space for sealing the gas, heat conduction in the wafer surface is hindered, and there is a concern that an error from an actual product may increase. JP-A-8-31336 using light reflectance
No. 8 also has the disadvantage that it must be provided with light irradiation-detection means. Another problem is that the temperature cannot be measured for an optically transparent substance. The method described in JP-A-6-310580 using a thermocouple is the same as the method using a thermocouple described in the present invention, but is inferior to the present invention in that a thermocouple is reliably formed.

【0006】[0006]

【発明が解決しようとする課題】さて、前記の実験にお
いてRTAプロセスの構築においては、昇温・降温レー
トやガス流量、ガス種、プロセス時間だけでなく、ウェ
ハに入射する熱量の面内分布にも注意する必要があるこ
とがわかった。そのため、通常のRTA装置は入熱分布
を調整するための手段を備えている。しかしながら、ウ
ェハ温度の面内分布を測定する手段の開発が不十分であ
る。ウェハ温度の面内分布は時間的に変化するので、従
来FAプロセスの面内均一性向上の目的で用いられてき
た酸化膜厚やシート電気抵抗の変化量を利用した測定法
は不適である。ウェハ温度面内分布の時間変化をリアル
タイムで得る方法としては、上記実験で用いた熱電対を
埋め込んだウェハを用いることが考えられる。しかしこ
の方法も測定点数が増えると信号を取り出すためのケー
ブルが入熱の妨げとなり(例えばランプ加熱の場合、ウ
ェハ上に影を作ってしまう)、均一性の測定を乱してし
まう。従って、RTAプロセスにおいて面内均一性を向
上させるためには、入熱やウェハ面内の熱伝導を妨げな
いウェハ温度の多点測定が必要である。測定点数はウェ
ハ径やチップ面積によって異なるが最低でも15点以上
は必要と思われる。また、熱伝導による時間応答の遅れ
を解消するために温度測定子はできるだけ小さいことが
望まれる。
By the way, in the construction of the RTA process in the above experiment, not only the temperature rise / fall rate, the gas flow rate, the gas type, the process time, but also the in-plane distribution of the amount of heat incident on the wafer. It turns out that you also need to be careful. Therefore, a normal RTA apparatus is provided with a means for adjusting the heat input distribution. However, the means for measuring the in-plane distribution of the wafer temperature is insufficiently developed. Since the in-plane distribution of the wafer temperature changes with time, the measurement method using the change in the oxide film thickness or sheet electric resistance, which has been conventionally used for the purpose of improving the in-plane uniformity of the FA process, is not suitable. As a method of obtaining the time change of the wafer temperature distribution in real time, it is conceivable to use a wafer in which the thermocouple used in the above experiment is embedded. However, also in this method, when the number of measurement points increases, a cable for extracting a signal hinders heat input (for example, in the case of lamp heating, a shadow is formed on a wafer), and the uniformity measurement is disturbed. Therefore, in order to improve the in-plane uniformity in the RTA process, it is necessary to perform a multi-point measurement of the wafer temperature that does not hinder heat input and heat conduction in the wafer surface. The number of measurement points varies depending on the wafer diameter and chip area, but at least 15 points are considered necessary. Further, it is desirable that the temperature measuring element be as small as possible in order to eliminate the delay of the time response due to heat conduction.

【0007】[0007]

【課題を解決するための手段】上記課題を解決されるた
めの手段として、熱電対や電気抵抗変化等により温度を
測定する温度測定素子を薄膜化して作り込んだ半導体ウ
ェハが考えられる。通常の半導体デバイスと同様に成
膜、レジスト塗布、露光、エッチングといった工程を繰
り返し用いることで作り込んだ薄膜状の温度測定素子は
小型であるために時間応答性も向上し、多点測定にも対
応させやすい。また信号線を取り出すためのパッドをウ
ェハ端部に設け、そこまでの配線もウェハ製造プロセス
で作り込むことによって入熱やウェハ面内の熱伝導を妨
げない構造にすることができる。
As a means for solving the above-mentioned problems, a semiconductor wafer in which a temperature measuring element for measuring a temperature by a thermocouple, a change in electric resistance, or the like is formed into a thin film is considered. Thin film-shaped temperature measuring elements made by repeatedly using processes such as film formation, resist coating, exposure, and etching, like ordinary semiconductor devices, are small in size, so their time response is improved, and they can be used for multipoint measurement. Easy to correspond. Further, by providing a pad for taking out a signal line at the edge of the wafer and forming wiring up to that end in the wafer manufacturing process, a structure that does not hinder heat input and heat conduction in the wafer surface can be obtained.

【0008】[0008]

【発明の実施の形態】図3に本発明の第一の実施例を示
す。ここではプロセス構築用TEGウェハ、または装置
QC用として用いることが可能となるように、ウェハ全
面に熱電対を作り込んだ例を示す。31は薄膜で作り込
んだ熱電対の1素子である。32は熱電対の信号を取り
出すためのパッド部である。これを拡大した平面図、断
面図が図4(a)、(b)である。41は第一の金属膜
Aで、42は第2の金属膜Bであり、これによって熱電
対を形成している。この素子の製造工程は図5の通りで
ある。まず酸化膜など下地膜の上に金属膜A(41)を
スパッタ、CVDなどにより形成する。レジスト(5
1)塗布、露光、エッチングにより金属膜Aと必要に応
じて金属膜Aでできた微細配線パターンを形成する。次
にSiO2等の層間絶縁膜(44)を堆積し、再びエッ
チングにより熱電対及び信号線取り出しのためのパッド
を形成するためのコンタクトホール(52)を形成す
る。さらに金属膜B(42)を堆積させ、エッチングに
より熱電対と金属膜Bによる配線パターンを形成する。
保護膜(53)は温度測定対象が金属膜の場合など必要
に応じて形成する。また、温度測定対象が金属膜Bの場
合には図6のような方法で熱電対を形成することも可能
である。この場合には金属膜Aからの信号線取り出しの
ためのパッドを形成するためのコンタクトホールを層間
絶縁膜だけでなく金属膜Bにも形成する必要がある。図
4、6の様な構造とすることで二種の金属の接合を密な
ものとし、確実に熱電対を形成することができる。ま
た、熱電対からの信号を取り出すための配線層を2段構
造にすることでウェハ面積に対する熱電対・配線の占め
る割合を最小限にすることができ、配線層によるウェハ
面内での熱伝導や外部からの入熱を妨げにくくする。こ
こではパッド部がウェハ端部にある例を示したが、パッ
ド部が熱電対の近傍にあっても構わない。
FIG. 3 shows a first embodiment of the present invention. Here, an example is shown in which a thermocouple is formed on the entire surface of the wafer so that it can be used for a TEG wafer for process construction or for a device QC. 31 is a thermocouple element made of a thin film. Reference numeral 32 denotes a pad for extracting a signal from the thermocouple. FIGS. 4A and 4B are enlarged plan views and cross-sectional views. 41 is a first metal film A and 42 is a second metal film B, which forms a thermocouple. The manufacturing process of this element is as shown in FIG. First, a metal film A (41) is formed on a base film such as an oxide film by sputtering, CVD, or the like. Resist (5
1) A metal film A and, if necessary, a fine wiring pattern made of the metal film A are formed by coating, exposing, and etching. Next, an interlayer insulating film (44) such as SiO2 is deposited, and a contact hole (52) for forming a pad for taking out a thermocouple and a signal line is formed by etching again. Further, a metal film B (42) is deposited, and a wiring pattern of the thermocouple and the metal film B is formed by etching.
The protective film (53) is formed as necessary, for example, when the temperature measurement target is a metal film. When the temperature measurement target is the metal film B, a thermocouple can be formed by a method as shown in FIG. In this case, a contact hole for forming a pad for taking out a signal line from the metal film A needs to be formed not only in the interlayer insulating film but also in the metal film B. With the structure as shown in FIGS. 4 and 6, the junction between the two metals can be made dense, and a thermocouple can be reliably formed. In addition, the ratio of the thermocouple / wiring to the wafer area can be minimized by forming the wiring layer for extracting signals from the thermocouple in a two-stage structure, and the heat conduction in the wafer surface by the wiring layer can be minimized. And heat input from the outside is hardly hindered. Here, an example is shown in which the pad portion is located at the edge of the wafer, but the pad portion may be located near the thermocouple.

【0009】ここでは熱電対をウェハ全面に作り込んだ
が、図7に示すように製品用の半導体ウェハの一部に熱
電対を用いたTEG部を設けても効果はほぼ同様であ
る。
Here, the thermocouple is formed on the entire surface of the wafer. However, as shown in FIG. 7, the effect is substantially the same even if a TEG portion using a thermocouple is provided in a part of a semiconductor wafer for product.

【0010】しかしながら、熱電対は一般に合金である
ことが多く、適用温度範囲が制限されていることが多
い。合金の場合、熱起電力は金属の混合比で物性値が左
右されるため図5に示したような微細加工で安定して特
性の熱電対を形成することが困難である。その場合の代
替案として図8に本発明の第二の実施例を示す。81は
温度変化による電気抵抗値の変化から温度を測定する温
度測定素子である。これはあらかじめ温度−素子材料の
電気抵抗値の関係を測定しておき、電気抵抗の値から温
度を測定するものである。低温から高温にわたって温度
測定素子として用いることができる金属としては白金が
知られている。白金であれば一種類の金属であり、スパ
ッタ等で安定した薄膜を形成することができる。作成工
程は第一の実施例における第一の金属膜Aの作成工程と
ほぼ同じである。ただし、熱電対の場合と異なり、ウェ
ハとは狭い接触面積で素子長を長く取るためつづら折れ
のパターンとすることが望ましい。使用温度が材料の耐
久温度以下であるならば白金以外の金属(ニッケル、
銅、アルミニウム等)、絶縁物(ダイヤモンド等)、半
導体(シリコン、ゲルマニウム等)を用いても同様であ
る。汚染やプロセスへの整合性を考慮するとなるべく製
品ウェハで使われているものを用いるのが望ましい。
[0010] However, thermocouples are generally alloys, and the application temperature range is often limited. In the case of an alloy, since the physical value of the thermoelectromotive force depends on the mixing ratio of the metal, it is difficult to form a thermocouple with stable characteristics by micromachining as shown in FIG. FIG. 8 shows a second embodiment of the present invention as an alternative in that case. Reference numeral 81 denotes a temperature measuring element for measuring a temperature from a change in electric resistance value due to a temperature change. In this method, the relationship between the temperature and the electric resistance value of the element material is measured in advance, and the temperature is measured from the electric resistance value. Platinum is known as a metal that can be used as a temperature measuring element from a low temperature to a high temperature. Platinum is one kind of metal, and a stable thin film can be formed by sputtering or the like. The forming process is almost the same as the forming process of the first metal film A in the first embodiment. However, unlike the case of a thermocouple, it is desirable to form a serpentine pattern in order to increase the element length with a small contact area with the wafer. If the operating temperature is below the endurance temperature of the material, metals other than platinum (nickel,
The same applies to the case where an insulator (such as diamond) or a semiconductor (such as silicon or germanium) is used. It is desirable to use the one used in the product wafer as much as possible in consideration of contamination and process compatibility.

【0011】[0011]

【発明の効果】本発明の温度測定素子を埋め込んだウェ
ハを用いることにより、次のような効果がある。RTA
プロセス構築用TEGウェハの全面、または一部に薄膜
状温度測定素子を作ることで、RTAプロセスのウェハ
温度面内均一性を確認、改善することが容易になる。装
置QC用のウェハの全面、または一部に薄膜状温度測定
素子を作ることで、日々の装置状態(ランプ劣化や治具
の曇りなど)による面内均一性の低下の確認も容易にな
る。また、製品ウェハの一部に薄膜状温度測定素子を作
ることによって装置QC用のダミーを特別に作成し、使
い捨てにすることによるコスト増加を抑制することがで
きる。
The following effects can be obtained by using the wafer in which the temperature measuring element of the present invention is embedded. RTA
By forming a thin-film temperature measuring element on the entire surface or a part of the TEG wafer for process construction, it is easy to confirm and improve the uniformity of the RTA process in the wafer temperature plane. By forming a thin-film temperature measuring element on the entire surface or a part of the wafer for the equipment QC, it is easy to confirm the deterioration of the in-plane uniformity due to the daily equipment state (deterioration of the lamp, fogging of the jig, etc.). Further, by forming a thin-film temperature measuring element on a part of the product wafer, a dummy for the device QC is specially prepared, and an increase in cost due to disposability can be suppressed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】熱電対埋め込み位置を示す模式図である。FIG. 1 is a schematic view showing a thermocouple embedding position.

【図2】Sensarray社製の熱電対埋め込みウェ
ハを用いたウェハ温度面内分布(5点)の測定例を示す
図である。
FIG. 2 is a diagram showing a measurement example of a wafer temperature in-plane distribution (5 points) using a thermocouple embedded wafer manufactured by Sensarray.

【図3】第一の実施例の説明図である。FIG. 3 is an explanatory diagram of the first embodiment.

【図4】第一の実施例で用いられる熱電対の断面図と平
面図である。
FIG. 4 is a sectional view and a plan view of a thermocouple used in the first embodiment.

【図5】第一の実施例に示した熱電対の形成方法を説明
する図である。
FIG. 5 is a diagram for explaining a method of forming the thermocouple shown in the first embodiment.

【図6】第一の実施例で、熱電対の一方が金属膜である
場合の例を示す図である。
FIG. 6 is a diagram showing an example in which one of the thermocouples is a metal film in the first embodiment.

【図7】製品ウェハに熱電対を作り込んだTEG部を設
けた例を示す図である。
FIG. 7 is a diagram showing an example in which a TEG unit incorporating a thermocouple is provided on a product wafer.

【図8】第二の実施例で用いられる温度測定素子の平面
図である。
FIG. 8 is a plan view of a temperature measuring element used in the second embodiment.

【符号の説明】[Explanation of symbols]

10…半導体ウェハ、11…L地点における温度プロフ
ァイルを測定するための熱電対、12…T地点における
温度プロファイルを測定するための熱電対、13…C地
点における温度プロファイルを測定するための熱電対、
14…B地点における温度プロファイルを測定するため
の熱電対、15…R地点における温度プロファイルを測
定するための熱電対、21…図1のL地点における温度
プロファイル、22…図1のT地点における温度プロフ
ァイル、23…図1のC地点における温度プロファイ
ル、24…図1のB地点における温度プロファイル、2
5…図1のR地点における温度プロファイル、26…図
1のL地点とC地点の温度差のプロファイル、27…図
1のT地点とC地点の温度差のプロファイル、28…図
1のB地点とC地点の温度差のプロファイル、29…図
1のR地点とC地点の温度差のプロファイル、31…熱
電対の1素子、32…熱電対からの信号を取り出すため
のパッド部、40…下地膜、41…金属膜A、42…金
属膜B、43…層間絶縁膜、44…金属膜A,B間の層
間絶縁膜、51…レジスト、52…コンタクトホール、
53…保護膜、71…熱電対を作り込んだTEG部、7
2…製品デバイス、81…電気抵抗値から温度を測定す
る薄膜。
10 semiconductor wafer, 11 thermocouple for measuring a temperature profile at point L, 12 thermocouple for measuring a temperature profile at point T, 13 thermocouple for measuring a temperature profile at point C,
14 thermocouple for measuring the temperature profile at point B, 15 thermocouple for measuring the temperature profile at point R, 21 temperature profile at point L in FIG. 1, 22 temperature at point T in FIG. Profile, 23: Temperature profile at point C in FIG. 1, 24: Temperature profile at point B in FIG. 1, 2
5: temperature profile at point R in FIG. 1; 26: profile of temperature difference between point L and point C in FIG. 1; 27: profile of temperature difference between point T and point C in FIG. 1; 28: point B in FIG. Profile of temperature difference between point C and point C, 29: Profile of temperature difference between point R and point C in FIG. 1, 31 element of thermocouple, 32 pad part for extracting signal from thermocouple, 40 bottom Ground film, 41: metal film A, 42: metal film B, 43: interlayer insulating film, 44: interlayer insulating film between metal films A, B, 51: resist, 52: contact hole,
53: Protective film, 71: TEG part incorporating thermocouple, 7
2: Product device, 81: Thin film for measuring temperature from electric resistance value.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 加藤 久幸 東京都小平市上水本町五丁目20番1号 株 式会社日立製作所半導体グループ内 Fターム(参考) 2F056 WA01 4M106 AA01 AA07 AB12 AD01 BA14 CA70 DH15  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hisayuki Kato 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 2F056 WA01 4M106 AA01 AA07 AB12 AD01 BA14 CA70 DH15

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 半導体ウェハの一部または全面に薄膜状
の熱電対と信号取り出しパッドを備えることを特徴とし
た半導体ウェハ。
1. A semiconductor wafer comprising a thin film thermocouple and a signal extraction pad on a part or the entire surface of the semiconductor wafer.
【請求項2】 半導体ウェハの一部または全面に電気抵
抗変化により温度を測定する薄膜状の温度測定素子と信
号取り出しパッドを備えることを特徴とした半導体ウェ
ハ。
2. A semiconductor wafer comprising a thin film-shaped temperature measuring element for measuring temperature by a change in electric resistance and a signal extraction pad on a part or the whole surface of the semiconductor wafer.
【請求項3】 半導体ウェハの一部または全面に薄膜状
の熱電対を備え、ウェハの端部に信号取り出しパッドを
備えることを特徴とした半導体ウェハ。
3. A semiconductor wafer comprising a thin-film thermocouple on a part or the entire surface of a semiconductor wafer, and a signal extraction pad at an end of the wafer.
【請求項4】 半導体ウェハの一部または全面に電気抵
抗変化により温度を測定する薄膜状の温度測定素子を備
え、ウェハの端部に信号取り出しパッドを備えることを
特徴とした半導体ウェハ。
4. A semiconductor wafer comprising: a thin film-shaped temperature measuring element for measuring a temperature by electric resistance change on a part or the whole surface of a semiconductor wafer; and a signal extraction pad at an end of the wafer.
【請求項5】 半導体ウェハが装置QCまたは製品開発
用のTEGウェハである請求項1から4に記載の半導体
ウェハ。
5. The semiconductor wafer according to claim 1, wherein the semiconductor wafer is a device QC or a TEG wafer for product development.
【請求項6】 半導体ウェハが製品デバイス製造用のウ
ェハで、デバイスの一部を請求項1から4に記載の薄膜
状温度測定素子に置き換えたことを特徴とする半導体ウ
ェハ。
6. A semiconductor wafer, wherein the semiconductor wafer is a wafer for manufacturing a product device, and a part of the device is replaced by the thin-film temperature measuring element according to claim 1.
JP2000196266A 2000-06-26 2000-06-26 Semiconductor wafer provided with processing temperature measuring method and temperature measuring method of semiconductor wafer Pending JP2002016117A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000196266A JP2002016117A (en) 2000-06-26 2000-06-26 Semiconductor wafer provided with processing temperature measuring method and temperature measuring method of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000196266A JP2002016117A (en) 2000-06-26 2000-06-26 Semiconductor wafer provided with processing temperature measuring method and temperature measuring method of semiconductor wafer

Publications (1)

Publication Number Publication Date
JP2002016117A true JP2002016117A (en) 2002-01-18

Family

ID=18694795

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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JP2005109454A (en) * 2003-09-09 2005-04-21 Seiko Instruments Inc Method of manufacturing semiconductor device
JP2005337750A (en) * 2004-05-24 2005-12-08 Komatsu Ltd Heat flux measuring substrate
JP2006053075A (en) * 2004-08-12 2006-02-23 Komatsu Ltd Temperature measuring device and substrate for temperature measurement
JP2007178253A (en) * 2005-12-28 2007-07-12 Tokyo Electron Ltd Device and method for measuring temperature
JP2007187619A (en) * 2006-01-16 2007-07-26 Tokyo Electron Ltd Wafer-type temperature sensor, temperature measuring device, thermal treatment apparatus and temperature measuring method
JP2008139067A (en) * 2006-11-30 2008-06-19 Dainippon Screen Mfg Co Ltd Temperature measuring substrate and temperature measuring system
US7648269B2 (en) 2006-06-07 2010-01-19 Fujitsu Microelectronics Limited Temperature measuring device for semiconductor manufacturing apparatus, method of measuring temperature in semiconductor manufacturing apparatus, and semiconductor manufacturing apparatus
US20210341342A1 (en) * 2020-03-19 2021-11-04 Changxin Memory Technologies, Inc. Methods for measuring temperature of wafer chuck and calibrating temperature and system for measuring temperature

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005109454A (en) * 2003-09-09 2005-04-21 Seiko Instruments Inc Method of manufacturing semiconductor device
JP2005337750A (en) * 2004-05-24 2005-12-08 Komatsu Ltd Heat flux measuring substrate
JP4563728B2 (en) * 2004-05-24 2010-10-13 株式会社小松製作所 Heat flux measurement board
JP2006053075A (en) * 2004-08-12 2006-02-23 Komatsu Ltd Temperature measuring device and substrate for temperature measurement
JP2007178253A (en) * 2005-12-28 2007-07-12 Tokyo Electron Ltd Device and method for measuring temperature
JP2007187619A (en) * 2006-01-16 2007-07-26 Tokyo Electron Ltd Wafer-type temperature sensor, temperature measuring device, thermal treatment apparatus and temperature measuring method
US7648269B2 (en) 2006-06-07 2010-01-19 Fujitsu Microelectronics Limited Temperature measuring device for semiconductor manufacturing apparatus, method of measuring temperature in semiconductor manufacturing apparatus, and semiconductor manufacturing apparatus
JP2008139067A (en) * 2006-11-30 2008-06-19 Dainippon Screen Mfg Co Ltd Temperature measuring substrate and temperature measuring system
US20210341342A1 (en) * 2020-03-19 2021-11-04 Changxin Memory Technologies, Inc. Methods for measuring temperature of wafer chuck and calibrating temperature and system for measuring temperature
US11852542B2 (en) * 2020-03-19 2023-12-26 Changxin Memory Technologies, Inc. Methods for measuring temperature of wafer chuck and calibrating temperature and system for measuring temperature

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